From 820f03ffe027367f275e9debb5f3f3376820ab37 Mon Sep 17 00:00:00 2001 From: Andrew Burgess Date: Mon, 21 Mar 2016 18:49:34 +0000 Subject: [PATCH] arc/nps400: Add additional instructions Adds the movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16, and crc32 instructions for the nps400 arc machine type. gas/ChangeLog: * testsuite/gas/arc/nps400-1.d: Update expected results. * testsuite/gas/arc/nps400-1.s: Additional test cases. opcodes/ChangeLog: * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16, and crc32 instructions. * arc-opc.c (arc_flag_operands): Add F_NPS_R. (arc_flag_classes): Add C_NPS_R. (insert_nps_bitop_size_2b): New function. (extract_nps_bitop_size_2b): Likewise. (insert_nps_bitop_uimm8): Likewise. (extract_nps_bitop_uimm8): Likewise. (arc_operands): Add new operand entries. --- gas/ChangeLog | 5 ++ gas/testsuite/gas/arc/nps400-1.d | 78 ++++++++++++++++++-- gas/testsuite/gas/arc/nps400-1.s | 60 ++++++++++++++++ opcodes/ChangeLog | 12 ++++ opcodes/arc-nps400-tbl.h | 112 +++++++++++++++++++++++++++++ opcodes/arc-opc.c | 119 ++++++++++++++++++++++++++++++- 6 files changed, 379 insertions(+), 7 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 53cf66aaf3..ec9c4e2cfb 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2016-04-05 Andrew Burgess + + * testsuite/gas/arc/nps400-1.d: Update expected results. + * testsuite/gas/arc/nps400-1.s: Additional test cases. + 2016-04-05 Claudiu Zissulescu * config/tc-arc.c (is_code_density_p): Compare directly the diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d index 294356a4e3..6d4bc8da2a 100644 --- a/gas/testsuite/gas/arc/nps400-1.d +++ b/gas/testsuite/gas/arc/nps400-1.d @@ -9,10 +9,78 @@ Disassembly of section .text: 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6 - c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6 - 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6 - 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6 + c: 4821 9485 movb\.cl r0,r1,0x4,0x5,0x6 + 10: 48c1 9485 movb\.cl r0,r14,0x4,0x5,0x6 + 14: 4d21 9485 movb\.cl r13,r1,0x4,0x5,0x6 18: 4808 04d2 movh r0,r0,0x4d2 1c: 4868 ffff movh r3,r3,0xffff - 20: 4818 04d2 movh.cl r0,0x4d2 - 24: 4878 ffff movh.cl r3,0xffff + 20: 4818 04d2 movh\.cl r0,0x4d2 + 24: 4878 ffff movh\.cl r3,0xffff + 28: 49cf 0906 movbi r14,r14,0x6,0x8,0x4 + 2c: 4aff 0174 movbi\.f r23,r23,0x14,0xb,0x1 + 30: 4bcf 864a movbi\.cl r30,0xa,0x12,0x2 + 34: 48df 8c09 movbi\.f\.cl r6,0x9,0,0x8 + 38: 4843 a845 decode1 r0,r0,r2,0x5,0xb + 3c: 4853 a845 decode1\.f r0,r0,r2,0x5,0xb + 40: 4843 d06b decode1\.cl r0,r2,0xb + 44: 4853 b472 decode1\.cl\.f r0,r2,0x12 + 48: 4963 b803 fbset r1,r1,r3,0x3,0xf + 4c: 4973 b803 fbset\.f r1,r1,r3,0x3,0xf + 50: 4a83 3803 fbclr r2,r2,r12,0x3,0xf + 54: 4b93 3803 fbclr\.f r3,r3,r12,0x3,0xf + 58: 4a24 0012 encode0 r2,r1,0x12,0x1 + 5c: 4814 7c00 encode0\.f r0,r0,0,0x20 + 60: 4a24 801f encode1 r2,r1,0x1f,0x1 + 64: 4814 fc00 encode1\.f r0,r0,0,0x20 + 68: 3c2e 150a rflt r10,r12,r20 + 6c: 3e2e 7500 1234 5678 rflt r0,0x12345678,r20 + 74: 3e2e 137e rflt 0,r14,r13 + 78: 3e2e 72be ffff ffff rflt 0,0xffffffff,r10 + 80: 3d6e 0044 rflt r4,r5,0x1 + 84: 3e6e 7083 1234 5678 rflt r3,0x12345678,0x2 + 8c: 396e 013e rflt 0,r1,0x4 + 90: 3e6e 707e ffff ffff rflt 0,0xffffffff,0x1 + 98: 3a33 00c1 crc16 r1,r2,r3 + 9c: 3e33 7144 ffff ffff crc16 r4,0xffffffff,r5 + a4: 3f33 0f86 ffff ffff crc16 r6,r7,0xffffffff + ac: 3e33 7f88 ffff ffff crc16 r8,0xffffffff,0xffffffff + b4: 3933 12be crc16 0,r9,r10 + b8: 3e33 72fe ffff ffff crc16 0,0xffffffff,r11 + c0: 3c33 1fbe ffff ffff crc16 0,r12,0xffffffff + c8: 3e73 1fcd crc16 r13,r14,0x3f + cc: 3e73 7fcf ffff ffff crc16 r15,0xffffffff,0x3f + d4: 3873 2ffe crc16 0,r16,0x3f + d8: 3e73 7ffe ffff ffff crc16 0,0xffffffff,0x3f + e0: 3a33 80c1 crc16\.r r1,r2,r3 + e4: 3e33 f144 ffff ffff crc16\.r r4,0xffffffff,r5 + ec: 3f33 8f86 ffff ffff crc16\.r r6,r7,0xffffffff + f4: 3e33 ff88 ffff ffff crc16\.r r8,0xffffffff,0xffffffff + fc: 3933 92be crc16\.r 0,r9,r10 + 100: 3e33 f2fe ffff ffff crc16\.r 0,0xffffffff,r11 + 108: 3c33 9fbe ffff ffff crc16\.r 0,r12,0xffffffff + 110: 3e73 9fcd crc16\.r r13,r14,0x3f + 114: 3e73 ffcf ffff ffff crc16\.r r15,0xffffffff,0x3f + 11c: 3873 affe crc16\.r 0,r16,0x3f + 120: 3e73 fffe ffff ffff crc16\.r 0,0xffffffff,0x3f + 128: 3a34 00c1 crc32 r1,r2,r3 + 12c: 3e34 7144 ffff ffff crc32 r4,0xffffffff,r5 + 134: 3f34 0f86 ffff ffff crc32 r6,r7,0xffffffff + 13c: 3e34 7f88 ffff ffff crc32 r8,0xffffffff,0xffffffff + 144: 3934 12be crc32 0,r9,r10 + 148: 3e34 72fe ffff ffff crc32 0,0xffffffff,r11 + 150: 3c34 1fbe ffff ffff crc32 0,r12,0xffffffff + 158: 3e74 1fcd crc32 r13,r14,0x3f + 15c: 3e74 7fcf ffff ffff crc32 r15,0xffffffff,0x3f + 164: 3874 2ffe crc32 0,r16,0x3f + 168: 3e74 7ffe ffff ffff crc32 0,0xffffffff,0x3f + 170: 3a34 80c1 crc32\.r r1,r2,r3 + 174: 3e34 f144 ffff ffff crc32\.r r4,0xffffffff,r5 + 17c: 3f34 8f86 ffff ffff crc32\.r r6,r7,0xffffffff + 184: 3e34 ff88 ffff ffff crc32\.r r8,0xffffffff,0xffffffff + 18c: 3934 92be crc32\.r 0,r9,r10 + 190: 3e34 f2fe ffff ffff crc32\.r 0,0xffffffff,r11 + 198: 3c34 9fbe ffff ffff crc32\.r 0,r12,0xffffffff + 1a0: 3e74 9fcd crc32\.r r13,r14,0x3f + 1a4: 3e74 ffcf ffff ffff crc32\.r r15,0xffffffff,0x3f + 1ac: 3874 affe crc32\.r 0,r16,0x3f + 1b0: 3e74 fffe ffff ffff crc32\.r 0,0xffffffff,0x3f diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s index 34d43d091d..0c7c108a40 100644 --- a/gas/testsuite/gas/arc/nps400-1.s +++ b/gas/testsuite/gas/arc/nps400-1.s @@ -10,3 +10,63 @@ movh r3, r3, 0xffff movh.cl r0, 1234 movh.cl r3, 0xffff + + /* movbi */ + movbi r14, r14, 6, 8, 4 + movbi.f r23, r23, 20, 11, 1 + movbi.cl r30, 10, 18, 2 + movbi.f.cl r6, 9, 0, 8 + + /* decode1 */ + decode1 r0, r0, r2, 5, 11 + decode1.f r0, r0, r2, 5, 11 + decode1.cl r0, r2, 11 + decode1.cl.f r0, r2, 18 + + /* fbset */ + fbset r1, r1, r3, 3, 15 + fbset.f r1, r1, r3, 3, 15 + + /* fbclear */ + fbclr r2, r2, r12, 3, 15 + fbclr.f r3, r3, r12, 3, 15 + + /* encode0 */ + encode0 r2, r1, 18, 1 + encode0.f r0, r0, 0, 32 + + /* encode1 */ + encode1 r2, r1, 31, 1 + encode1.f r0, r0, 0, 32 + + /* rflt */ + rflt r10,r12,r20 + rflt r0,0x12345678,r20 + rflt 0,r14,r13 + rflt 0,0xffffffff,r10 + rflt r4,r5,0x1 + rflt r3,0x12345678,0x2 + rflt 0,r1,0x4 + rflt 0,0xffffffff,0x1 + + .macro crc_test mnem + \mnem r1,r2,r3 + \mnem r4,0xffffffff,r5 + \mnem r6,r7,0xffffffff + \mnem r8,0xffffffff,0xffffffff + \mnem 0,r9,r10 + \mnem 0,0xffffffff,r11 + \mnem 0,r12,0xffffffff + \mnem r13,r14,0x3f + \mnem r15,0xffffffff,0x3f + \mnem 0,r16,0x3f + \mnem 0,0xffffffff,0x3f + .endm + + /* crc16 */ + crc_test crc16 + crc_test crc16.r + + /* crc32 */ + crc_test crc32 + crc_test crc32.r diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7dfe70736e..4ff1366984 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2016-04-05 Andrew Burgess + + * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, + encode1, rflt, crc16, and crc32 instructions. + * arc-opc.c (arc_flag_operands): Add F_NPS_R. + (arc_flag_classes): Add C_NPS_R. + (insert_nps_bitop_size_2b): New function. + (extract_nps_bitop_size_2b): Likewise. + (insert_nps_bitop_uimm8): Likewise. + (extract_nps_bitop_uimm8): Likewise. + (arc_operands): Add new operand entries. + 2016-04-05 Claudiu Zissulescu * arc-regs.h: Add a new subclass field. Add double assist diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 493c5b6584..dc7b066151 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -11,3 +11,115 @@ /* movb<.f><.cl> */ { "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, { "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, + +/* movbi<.f><.cl> */ +{ "movbi", 0x480f0000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B }, { C_NPS_F }}, +{ "movbi", 0x480f8000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B }, { C_NPS_F, C_NPS_CL }}, + +/* decode1<.f> */ +{ "decode1", 0x48038040, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, + +/* decode1.cl<.f> */ +{ "decode1", 0x48038060, 0xf80803e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS_SZ }, { C_NPS_CL, C_NPS_F }}, + +/* fbset<.f> */ +{ "fbset", 0x48038000, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, + +/* fbclr<.f> */ +{ "fbclr", 0x48030000, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, + +/* encode0<.f> */ +{ "encode0", 0x48040000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, + +/* encode1<.f> */ +{ "encode1", 0x48048000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, + +/* rflt a,b,c 00111bbb00101110FBBBCCCCCCAAAAAA */ +{ "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { 0 }}, + +/* rflt a,limm,c 0011111000101110F111CCCCCCAAAAAA */ +{ "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* rflt 0,b,c 00111bbb00101110FBBBCCCCCC111110 */ +{ "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { 0 }}, + +/* rflt 0,limm,c 0011111000101110F111CCCCCC111110 */ +{ "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* rflt a,b,u6 00111bbb01101110FBBBuuuuuuAAAAAA */ +{ "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, + +/* rflt a,limm,u6 0011111001101110F111uuuuuuAAAAAA */ +{ "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, + +/* rflt 0,b,u6 00111bbb01101110FBBBuuuuuu111110 */ +{ "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, + +/* rflt 0,limm,u6 0011111001101110F111uuuuuu111110 */ +{ "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, + +/* crc16<.r> a,b,c 00111bbb00110011RBBBCCCCCCAAAAAA */ +{ "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { C_NPS_R }}, + +/* crc16<.r> a,limm,c 0011111000110011R111CCCCCCAAAAAA */ +{ "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { C_NPS_R }}, + +/* crc16<.r> a,b,u6 00111bbb01110011RBBBuuuuuuAAAAAA */ +{ "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, UIMM6_20 }, { C_NPS_R }}, + +/* crc16<.r> 0,b,c 00111bbb00110011RBBBCCCCCC111110 */ +{ "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { C_NPS_R }}, + +/* crc16<.r> 0,limm,c 0011111000110011R111CCCCCC111110 */ +{ "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { C_NPS_R }}, + +/* crc16<.r> 0,b,u6 00111bbb01110011RBBBuuuuuu111110 */ +{ "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_R }}, + +/* crc16<.r> 0,b,limm 00111bbb00110011RBBB111110111110 */ +{ "crc16", 0x38330fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { C_NPS_R }}, + +/* crc16<.r> a,b,limm 00111bbb00110011RBBB111110AAAAAA */ +{ "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { C_NPS_R }}, + +/* crc16<.r> a,limm,limm 0011111000110011R111111110AAAAAA */ +{ "crc16", 0x3e337f80, 0xffff7fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { C_NPS_R }}, + +/* crc16<.r> a,limm,u6 0011111001110011R111uuuuuuAAAAAA */ +{ "crc16", 0x3e737000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_R }}, + +/* crc16<.r> 0,limm,u6 0011111001110011R111uuuuuu111110 */ +{ "crc16", 0x3e73703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, + +/* crc32<.r> a,b,c 00111 bbb 00 110100 R BBB CCCCCC AAAAAA */ +{ "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { C_NPS_R }}, + +/* crc32<.r> a,limm,c 00111 110 00 110100 R 111 CCCCCC AAAAAA */ +{ "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { C_NPS_R }}, + +/* crc32<.r> a,b,u6 00111 bbb 01 110100 R BBB uuuuuu AAAAAA */ +{ "crc32", 0x38740000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, UIMM6_20 }, { C_NPS_R }}, + +/* crc32<.r> 0,b,c 00111 bbb 00 110100 R BBB CCCCCC 111110 */ +{ "crc32", 0x3834003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { C_NPS_R }}, + +/* crc32<.r> 0,limm,c 00111 110 00 110100 R 111 CCCCCC 111110 */ +{ "crc32", 0x3e34703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { C_NPS_R }}, + +/* crc32<.r> 0,b,u6 00111 bbb 01 110100 R BBB uuuuuu 111110 */ +{ "crc32", 0x3874003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_R }}, + +/* crc32<.r> 0,b,limm 00111 bbb 00 110100 R BBB 111110 111110 */ +{ "crc32", 0x38340fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { C_NPS_R }}, + +/* crc32<.r> a,b,limm 00111 bbb 00 110100 R BBB 111110 AAAAAA */ +{ "crc32", 0x38340f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { C_NPS_R }}, + +/* crc32<.r> a,limm,limm 00111 110 00 110100 R 111 111110 AAAAAA */ +{ "crc32", 0x3e347f80, 0xffff7fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { C_NPS_R }}, + +/* crc32<.r> a,limm,u6 00111 110 01 110100 R 111 uuuuuu AAAAAA */ +{ "crc32", 0x3e747000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_R }}, + +/* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */ +{ "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index cecf60c39a..f182318865 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -741,6 +741,103 @@ extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED, return ((insn >> 10) & 0x1f) + 1; } +static unsigned +insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + switch (value) + { + case 1: + value = 0; + break; + case 2: + value = 1; + break; + case 4: + value = 2; + break; + case 8: + value = 3; + break; + default: + value = 0; + *errmsg = _("Invalid size, should be 1, 2, 4, or 8."); + break; + } + + insn |= value << 10; + return insn; +} + +static int +extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return 1 << ((insn >> 10) & 0x3); +} + +static unsigned +insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value >> 5) & 7) << 12; + insn |= (value & 0x1f); + return insn; +} + +static int +extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); +} + +static unsigned +insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + switch (value) + { + case 1: + case 2: + case 4: + break; + + default: + *errmsg = _("invalid immediate, must be 1, 2, or 4"); + value = 0; + } + + insn |= (value << 6); + return insn; +} + +static int +extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 6) & 0x3f; +} + +static unsigned +insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); + return insn; +} + +static int +extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x1f); +} + /* Include the generic extract/insert functions. Order is important as some of the functions present in the .h may be disabled via defines. */ @@ -903,6 +1000,9 @@ const struct arc_flag_operand arc_flag_operands[] = #define F_NPS_FLAG (F_NPS_CL + 1) { "f", 1, 1, 20, 1 }, + +#define F_NPS_R (F_NPS_FLAG + 1) + { "r", 1, 1, 15, 1 }, }; const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); @@ -981,6 +1081,9 @@ const struct arc_flag_class arc_flag_classes[] = #define C_NPS_F (C_NPS_CL + 1) { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, + +#define C_NPS_R (C_NPS_F + 1) + { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, }; /* The operands table. @@ -1323,10 +1426,22 @@ const struct arc_operand arc_operands[] = { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) - { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size }, + { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size }, -#define NPS_UIMM16 (NPS_BITOP_SIZE + 1) +#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) + { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, + +#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, + +#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) + { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, + +#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1) + { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, }; const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);