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gas: ARM: Fix encoding of VCVTr.s32.f64 instructions 

The direct rounding floating-point VCVT instructions introduced in
ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
set to 1 for all signed conversions.

gas/ChangeLog:

2014-01-17  Will Newton  <will.newton@linaro.org>

	* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
	for the s32.f64 flavours of VCVT.

gas/testsuite/ChangeLog:

2014-01-17  Will Newton  <will.newton@linaro.org>

	* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
This commit is contained in:
Will Newton 2014-01-16 10:08:45 +00:00
parent c7faa97a85
commit 827f64ffb5
4 changed files with 14 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2014-01-17 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
for the s32.f64 flavours of VCVT.
2014-01-14 Nick Clifton <nickc@redhat.com>
PR gas/16434

2
gas/config/tc-arm.c
View File

@ -14671,7 +14671,7 @@ do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
{
case neon_cvt_flavour_s32_f64:
sz = 1;
op = 0;
op = 1;
break;
case neon_cvt_flavour_s32_f32:
sz = 0;

4
gas/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2014-01-17 Will Newton <will.newton@linaro.org>
* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
For older changes see ChangeLog-2013
Copyright (C) 2014 Free Software Foundation, Inc.

8
gas/testsuite/gas/arm/armv8-a+fp.d
View File

@ -32,8 +32,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0
0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febc0bc0 vcvta.s32.f64 s0, d0
0[0-9a-f]+ <[^>]+> fefd0be0 vcvtn.s32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32 s0, s0
@ -86,8 +86,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0
0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febc 0bc0 vcvta.s32.f64 s0, d0
0[0-9a-f]+ <[^>]+> fefd 0be0 vcvtn.s32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
0[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32 s0, s0