2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
* opcodes/arc-dis.c:Add enum a4_decoding_class. (dsmOneArcInst): Use the enum values for the decoding class Remove redundant case in the switch for decodingClass value 11
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Ramana Radhakrishnan
parent
909cf6ea0e
commit
82b829a7d3
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@ -1,3 +1,9 @@
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2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
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* opcodes/arc-dis.c:Add enum a4_decoding_class.
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(dsmOneArcInst): Use the enum values for the decoding class
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Remove redundant case in the switch for decodingClass value 11
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2005-03-02 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
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@ -34,6 +34,29 @@
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#define dbg (0)
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#endif
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/* Classification of the opcodes for the decoder to print
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the instructions. */
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typedef enum {
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CLASS_A4_ARITH,
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CLASS_A4_OP3_GENERAL,
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CLASS_A4_FLAG,
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/* All branches other than JC. */
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CLASS_A4_BRANCH,
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CLASS_A4_JC ,
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/* All loads other than immediate
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indexed loads. */
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CLASS_A4_LD0,
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CLASS_A4_LD1,
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CLASS_A4_ST,
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CLASS_A4_SR,
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/* All single operand instructions. */
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CLASS_A4_OP3_SUBOPC3F,
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CLASS_A4_LR
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} a4_decoding_class;
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#define BIT(word,n) ((word) & (1 << n))
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#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
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#define OPCODE(word) (BITS ((word), 27, 31))
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@ -41,6 +64,7 @@
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#define FIELDB(word) (BITS ((word), 15, 20))
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#define FIELDC(word) (BITS ((word), 9, 14))
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/* FIELD D is signed in all of its uses, so we make sure argument is
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treated as signed for bit shifting purposes: */
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#define FIELDD(word) (BITS (((signed int)word), 0, 8))
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@ -531,7 +555,7 @@ dsmOneArcInst (addr, state)
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struct arcDisState * state;
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{
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int condCodeIsPartOfName = 0;
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int decodingClass;
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a4_decoding_class decodingClass;
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const char * instrName;
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int repeatsOp = 0;
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int fieldAisReg = 1;
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@ -572,7 +596,7 @@ dsmOneArcInst (addr, state)
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state->_opcode = OPCODE (state->words[0]);
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instrName = 0;
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decodingClass = 0; /* default! */
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decodingClass = CLASS_A4_ARITH; /* default! */
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repeatsOp = 0;
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condCodeIsPartOfName=0;
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state->commNum = 0;
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@ -606,14 +630,14 @@ dsmOneArcInst (addr, state)
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state->flow = invalid_instr;
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break;
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}
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decodingClass = 5;
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decodingClass = CLASS_A4_LD0;
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break;
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case op_LD1:
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if (BIT (state->words[0],13))
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{
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instrName = "lr";
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decodingClass = 10;
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decodingClass = CLASS_A4_LR;
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}
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else
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{
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@ -636,7 +660,7 @@ dsmOneArcInst (addr, state)
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state->flow = invalid_instr;
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break;
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}
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decodingClass = 6;
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decodingClass = CLASS_A4_LD1;
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}
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break;
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@ -644,7 +668,7 @@ dsmOneArcInst (addr, state)
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if (BIT (state->words[0],25))
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{
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instrName = "sr";
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decodingClass = 8;
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decodingClass = CLASS_A4_SR;
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}
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else
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{
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@ -664,17 +688,17 @@ dsmOneArcInst (addr, state)
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state->flow = invalid_instr;
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break;
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}
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decodingClass = 7;
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decodingClass = CLASS_A4_ST;
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}
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break;
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case op_3:
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decodingClass = 1; /* default for opcode 3... */
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decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */
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switch (FIELDC (state->words[0]))
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{
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case 0:
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instrName = "flag";
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decodingClass = 2;
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decodingClass = CLASS_A4_FLAG;
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break;
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case 1:
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instrName = "asr";
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@ -702,7 +726,7 @@ dsmOneArcInst (addr, state)
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break;
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case 0x3f:
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{
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decodingClass = 9;
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decodingClass = CLASS_A4_OP3_SUBOPC3F;
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switch( FIELDD (state->words[0]) )
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{
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case 0:
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@ -763,7 +787,7 @@ dsmOneArcInst (addr, state)
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}
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}
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condCodeIsPartOfName = 1;
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decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
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decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
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state->isBranch = 1;
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break;
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@ -771,7 +795,6 @@ dsmOneArcInst (addr, state)
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case op_ADC:
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case op_AND:
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repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
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decodingClass = 0;
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switch (state->_opcode)
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{
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@ -801,7 +824,7 @@ dsmOneArcInst (addr, state)
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{
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/* nop encoded as xor -1, -1, -1 */
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instrName = "nop";
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decodingClass = 9;
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decodingClass = CLASS_A4_OP3_SUBOPC3F;
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}
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else
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instrName = "xor";
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@ -828,7 +851,7 @@ dsmOneArcInst (addr, state)
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switch (decodingClass)
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{
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case 0:
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case CLASS_A4_ARITH:
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CHECK_FIELD_A ();
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CHECK_FIELD_B ();
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if (!repeatsOp)
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@ -857,7 +880,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 1:
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case CLASS_A4_OP3_GENERAL:
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CHECK_FIELD_A ();
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CHECK_FIELD_B ();
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CHECK_FLAG_COND_NULLIFY ();
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@ -879,7 +902,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 2:
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case CLASS_A4_FLAG:
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CHECK_FIELD_B ();
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CHECK_FLAG_COND_NULLIFY ();
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flag = 0; /* this is the FLAG instruction -- it's redundant */
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@ -890,7 +913,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 3:
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case CLASS_A4_BRANCH:
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fieldA = BITS (state->words[0],7,26) << 2;
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fieldA = (fieldA << 10) >> 10; /* make it signed */
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fieldA += addr + 4;
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@ -915,7 +938,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 4:
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case CLASS_A4_JC:
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/* For op_JC -- jump to address specified.
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Also covers jump and link--bit 9 of the instr. word
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selects whether linked, thus "is_linked" is set above. */
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@ -961,7 +984,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 5:
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case CLASS_A4_LD0:
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/* LD instruction.
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B and C can be regs, or one (both?) can be limm. */
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CHECK_FIELD_A ();
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@ -999,7 +1022,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 6:
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case CLASS_A4_LD1:
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/* LD instruction. */
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CHECK_FIELD_B ();
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CHECK_FIELD_A ();
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@ -1045,7 +1068,7 @@ dsmOneArcInst (addr, state)
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write_comments ();
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break;
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case 7:
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case CLASS_A4_ST:
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/* ST instruction. */
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CHECK_FIELD_B();
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CHECK_FIELD_C();
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@ -1090,7 +1113,8 @@ dsmOneArcInst (addr, state)
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fieldC, fieldB, fieldA);
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write_comments2(fieldA);
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break;
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case 8:
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case CLASS_A4_SR:
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/* SR instruction */
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CHECK_FIELD_B();
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CHECK_FIELD_C();
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@ -1105,12 +1129,12 @@ dsmOneArcInst (addr, state)
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write_comments();
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break;
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case 9:
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case CLASS_A4_OP3_SUBOPC3F:
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write_instr_name();
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state->operandBuffer[0] = '\0';
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break;
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case 10:
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case CLASS_A4_LR:
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/* LR instruction */
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CHECK_FIELD_A();
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CHECK_FIELD_B();
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@ -1125,11 +1149,6 @@ dsmOneArcInst (addr, state)
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write_comments();
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break;
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case 11:
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CHECK_COND();
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write_instr_name();
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state->operandBuffer[0] = '\0';
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break;
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default:
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mwerror (state, "Bad decoding class in ARC disassembler");
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