Fix problem where -relax could reorder multiple consecutive sets of the
same register: * coff-sh.c (USES1_REG, USES2_REG, SETS1_REG, SETS2_REG, USESF1_REG, USESF2_REG, SETSF1_REG, SETSF2_REG): New macros. * (sh_insn_sets_reg, sh_insn_sets_freg): New prototypes. * (sh_insn_sets_reg, sh_insn_uses_or_sets_reg, sh_insns_sets_freg, sh_insns_uses_or_sets_freg): New functions. * (sh_insn_uses_reg, sh_insn_uses_freg): Use new macros. * (sh_insns_conflict): Use new functions and new macros to detect conflicts when two instructions both set same integer registers, both set same fp register, and both set special register.
This commit is contained in:
Joern Rennecke
parent
09f99d3f44
commit
84dcfba7a2
@ -1,3 +1,15 @@
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Thu Feb 10 20:07:50 GMT 2000 Toshiyasu Morita (toshi.morita@sega.com)
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* coff-sh.c (USES1_REG, USES2_REG, SETS1_REG, SETS2_REG,
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USESF1_REG, USESF2_REG, SETSF1_REG, SETSF2_REG): New macros.
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* (sh_insn_sets_reg, sh_insn_sets_freg): New prototypes.
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* (sh_insn_sets_reg, sh_insn_uses_or_sets_reg, sh_insns_sets_freg,
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sh_insns_uses_or_sets_freg): New functions.
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* (sh_insn_uses_reg, sh_insn_uses_freg): Use new macros.
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* (sh_insns_conflict): Use new functions and new macros to
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detect conflicts when two instructions both set same integer registers,
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both set same fp register, and both set special register.
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2000-02-09 Timothy Wall <twall@cygnus.com>
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* coffgen.c (coff_real_object_p): Set arch/mach info prior to
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127
bfd/coff-sh.c
127
bfd/coff-sh.c
@ -1,5 +1,5 @@
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/* BFD back-end for Hitachi Super-H COFF binaries.
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Copyright 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
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Copyright 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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Written by Steve Chamberlain, <sac@cygnus.com>.
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Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
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@ -1384,10 +1384,12 @@ struct sh_opcode
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/* This instruction uses the value in the register in the field at
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mask 0x0f00 of the instruction. */
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#define USES1 (0x10)
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#define USES1_REG(x) ((x & 0x0f00) >> 8)
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/* This instruction uses the value in the register in the field at
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mask 0x00f0 of the instruction. */
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#define USES2 (0x20)
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#define USES2_REG(x) ((x & 0x00f0) >> 4)
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/* This instruction uses the value in register 0. */
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#define USESR0 (0x40)
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@ -1395,10 +1397,12 @@ struct sh_opcode
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/* This instruction sets the value in the register in the field at
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mask 0x0f00 of the instruction. */
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#define SETS1 (0x80)
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#define SETS1_REG(x) ((x & 0x0f00) >> 8)
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/* This instruction sets the value in the register in the field at
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mask 0x00f0 of the instruction. */
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#define SETS2 (0x100)
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#define SETS2_REG(x) ((x & 0x00f0) >> 4)
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/* This instruction sets register 0. */
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#define SETSR0 (0x200)
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@ -1412,10 +1416,12 @@ struct sh_opcode
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/* This instruction uses the floating point register in the field at
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mask 0x0f00 of the instruction. */
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#define USESF1 (0x1000)
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#define USESF1_REG(x) ((x & 0x0f00) >> 8)
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/* This instruction uses the floating point register in the field at
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mask 0x00f0 of the instruction. */
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#define USESF2 (0x2000)
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#define USESF2_REG(x) ((x & 0x00f0) >> 4)
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/* This instruction uses floating point register 0. */
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#define USESF0 (0x4000)
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@ -1423,11 +1429,20 @@ struct sh_opcode
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/* This instruction sets the floating point register in the field at
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mask 0x0f00 of the instruction. */
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#define SETSF1 (0x8000)
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#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
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static boolean sh_insn_uses_reg
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
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static boolean sh_insn_sets_reg
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
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static boolean sh_insn_uses_or_sets_reg
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
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static boolean sh_insn_uses_freg
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
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static boolean sh_insn_sets_freg
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
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static boolean sh_insn_uses_or_sets_freg
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
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static boolean sh_insns_conflict
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PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
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const struct sh_opcode *));
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@ -1860,6 +1875,20 @@ sh_insn_info (insn)
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return NULL;
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}
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/* See whether an instruction uses or sets a general purpose register */
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static boolean
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sh_insn_uses_or_sets_reg (insn, op, reg)
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unsigned int insn;
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const struct sh_opcode *op;
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unsigned int reg;
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{
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if (sh_insn_uses_reg (insn, op, reg))
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return true;
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return sh_insn_sets_reg (insn, op, reg);
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}
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/* See whether an instruction uses a general purpose register. */
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static boolean
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@ -1873,10 +1902,10 @@ sh_insn_uses_reg (insn, op, reg)
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f = op->flags;
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if ((f & USES1) != 0
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&& ((insn & 0x0f00) >> 8) == reg)
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&& USES1_REG (insn) == reg)
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return true;
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if ((f & USES2) != 0
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&& ((insn & 0x00f0) >> 4) == reg)
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&& USES2_REG (insn) == reg)
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return true;
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if ((f & USESR0) != 0
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&& reg == 0)
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@ -1884,6 +1913,44 @@ sh_insn_uses_reg (insn, op, reg)
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return false;
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}
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/* See whether an instruction sets a general purpose register. */
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static boolean
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sh_insn_sets_reg (insn, op, reg)
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unsigned int insn;
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const struct sh_opcode *op;
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unsigned int reg;
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{
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unsigned int f;
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f = op->flags;
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if ((f & SETS1) != 0
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&& SETS1_REG (insn) == reg)
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return true;
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if ((f & SETS2) != 0
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&& SETS2_REG (insn) == reg)
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return true;
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if ((f & SETSR0) != 0
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&& reg == 0)
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return true;
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return false;
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}
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/* See whether an instruction uses or sets a floating point register */
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static boolean
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sh_insn_uses_or_sets_freg (insn, op, reg)
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unsigned int insn;
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const struct sh_opcode *op;
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unsigned int reg;
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{
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if (sh_insn_uses_freg (insn, op, reg))
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return true;
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return sh_insn_sets_freg (insn, op, reg);
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}
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/* See whether an instruction uses a floating point register. */
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@ -1907,10 +1974,10 @@ sh_insn_uses_freg (insn, op, freg)
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bit of the register number. */
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if ((f & USESF1) != 0
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&& ((insn & 0x0e00) >> 8) == (freg & 0xe))
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&& (USESF1_REG (insn) & 0xe) == (freg & 0xe))
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return true;
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if ((f & USESF2) != 0
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&& ((insn & 0x00e0) >> 4) == (freg & 0xe))
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&& (USESF2_REG (insn) & 0xe) == (freg & 0xe))
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return true;
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if ((f & USESF0) != 0
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&& freg == 0)
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@ -1919,6 +1986,34 @@ sh_insn_uses_freg (insn, op, freg)
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return false;
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}
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/* See whether an instruction sets a floating point register. */
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static boolean
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sh_insn_sets_freg (insn, op, freg)
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unsigned int insn;
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const struct sh_opcode *op;
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unsigned int freg;
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{
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unsigned int f;
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f = op->flags;
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/* We can't tell if this is a double-precision insn, so just play safe
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and assume that it might be. So not only have we test FREG against
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itself, but also even FREG against FREG+1 - if the using insn uses
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just the low part of a double precision value - but also an odd
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FREG against FREG-1 - if the setting insn sets just the low part
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of a double precision value.
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So what this all boils down to is that we have to ignore the lowest
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bit of the register number. */
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if ((f & SETSF1) != 0
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&& (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
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return true;
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return false;
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}
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/* See whether instructions I1 and I2 conflict, assuming I1 comes
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before I2. OP1 and OP2 are the corresponding sh_opcode structures.
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This should return true if there is a conflict, or false if the
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@ -1946,35 +2041,35 @@ sh_insns_conflict (i1, op1, i2, op2)
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|| (f2 & (BRANCH | DELAY)) != 0)
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return true;
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if ((f1 & SETSSP) != 0 && (f2 & USESSP) != 0)
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return true;
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if ((f2 & SETSSP) != 0 && (f1 & USESSP) != 0)
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if (((f1 | f2) & SETSSP)
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&& (f1 & (SETSSP | USESSP))
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&& (f2 & (SETSSP | USESSP)))
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return true;
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if ((f1 & SETS1) != 0
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&& sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
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&& sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
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return true;
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if ((f1 & SETS2) != 0
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&& sh_insn_uses_reg (i2, op2, (i1 & 0x00f0) >> 4))
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&& sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
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return true;
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if ((f1 & SETSR0) != 0
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&& sh_insn_uses_reg (i2, op2, 0))
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&& sh_insn_uses_or_sets_reg (i2, op2, 0))
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return true;
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if ((f1 & SETSF1) != 0
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&& sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
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&& sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
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return true;
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if ((f2 & SETS1) != 0
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&& sh_insn_uses_reg (i1, op1, (i2 & 0x0f00) >> 8))
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&& sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
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return true;
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if ((f2 & SETS2) != 0
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&& sh_insn_uses_reg (i1, op1, (i2 & 0x00f0) >> 4))
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&& sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
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return true;
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if ((f2 & SETSR0) != 0
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&& sh_insn_uses_reg (i1, op1, 0))
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&& sh_insn_uses_or_sets_reg (i1, op1, 0))
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return true;
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if ((f2 & SETSF1) != 0
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&& sh_insn_uses_freg (i1, op1, (i2 & 0x0f00) >> 8))
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&& sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
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return true;
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/* The instructions do not conflict. */
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