PR22069, Several instances of register accidentally spelled as regsiter
PR 22069 binutils/ * od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming. cpu/ChangeLog * or1kcommon.cpu (spr-reg-info): Typo fix. include/ChangeLog * mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS): Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS. (MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS. opcodes/ChangeLog * cr16-opc.c (cr16_instruction): Comment typo fix. * hppa-dis.c (print_insn_hppa): Likewise. sim/ppc/ChangeLog * e500_registers.h: Comment typo fix. * ppc-instructions (ppc_insn_mfcr): Likewise.
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Alan Modra
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@ -1,3 +1,7 @@
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming.
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2018-05-08 Alan Modra <amodra@gmail.com>
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PR 23141
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@ -1688,7 +1688,7 @@ dump_unwind_encoding_x86 (unsigned int encoding, unsigned int sz,
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unsigned int regs;
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char pfx = sz == 8 ? 'R' : 'E';
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regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS;
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regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS
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printf (" %cSP frame", pfx);
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if (regs != 0)
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{
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@ -1,3 +1,7 @@
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* or1kcommon.cpu (spr-reg-info): Typo fix.
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2018-03-03 Alan Modra <amodra@gmail.com>
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* frv.opc: Include opintl.h.
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@ -170,7 +170,7 @@
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(SYS DCFGR #x007 "Debug configuration register")
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(SYS PCCFGR #x008 "Performance counters configuration register")
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(SYS NPC #x010 "Next program counter")
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(SYS SR #x011 "Supervision Regsiter")
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(SYS SR #x011 "Supervision Register")
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(SYS PPC #x012 "Previous program counter")
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(SYS FPCSR #x014 "Floating point control status register")
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(.unsplice
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@ -1,3 +1,10 @@
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
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Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
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(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
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MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
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2018-05-08 Jim Wilson <jimw@sifive.com>
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* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
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@ -37,7 +37,7 @@
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%rbp-2040 (offset is encoded in offset bits * 8). Registers saved are
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encoded in registers bits, 3 bits per register. */
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#define MACH_O_UNWIND_X86_64_MODE_RBP_FRAME 0x01000000
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#define MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS 0x00007FFF
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#define MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS 0x00007FFF
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#define MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET 0x00FF0000
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/* Frameless function, with a small stack size. */
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@ -75,7 +75,7 @@
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%ebp-240 (offset is encoded in offset bits * 4). Registers saved are
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encoded in registers bits, 3 bits per register. */
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#define MACH_O_UNWIND_X86_MODE_EBP_FRAME 0x01000000
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#define MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS 0x00007FFF
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#define MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS 0x00007FFF
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#define MACH_O_UNWIND_X86_EBP_FRAME_OFFSET 0x00FF0000
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/* Frameless function, with a small stack size. */
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@ -1,3 +1,8 @@
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* cr16-opc.c (cr16_instruction): Comment typo fix.
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* hppa-dis.c (print_insn_hppa): Likewise.
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2018-05-08 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
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@ -276,7 +276,7 @@ const inst cr16_instruction[] =
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{"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
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{"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
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/* Processor Regsiter Manipulation instructions */
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/* Processor Register Manipulation instructions */
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/* opc16 reg, preg */
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{"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}},
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/* opc16 regp, pregp */
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@ -425,7 +425,7 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
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fput_fp_reg (GET_FIELD (insn, 6, 10), info);
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break;
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/* 'fA' will not generate a space before the regsiter
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/* 'fA' will not generate a space before the register
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name. Normally that is fine. Except that it
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causes problems with xmpyu which has no FP format
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completer. */
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@ -1,3 +1,8 @@
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* e500_registers.h: Comment typo fix.
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* ppc-instructions (ppc_insn_mfcr): Likewise.
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2017-09-05 John Baldwin <jhb@FreeBSD.org>
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PR sim/20863
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@ -28,7 +28,7 @@ enum {
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msr_e500_spu_enable = BIT(38)
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};
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/* E500 regsiters. */
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/* E500 registers. */
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enum
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{
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@ -734,7 +734,7 @@ void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr,
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busy_ptr->nr_writebacks = 1;
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TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));
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# Schedule a MFCR instruction that moves the CR into an integer regsiter
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# Schedule a MFCR instruction that moves the CR into an integer register
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void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask
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const unsigned32 cr_mask = 0xff;
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model_busy *busy_ptr;
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