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PR22069, Several instances of register accidentally spelled as regsiter 

PR 22069
binutils/
	* od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming.
cpu/ChangeLog
	* or1kcommon.cpu (spr-reg-info): Typo fix.
include/ChangeLog
	* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
	Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
	(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
	MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
opcodes/ChangeLog
	* cr16-opc.c (cr16_instruction): Comment typo fix.
	* hppa-dis.c (print_insn_hppa): Likewise.
sim/ppc/ChangeLog
	* e500_registers.h: Comment typo fix.
	* ppc-instructions (ppc_insn_mfcr): Likewise.
This commit is contained in:
Alan Modra 2018-05-09 15:50:29 +09:30
parent a7287b941e
commit 84f9f8c330
12 changed files with 33 additions and 8 deletions
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4
binutils/ChangeLog
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@ -1,3 +1,7 @@
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming.
2018-05-08 Alan Modra <amodra@gmail.com> 2018-05-08 Alan Modra <amodra@gmail.com>
PR 23141 PR 23141

2
binutils/od-macho.c
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@ -1688,7 +1688,7 @@ dump_unwind_encoding_x86 (unsigned int encoding, unsigned int sz,
unsigned int regs; unsigned int regs;
char pfx = sz == 8 ? 'R' : 'E'; char pfx = sz == 8 ? 'R' : 'E';
regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS; regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS
printf (" %cSP frame", pfx); printf (" %cSP frame", pfx);
if (regs != 0) if (regs != 0)
{ {

4
cpu/ChangeLog
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@ -1,3 +1,7 @@
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* or1kcommon.cpu (spr-reg-info): Typo fix.
2018-03-03 Alan Modra <amodra@gmail.com> 2018-03-03 Alan Modra <amodra@gmail.com>
* frv.opc: Include opintl.h. * frv.opc: Include opintl.h.

2
cpu/or1kcommon.cpu
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@ -170,7 +170,7 @@
(SYS DCFGR #x007 "Debug configuration register") (SYS DCFGR #x007 "Debug configuration register")
(SYS PCCFGR #x008 "Performance counters configuration register") (SYS PCCFGR #x008 "Performance counters configuration register")
(SYS NPC #x010 "Next program counter") (SYS NPC #x010 "Next program counter")
(SYS SR #x011 "Supervision Regsiter") (SYS SR #x011 "Supervision Register")
(SYS PPC #x012 "Previous program counter") (SYS PPC #x012 "Previous program counter")
(SYS FPCSR #x014 "Floating point control status register") (SYS FPCSR #x014 "Floating point control status register")
(.unsplice (.unsplice

7
include/ChangeLog
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@ -1,3 +1,10 @@
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
2018-05-08 Jim Wilson <jimw@sifive.com> 2018-05-08 Jim Wilson <jimw@sifive.com>
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.

4
include/mach-o/unwind.h
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@ -37,7 +37,7 @@
%rbp-2040 (offset is encoded in offset bits * 8). Registers saved are %rbp-2040 (offset is encoded in offset bits * 8). Registers saved are
encoded in registers bits, 3 bits per register. */ encoded in registers bits, 3 bits per register. */
#define MACH_O_UNWIND_X86_64_MODE_RBP_FRAME 0x01000000 #define MACH_O_UNWIND_X86_64_MODE_RBP_FRAME 0x01000000
#define MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS 0x00007FFF #define MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS 0x00007FFF
#define MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET 0x00FF0000 #define MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET 0x00FF0000
/* Frameless function, with a small stack size. */ /* Frameless function, with a small stack size. */
@ -75,7 +75,7 @@
%ebp-240 (offset is encoded in offset bits * 4). Registers saved are %ebp-240 (offset is encoded in offset bits * 4). Registers saved are
encoded in registers bits, 3 bits per register. */ encoded in registers bits, 3 bits per register. */
#define MACH_O_UNWIND_X86_MODE_EBP_FRAME 0x01000000 #define MACH_O_UNWIND_X86_MODE_EBP_FRAME 0x01000000
#define MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS 0x00007FFF #define MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS 0x00007FFF
#define MACH_O_UNWIND_X86_EBP_FRAME_OFFSET 0x00FF0000 #define MACH_O_UNWIND_X86_EBP_FRAME_OFFSET 0x00FF0000
/* Frameless function, with a small stack size. */ /* Frameless function, with a small stack size. */

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* cr16-opc.c (cr16_instruction): Comment typo fix.
* hppa-dis.c (print_insn_hppa): Likewise.
2018-05-08 Jim Wilson <jimw@sifive.com> 2018-05-08 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.

2
opcodes/cr16-opc.c
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@ -276,7 +276,7 @@ const inst cr16_instruction[] =
{"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, {"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
{"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
/* Processor Regsiter Manipulation instructions */ /* Processor Register Manipulation instructions */
/* opc16 reg, preg */ /* opc16 reg, preg */
{"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}}, {"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}},
/* opc16 regp, pregp */ /* opc16 regp, pregp */

2
opcodes/hppa-dis.c
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@ -425,7 +425,7 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
fput_fp_reg (GET_FIELD (insn, 6, 10), info); fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break; break;
/* 'fA' will not generate a space before the regsiter /* 'fA' will not generate a space before the register
name. Normally that is fine. Except that it name. Normally that is fine. Except that it
causes problems with xmpyu which has no FP format causes problems with xmpyu which has no FP format
completer. */ completer. */

5
sim/ppc/ChangeLog
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@ -1,3 +1,8 @@
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* e500_registers.h: Comment typo fix.
* ppc-instructions (ppc_insn_mfcr): Likewise.
2017-09-05 John Baldwin <jhb@FreeBSD.org> 2017-09-05 John Baldwin <jhb@FreeBSD.org>
PR sim/20863 PR sim/20863

2
sim/ppc/e500_registers.h
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@ -28,7 +28,7 @@ enum {
msr_e500_spu_enable = BIT(38) msr_e500_spu_enable = BIT(38)
}; };
/* E500 regsiters. */ /* E500 registers. */
enum enum
{ {

2
sim/ppc/ppc-instructions
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@ -734,7 +734,7 @@ void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr,
busy_ptr->nr_writebacks = 1; busy_ptr->nr_writebacks = 1;
TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR))); TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));
# Schedule a MFCR instruction that moves the CR into an integer regsiter # Schedule a MFCR instruction that moves the CR into an integer register
void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask
const unsigned32 cr_mask = 0xff; const unsigned32 cr_mask = 0xff;
model_busy *busy_ptr; model_busy *busy_ptr;