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Add AMD SSE5 support

This commit is contained in:
Michael Meissner 2007-09-14 18:21:09 +00:00
parent 4a543daf06
commit 85f10a010c
17 changed files with 13544 additions and 2416 deletions
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5
binutils/ChangeLog
View File

@ -1,3 +1,8 @@
2007-08-31 Michael Meissner <michael.meissner@amd.com>
Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* NEWS: Add note about SSE5 being added on i386.
2007-09-13 Alan Modra <amodra@bigpond.net.au>
Zhou Drangon <drangon.mail@gmail.com>

2
binutils/NEWS
View File

@ -1,4 +1,6 @@
-*- text -*-
* Support for SSE5 has been added to the i386 port.
* Added -p switch to readelf to allow string dumps of sections.
Changes in 2.18:

35
gas/ChangeLog
View File

@ -1,3 +1,38 @@
2007-08-31 Michael Meissner <michael.meissner@amd.com>
Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Tony Linthicum <tony.linthicum@amd.com>
* NEWS: Add SSE5 support to NEWS file.
* config/tc-i386.h (drex_byte): Add fields to allow process_drex
and build_modrm_byte to communicate.
(DREX_OC0): New SSE5 macro.
(DREX_OC0_MASK): Ditto.
(DREX_OC1): Ditto.
(DREX_OC1_MASK): Ditto.
(DREX_XMEM_X1_X2_X2): Ditto.
(DREX_X1_XMEM_X2_X2): Ditto.
(DREX_X1_XMEM_X2_X1: Ditto.
(DREX_X1_X2_XMEM_X1: Ditto.
(DREX_XMEM_X1_X2): Ditto.
(DREX_X1_XMEM_X2): Ditto.
(drex_byte): New structure to describe the DREX byte.
* config/tc-i386.c (process_drex): New function to handle SSE5
DREX bits.
(build_modrm_byte): Use the information cached away in
process_drex in the case of DREX instructions.
(i386_insn): Add drex field.
(pi): Add debugging of drex field.
(md_assemble): Treat SSE5 like SSE3 in instructions with an
immediate byte. Move REX field to DREX if this is a DREX
instruction.
(process_operands): Add SSE5 support.
(build_modrm_byte): Ditto.
(output_insn): Ditto.
(cpu_arch): Ditto.
(i386_align_code): Ditto.
2007-09-12 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (md_assemble): Move handling of extrq/insertq

2
gas/NEWS
View File

@ -1,4 +1,6 @@
-*- text -*-
* Support for SSE5 has been added to the i386 port.
Changes in 2.18:
* The GAS sources are now released under the GPLv3.

453
gas/config/tc-i386.c
View File

@ -89,6 +89,7 @@ static int check_long_reg (void);
static int check_qword_reg (void);
static int check_word_reg (void);
static int finalize_imm (void);
static void process_drex (void);
static int process_operands (void);
static const seg_entry *build_modrm_byte (void);
static void output_insn (void);
@ -161,11 +162,13 @@ struct _i386_insn
unsigned char prefix[MAX_PREFIXES];
/* RM and SIB are the modrm byte and the sib byte where the
addressing modes of this insn are encoded. */
addressing modes of this insn are encoded. DREX is the byte
added by the SSE5 instructions. */
modrm_byte rm;
rex_byte rex;
sib_byte sib;
drex_byte drex;
};
typedef struct _i386_insn i386_insn;
@ -508,6 +511,8 @@ static const arch_entry cpu_arch[] =
CPU_SSE4A_FLAGS },
{".abm", PROCESSOR_UNKNOWN,
CPU_ABM_FLAGS },
{".sse5", PROCESSOR_UNKNOWN,
CPU_SSE5_FLAGS },
};
const pseudo_typeS md_pseudo_table[] =
@ -1767,6 +1772,8 @@ pi (char *line, i386_insn *x)
(x->rex & REX_R) != 0,
(x->rex & REX_X) != 0,
(x->rex & REX_B) != 0);
fprintf (stdout, " drex: reg %d rex 0x%x\n",
x->drex.reg, x->drex.rex);
for (i = 0; i < x->operands; i++)
{
fprintf (stdout, " #%d: ", i + 1);
@ -2254,9 +2261,14 @@ md_assemble (line)
/* These AMD 3DNow! and Intel Katmai New Instructions have an
opcode suffix which is coded in the same place as an 8-bit
immediate field would be. Here we fake an 8-bit immediate
operand from the opcode suffix stored in tm.extension_opcode. */
operand from the opcode suffix stored in tm.extension_opcode.
SSE5 also uses this encoding, for some of its 3 argument
instructions. */
assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
assert (i.imm_operands == 0
&& (i.operands <= 2
|| (i.tm.cpu_flags.bitfield.cpusse5
&& i.operands <= 3)));
exp = &im_expressions[i.imm_operands++];
i.op[i.operands].imms = exp;
@ -2338,7 +2350,14 @@ md_assemble (line)
}
}
if (i.rex != 0)
/* If the instruction has the DREX attribute (aka SSE5), don't emit a
REX prefix. */
if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
{
i.drex.rex = i.rex;
i.rex = 0;
}
else if (i.rex != 0)
add_prefix (REX_OPCODE | i.rex);
/* We are ready to output the insn. */
@ -3859,6 +3878,336 @@ finalize_imm (void)
return 1;
}
static void
process_drex (void)
{
i.drex.modrm_reg = None;
i.drex.modrm_regmem = None;
/* SSE5 4 operand instructions must have the destination the same as
one of the inputs. Figure out the destination register and cache
it away in the drex field, and remember which fields to use for
the modrm byte. */
if (i.tm.opcode_modifier.drex
&& i.tm.opcode_modifier.drexv
&& i.operands == 4)
{
i.tm.extension_opcode = None;
/* Case 1: 4 operand insn, dest = src1, src3 = register. */
if (i.types[0].bitfield.regxmm != 0
&& i.types[1].bitfield.regxmm != 0
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0
&& i.op[0].regs->reg_num == i.op[3].regs->reg_num
&& i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* Clear the arguments that are stored in drex. */
UINTS_CLEAR (i.types[0]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* There are two different ways to encode a 4 operand
instruction with all registers that uses OC1 set to
0 or 1. Favor setting OC1 to 0 since this mimics the
actions of other SSE5 assemblers. Use modrm encoding 2
for register/register. Include the high order bit that
is normally stored in the REX byte in the register
field. */
i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
i.drex.modrm_reg = 2;
i.drex.modrm_regmem = 1;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 2: 4 operand insn, dest = src1, src3 = memory. */
else if (i.types[0].bitfield.regxmm != 0
&& i.types[1].bitfield.regxmm != 0
&& (i.types[2].bitfield.regxmm
|| operand_type_check (i.types[2], anymem))
&& i.types[3].bitfield.regxmm != 0
&& i.op[0].regs->reg_num == i.op[3].regs->reg_num
&& i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* clear the arguments that are stored in drex */
UINTS_CLEAR (i.types[0]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* Specify the modrm encoding for memory addressing. Include
the high order bit that is normally stored in the REX byte
in the register field. */
i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
i.drex.modrm_reg = 1;
i.drex.modrm_regmem = 2;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 3: 4 operand insn, dest = src1, src2 = memory. */
else if (i.types[0].bitfield.regxmm != 0
&& operand_type_check (i.types[1], anymem) != 0
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0
&& i.op[0].regs->reg_num == i.op[3].regs->reg_num
&& i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* Clear the arguments that are stored in drex. */
UINTS_CLEAR (i.types[0]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* Specify the modrm encoding for memory addressing. Include
the high order bit that is normally stored in the REX byte
in the register field. */
i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
i.drex.modrm_reg = 2;
i.drex.modrm_regmem = 1;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 4: 4 operand insn, dest = src3, src2 = register. */
else if (i.types[0].bitfield.regxmm != 0
&& i.types[1].bitfield.regxmm != 0
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0
&& i.op[2].regs->reg_num == i.op[3].regs->reg_num
&& i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* clear the arguments that are stored in drex */
UINTS_CLEAR (i.types[2]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* There are two different ways to encode a 4 operand
instruction with all registers that uses OC1 set to
0 or 1. Favor setting OC1 to 0 since this mimics the
actions of other SSE5 assemblers. Use modrm encoding
2 for register/register. Include the high order bit that
is normally stored in the REX byte in the register
field. */
i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
i.drex.modrm_reg = 1;
i.drex.modrm_regmem = 0;
/* Remember the register, including the upper bits */
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 5: 4 operand insn, dest = src3, src2 = memory. */
else if (i.types[0].bitfield.regxmm != 0
&& (i.types[1].bitfield.regxmm
|| operand_type_check (i.types[1], anymem))
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0
&& i.op[2].regs->reg_num == i.op[3].regs->reg_num
&& i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* Clear the arguments that are stored in drex. */
UINTS_CLEAR (i.types[2]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* Specify the modrm encoding and remember the register
including the bits normally stored in the REX byte. */
i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
i.drex.modrm_reg = 0;
i.drex.modrm_regmem = 1;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 6: 4 operand insn, dest = src3, src1 = memory. */
else if (operand_type_check (i.types[0], anymem) != 0
&& i.types[1].bitfield.regxmm != 0
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0
&& i.op[2].regs->reg_num == i.op[3].regs->reg_num
&& i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* clear the arguments that are stored in drex */
UINTS_CLEAR (i.types[2]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* Specify the modrm encoding and remember the register
including the bits normally stored in the REX byte. */
i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
i.drex.modrm_reg = 1;
i.drex.modrm_regmem = 0;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
else
as_bad (_("Incorrect operands for the '%s' instruction"),
i.tm.name);
}
/* SSE5 instructions with the DREX byte where the only memory operand
is in the 2nd argument, and the first and last xmm register must
match, and is encoded in the DREX byte. */
else if (i.tm.opcode_modifier.drex
&& !i.tm.opcode_modifier.drexv
&& i.operands == 4)
{
/* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
if (i.types[0].bitfield.regxmm != 0
&& (i.types[1].bitfield.regxmm
|| operand_type_check(i.types[1], anymem))
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0
&& i.op[0].regs->reg_num == i.op[3].regs->reg_num
&& i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
{
/* clear the arguments that are stored in drex */
UINTS_CLEAR (i.types[0]);
UINTS_CLEAR (i.types[3]);
i.reg_operands -= 2;
/* Specify the modrm encoding and remember the register
including the high bit normally stored in the REX
byte. */
i.drex.modrm_reg = 2;
i.drex.modrm_regmem = 1;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
else
as_bad (_("Incorrect operands for the '%s' instruction"),
i.tm.name);
}
/* SSE5 3 operand instructions that the result is a register, being
either operand can be a memory operand, using OC0 to note which
one is the memory. */
else if (i.tm.opcode_modifier.drex
&& i.tm.opcode_modifier.drexv
&& i.operands == 3)
{
i.tm.extension_opcode = None;
/* Case 1: 3 operand insn, src1 = register. */
if (i.types[0].bitfield.regxmm != 0
&& i.types[1].bitfield.regxmm != 0
&& i.types[2].bitfield.regxmm != 0)
{
/* Clear the arguments that are stored in drex. */
UINTS_CLEAR (i.types[2]);
i.reg_operands--;
/* Specify the modrm encoding and remember the register
including the high bit normally stored in the REX byte. */
i.tm.extension_opcode = DREX_XMEM_X1_X2;
i.drex.modrm_reg = 1;
i.drex.modrm_regmem = 0;
i.drex.reg = (i.op[2].regs->reg_num
+ ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 2: 3 operand insn, src1 = memory. */
else if (operand_type_check (i.types[0], anymem) != 0
&& i.types[1].bitfield.regxmm != 0
&& i.types[2].bitfield.regxmm != 0)
{
/* Clear the arguments that are stored in drex. */
UINTS_CLEAR (i.types[2]);
i.reg_operands--;
/* Specify the modrm encoding and remember the register
including the high bit normally stored in the REX
byte. */
i.tm.extension_opcode = DREX_XMEM_X1_X2;
i.drex.modrm_reg = 1;
i.drex.modrm_regmem = 0;
i.drex.reg = (i.op[2].regs->reg_num
+ ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 3: 3 operand insn, src2 = memory. */
else if (i.types[0].bitfield.regxmm != 0
&& operand_type_check (i.types[1], anymem) != 0
&& i.types[2].bitfield.regxmm != 0)
{
/* Clear the arguments that are stored in drex. */
UINTS_CLEAR (i.types[2]);
i.reg_operands--;
/* Specify the modrm encoding and remember the register
including the high bit normally stored in the REX byte. */
i.tm.extension_opcode = DREX_X1_XMEM_X2;
i.drex.modrm_reg = 0;
i.drex.modrm_regmem = 1;
i.drex.reg = (i.op[2].regs->reg_num
+ ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
}
else
as_bad (_("Incorrect operands for the '%s' instruction"),
i.tm.name);
}
/* SSE5 4 operand instructions that are the comparison instructions
where the first operand is the immediate value of the comparison
to be done. */
else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
{
/* Case 1: 4 operand insn, src1 = reg/memory. */
if (operand_type_check (i.types[0], imm) != 0
&& (i.types[1].bitfield.regxmm
|| operand_type_check (i.types[1], anymem))
&& i.types[2].bitfield.regxmm != 0
&& i.types[3].bitfield.regxmm != 0)
{
/* clear the arguments that are stored in drex */
UINTS_CLEAR (i.types[3]);
i.reg_operands--;
/* Specify the modrm encoding and remember the register
including the high bit normally stored in the REX byte. */
i.drex.modrm_reg = 2;
i.drex.modrm_regmem = 1;
i.drex.reg = (i.op[3].regs->reg_num
+ ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
}
/* Case 2: 3 operand insn with ImmExt that places the
opcode_extension as an immediate argument. This is used for
all of the varients of comparison that supplies the appropriate
value as part of the instruction. */
else if ((i.types[0].bitfield.regxmm
|| operand_type_check (i.types[0], anymem))
&& i.types[1].bitfield.regxmm != 0
&& i.types[2].bitfield.regxmm != 0
&& operand_type_check (i.types[3], imm) != 0)
{
/* clear the arguments that are stored in drex */
UINTS_CLEAR (i.types[2]);
i.reg_operands--;
/* Specify the modrm encoding and remember the register
including the high bit normally stored in the REX byte. */
i.drex.modrm_reg = 1;
i.drex.modrm_regmem = 0;
i.drex.reg = (i.op[2].regs->reg_num
+ ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
}
else
as_bad (_("Incorrect operands for the '%s' instruction"),
i.tm.name);
}
else if (i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv
|| i.tm.opcode_modifier.drexc)
as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
}
static int
process_operands (void)
{
@ -3867,6 +4216,12 @@ process_operands (void)
unnecessary segment overrides. */
const seg_entry *default_seg = 0;
/* Handle all of the DREX munging that SSE5 needs. */
if (i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv
|| i.tm.opcode_modifier.drexc)
process_drex ();
/* The imul $imm, %reg instruction is converted into
imul $imm, %reg, %reg, and the clr %reg instruction
is converted into xor %reg, %reg. */
@ -3937,7 +4292,8 @@ process_operands (void)
}
else
{
/* The register or float register operand is in operand 0 or 1. */
/* The register or float register operand is in operand
0 or 1. */
unsigned int op;
if (i.types[0].bitfield.floatreg
@ -4011,9 +4367,30 @@ build_modrm_byte (void)
{
const seg_entry *default_seg = 0;
/* SSE5 4 operand instructions are encoded in such a way that one of
the inputs must match the destination register. Process_drex hides
the 3rd argument in the drex field, so that by the time we get
here, it looks to GAS as if this is a 2 operand instruction. */
if ((i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv
|| i.tm.opcode_modifier.drexc) != 0
&& i.reg_operands == 2)
{
const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
i.rm.reg = reg->reg_num;
i.rm.regmem = regmem->reg_num;
i.rm.mode = 3;
if ((reg->reg_flags & RegRex) != 0)
i.rex |= REX_R;
if ((regmem->reg_flags & RegRex) != 0)
i.rex |= REX_B;
}
/* i.reg_operands MUST be the number of real register operands;
implicit registers do not count. */
if (i.reg_operands == 2)
else if (i.reg_operands == 2)
{
unsigned int source, dest;
@ -4091,10 +4468,19 @@ build_modrm_byte (void)
unsigned int fake_zero_displacement = 0;
unsigned int op;
/* This has been precalculated for SSE5 instructions
that have a DREX field earlier in process_drex. */
if ((i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv
|| i.tm.opcode_modifier.drexc) != 0)
op = i.drex.modrm_regmem;
else
{
for (op = 0; op < i.operands; op++)
if (operand_type_check (i.types[op], anymem))
break;
assert (op < i.operands);
}
default_seg = &ds;
@ -4241,7 +4627,8 @@ build_modrm_byte (void)
extra modrm byte. */
i.sib.index = NO_INDEX_REGISTER;
#if !SCALE1_WHEN_NO_INDEX
/* Another case where we force the second modrm byte. */
/* Another case where we force the second
modrm byte. */
if (i.log2_scale_factor)
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
#endif
@ -4286,6 +4673,19 @@ build_modrm_byte (void)
{
unsigned int op;
/* This has been precalculated for SSE5 instructions
that have a DREX field earlier in process_drex. */
if ((i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv
|| i.tm.opcode_modifier.drexc) != 0)
{
op = i.drex.modrm_reg;
i.rm.reg = i.op[op].regs->reg_num;
if ((i.op[op].regs->reg_flags & RegRex) != 0)
i.rex |= REX_R;
}
else
{
for (op = 0; op < i.operands; op++)
if (i.types[op].bitfield.reg8
|| i.types[op].bitfield.reg16
@ -4301,8 +4701,8 @@ build_modrm_byte (void)
break;
assert (op < i.operands);
/* If there is an extension opcode to put here, the register
number must be put into the regmem field. */
/* If there is an extension opcode to put here, the
register number must be put into the regmem field. */
if (i.tm.extension_opcode != None)
{
i.rm.regmem = i.op[op].regs->reg_num;
@ -4315,6 +4715,7 @@ build_modrm_byte (void)
if ((i.op[op].regs->reg_flags & RegRex) != 0)
i.rex |= REX_R;
}
}
/* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
must set it to 3 to indicate this is a register operand
@ -4324,7 +4725,10 @@ build_modrm_byte (void)
}
/* Fill in i.rm.reg field with extension opcode (if any). */
if (i.tm.extension_opcode != None)
if (i.tm.extension_opcode != None
&& !(i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv
|| i.tm.opcode_modifier.drexc))
i.rm.reg = i.tm.extension_opcode;
}
return default_seg;
@ -4569,10 +4973,12 @@ output_insn (void)
int opc_3b;
/* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
SSE4 instructions have 3 bytes. We may use one more higher
byte to specify a prefix the instruction requires. Exclude
instructions which are in both SSE4.2 and ABM. */
SSE4 and SSE5 instructions have 3 bytes. We may use one
more higher byte to specify a prefix the instruction
requires. Exclude instructions which are in both SSE4.2
and ABM. */
opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
|| i.tm.cpu_flags.bitfield.cpusse5
|| i.tm.cpu_flags.bitfield.cpusse4_1
|| (i.tm.cpu_flags.bitfield.cpusse4_2
&& !i.tm.cpu_flags.bitfield.cpuabm));
@ -4628,6 +5034,13 @@ output_insn (void)
/* Put out high byte first: can't use md_number_to_chars! */
*p++ = (i.tm.base_opcode >> 8) & 0xff;
*p = i.tm.base_opcode & 0xff;
/* On SSE5, encode the OC1 bit in the DREX field if this
encoding has multiple formats. */
if (i.tm.opcode_modifier.drex
&& i.tm.opcode_modifier.drexv
&& DREX_OC1 (i.tm.extension_opcode))
*p |= DREX_OC1_MASK;
}
/* Now the modrm byte and sib byte (if present). */
@ -4656,6 +5069,20 @@ output_insn (void)
}
}
/* Write the DREX byte if needed. */
if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
{
p = frag_more (1);
*p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
/* Encode the OC0 bit if this encoding has multiple
formats. */
if ((i.tm.opcode_modifier.drex
|| i.tm.opcode_modifier.drexv)
&& DREX_OC0 (i.tm.extension_opcode))
*p |= DREX_OC0_MASK;
}
if (i.disp_operands)
output_disp (insn_start_frag, insn_start_off);

27
gas/config/tc-i386.h
View File

@ -153,6 +153,33 @@ modrm_byte;
/* x86-64 extension prefix. */
typedef int rex_byte;
/* The SSE5 instructions have a two bit instruction modifier (OC) that
is stored in two separate bytes in the instruction. Pick apart OC
into the 2 separate bits for instruction. */
#define DREX_OC0(x) (((x) & 1) != 0)
#define DREX_OC1(x) (((x) & 2) != 0)
#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
/* OC mappings */
#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
/* Information needed to create the DREX byte in SSE5 instructions. */
typedef struct
{
unsigned int reg; /* register */
unsigned int rex; /* REX flags */
unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
} drex_byte;
/* 386 opcode byte to code indirect addressing. */
typedef struct
{

10
gas/testsuite/ChangeLog
View File

@ -1,3 +1,13 @@
2007-08-31 Michael Meissner <michael.meissner@amd.com>
Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Tony Linthicum <tony.linthicum@amd.com>
* gas/i386/i386.exp (x86-64-sse5): Run SSE5 64-bit tests.
(sse5): Do not currently run 32-bit tests.
* gas/i386/x86-64-sse5.s: New file for SSE5 support.
* gas/i386/x86-64-sse5.d: Ditto.
2007-09-12 Jan Beulich <jbeulich@novell.com>
* gas/i386/sse4_1.s, gas/i386/x86-64-sse4_1.s: Add two-operand forms
of blendvps, blendvpd, and pblendvb.

1
gas/testsuite/gas/i386/i386.exp
View File

@ -191,6 +191,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_list_test "x86-64-inval-crc32" "-al"
run_dump_test "x86-64-simd"
run_dump_test "x86-64-simd-intel"
run_dump_test "x86-64-sse5"
run_dump_test "x86-64-mem"
run_dump_test "x86-64-mem-intel"
run_dump_test "x86-64-reg"

2841
gas/testsuite/gas/i386/x86-64-sse5.d Normal file
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File diff suppressed because it is too large Load Diff

2970
gas/testsuite/gas/i386/x86-64-sse5.s Normal file
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File diff suppressed because it is too large Load Diff

104
opcodes/ChangeLog
View File

@ -1,3 +1,107 @@
2007-08-31 Michael Meissner <michael.meissner@amd.com>
Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Tony Linthicum <tony.linthicum@amd.com>
* i386-opc.h (CpuSSE5): New macro.
(i386_cpu_flags): Add Drex, Drexv and Drexc.
* i386-gen.c (cpu_flag_init): Add CPU_SSE5_FLAGS.
(operand_type_init): Add CpuSSE5.
(opcode_modifiers): Add Drex, Drexv and Drexc.
(i386_opcode_modifier): Ditto.
* i386-opc.tbl (fmaddps,fmaddpd,fmaddss,fmaddsd): Define SSE5
instructions here.
(fmsubps,fmsubpd,fmsubss,fmsubsd): Ditto.
(fnmaddps,fnmaddpd,fnmaddss,fnmaddsd): Ditto.
(fnmsubps,fnmsubpd,fnmsubss,fnmsubsd): Ditto.
(pmacssww,pmacsww,pmacsswd,pmacswd): Ditto.
(pmacssdd,pmacsdd,pmacssdql,pmacssdqh): Ditto.
(pmacsdql,pmacsdqh,pmadcsswd,pmadcswd): Ditto.
(phaddbw,phaddbd,phaddbq,phaddwd): Ditto.
(phaddwq,phadddq,phaddubw,phaddubd): Ditto.
(phaddubq,phadduwd,phadduwq,phaddudq): Ditto.
(phsubbw,phsubwd,phsubdq): Ditto.
(pcmov,pperm,permps,permpd): Ditto.
(protb,protw,protd,protq): Ditto.
(pshlb,pshlw,pshld,pshlq): Ditto.
(pshab,pshaw,pshad,pshaq): Ditto.
(comps,comeqps,comltps,comungeps,comleps,comungtps): Ditto.
(comunordps,comneps,comneqps,comnltps,comugeps): Ditto.
(comnleps,comugtps,comordps,comueqps,comultps): Ditto.
(comngeps,comuleps,comngtps,comfalseps,comuneps): Ditto.
(comuneqps,comunltps,comgeps,comunleps,comgtps,comtrueps): Ditto.
(compd,comeqpd,comltpd,comungepd,comlepd,comungtpd,comunordpd): Ditto.
(comnepd,comneqpd,comnltpd,comugepd,comnlepd,comugtpd): Ditto.
(comordpd,comueqpd,comultpd,comngepd,comulepd,comngtpd): Ditto.
(comfalsepd,comunepd,comuneqpd,comunltpd,comgepd): Ditto.
(comunlepd,comgtpd,comtruepd): Ditto.
(comss,comeqss,comltss,comungess,comless,comungtss,comunordss): Ditto.
(comness,comneqss,comnltss,comugess,comnless,comugtss): Ditto.
(comordss,comueqss,comultss,comngess,comuless,comngtss): Ditto.
(comfalsess,comuness,comuneqss,comunltss,comgess): Ditto.
(comunless,comgtss,comtruess): Ditto.
(comsd,comeqsd,comltsd,comungesd,comlesd,comungtsd,comunordsd): Ditto.
(comnesd,comneqsd,comnltsd,comugesd,comnlesd,comugtsd): Ditto.
(comordsd,comueqsd,comultsd,comngesd,comulesd,comngtsd): Ditto.
(comfalsesd,comunesd,comuneqsd,comunltsd,comgesd): Ditto.
(comunlesd,comgtsd,comtruesd): Ditto.
(pcomub,pcomltub,pcomleub,pcomgtub,pcomgeub,pcomequb): Ditto.
(pcomnequb,pcomneub): Ditto.
(pcomuw,pcomltuw,pcomleuw,pcomgtuw,pcomgeuw,pcomequw): Ditto.
(pcomnequw,pcomneuw): Ditto.
(pcomud,pcomltud,pcomleud,pcomgtud,pcomgeud,pcomequd): Ditto.
(pcomnequd,pcomneud): Ditto.
(pcomuq,pcomltuq,pcomleuq,pcomgtuq,pcomgeuq,pcomequq): Ditto.
(pcomnequq,pcomneuq): Ditto.
(pcomb,pcomltb,pcomleb,pcomgtb,pcomgeb,pcomeqb): Ditto.
(pcomneqb,pcomneb): Ditto.
(pcomw,pcomltw,pcomlew,pcomgtw,pcomgew,pcomeqw): Ditto.
(pcomneqw,pcomnew): Ditto.
(pcomd,pcomltd,pcomled,pcomgtd,pcomged,pcomeqd): Ditto.
(pcomneqd,pcomned): Ditto.
(pcomq,pcomltq,pcomleq,pcomgtq,pcomgeq): Ditto.
(pcomeqq,pcomneqq,pcomneq): Ditto.
(pcomtrueb, pcomtruew, pcomtrued, pcomtrueq): Ditto.
(pcomtrueub, pcomtrueuw, pcomtrueud, pcomtrueuq): Ditto.
(pcomfalseb, pcomfalsew, pcomfalsed, pcomfalseq): Ditto.
(pcomfalseub, pcomfalseuw, pcomfalseud, pcomfalseuq): Ditto.
(frczps,frczpd,frczss,frczsd): Ditto.
(cvtph2ps,cvtps2ph): Ditto.
* i386-tbl.h: Regenerate from i386-opc.tbl.
* i386-dis.c (libiberty.h): Include to get ARRAY_SIZE.
(dis386_move_test): New disassembly support for move from test
register instruction that overlaps with SSE5 instructions.
(print_insn): Add support for special casing the i386/i486 move
from test register instruction that overlaps with the SSE5
0x0f24 4 operand instructions.
(OP_DREX_ICMP): New macros for SSE5 DREX handling.
(OP_DREX_FCMP): Ditto.
(OP_E_extended): Rename from OP_E, add additional argument to skip
the DREX byte.
(OP_E): Call OP_E_extended.
(DREX_REG_MEMORY): New macros for drex handling.
(DREX_REG_UNKNOWN): Ditto.
(DREX4_OC1): Ditto.
(DREX4_NO_OC0): Ditto.
(DREX4_MASK): Ditto.
(three_byte_table): Add SSE5 instructions.
(print_drex_arg): New function to print a DREX register or memory
reference.
(OP_DREX4): New function for handling DREX 4 argument ops.
(OP_DREX3): New function for handling DREX 3 argument ops.
(twobyte_has_modrm): 0f{25,7a,7b} all use the modrm byte.
(THREE_BYTE_SSE5_0F{24,25,7A,7B}): New macros for initializing 3
byte opcode support for SSE5 instructions.
(dis386_twobyte): Add SSE5 24/25/7a/7b support.
(three_byte_table): Add rows for describing SSE5 instructions.
* Makefile.am (i386-dis.lo): Add $(INCDIR)/libiberty.h.
* Makefile.in (i386-dis.lo): Add $(INCDIR)/libiberty.h.
2007-09-13 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (get_valid_dis386): Take a pointer to

1567
opcodes/i386-dis.c
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File diff suppressed because it is too large Load Diff

8
opcodes/i386-gen.c
View File

@ -107,7 +107,9 @@ static initializer cpu_flag_init [] =
{ "CPU_SSE4A_FLAGS",
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
{ "CPU_ABM_FLAGS",
"CpuABM" }
"CpuABM" },
{ "CPU_SSE5_FLAGS",
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5"}
};
static initializer operand_type_init [] =
@ -231,6 +233,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuSSE4_1),
BITFIELD (CpuSSE4_2),
BITFIELD (CpuSSE4a),
BITFIELD (CpuSSE5),
BITFIELD (Cpu3dnow),
BITFIELD (Cpu3dnowA),
BITFIELD (CpuPadLock),
@ -277,6 +280,9 @@ static bitfield opcode_modifiers[] =
BITFIELD (NoRex64),
BITFIELD (Rex64),
BITFIELD (Ugh),
BITFIELD (Drex),
BITFIELD (Drexv),
BITFIELD (Drexc),
};
static bitfield operand_types[] =

72
opcodes/i386-init.h
View File

@ -20,139 +20,143 @@
#define CPU_UNKNOWN_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 0, 1, 1 } }
1, 1, 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_GENERIC32_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_GENERIC64_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NONE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I186_FLAGS \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I286_FLAGS \
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I386_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I486_FLAGS \
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I586_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I686_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P4_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NOCONA_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_CORE_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CORE2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_K6_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K6_2_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ATHLON_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K8_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_AMDFAM10_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1, 1, 0, 0, 1, 0, 0, 0 } }
1, 1, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_MMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
0, 0, 1, 0, 0, 0, 0, 0 } }
0, 0, 1, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 0, 0, 0 } }
0, 0, 1, 1, 0, 0, 0, 0, 0 } }
#define CPU_3DNOW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_3DNOWA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PADLOCK_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SVME_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4A_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0 } }
1, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ABM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE5_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
1, 1, 0, 0, 1, 0, 0, 0, 0 } }
#define OPERAND_TYPE_NONE \

18
opcodes/i386-opc.h
View File

@ -78,8 +78,10 @@
#define CpuSSE4_1 (CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2 (CpuSSE4_1 + 1)
/* SSE5 support required */
#define CpuSSE5 (CpuSSE4_2 + 1)
/* 64bit support available, used by -march= in assembler. */
#define CpuLM (CpuSSE4_2 + 1)
#define CpuLM (CpuSSE5 + 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
@ -126,6 +128,7 @@ typedef union i386_cpu_flags
unsigned int cpuabm:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpusse5:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
@ -199,8 +202,13 @@ typedef union i386_cpu_flags
#define Rex64 (NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh (Rex64 + 1)
#define Drex (Ugh + 1)
/* instruction needs DREX with multiple encodings for memory ops */
#define Drexv (Drex + 1)
/* special DREX for comparisons */
#define Drexc (Drexv + 1)
/* The last bitfield in i386_opcode_modifier. */
#define Opcode_Modifier_Max Ugh
#define Opcode_Modifier_Max Drexc
typedef struct i386_opcode_modifier
{
@ -234,6 +242,9 @@ typedef struct i386_opcode_modifier
unsigned int norex64:1;
unsigned int rex64:1;
unsigned int ugh:1;
unsigned int drex:1;
unsigned int drexv:1;
unsigned int drexc:1;
} i386_opcode_modifier;
/* Position of operand_type bits. */
@ -400,7 +411,8 @@ typedef struct template
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None */
If this template has no extension opcode (the usual case) use None
Instructions with Drex use this to specify 2 bits for OC */
unsigned int extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */

268
opcodes/i386-opc.tbl
View File

@ -1404,11 +1404,11 @@ pmovzxwq, 2, 0x660f3834, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lS
pmovzxdq, 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pmuldq, 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pmulld, 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
ptest, 2, 0x660f3817, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundpd, 3, 0x660f3a09, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundps, 3, 0x660f3a08, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundsd, 3, 0x660f3a0b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundss, 3, 0x660f3a0a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
ptest, 2, 0x660f3817, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundpd, 3, 0x660f3a09, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundps, 3, 0x660f3a08, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundsd, 3, 0x660f3a0b, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundss, 3, 0x660f3a0a, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
// Streaming SIMD extensions 4.2 Instructions.
@ -1493,6 +1493,264 @@ insertq, 4, 0xf20f78, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N
popcnt, 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
lzcnt, 2, 0xf30fbd, None, CpuABM, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
// SSE5 instructions
fmaddps, 4, 0x0f2400, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmaddpd, 4, 0x0f2401, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmaddss, 4, 0x0f2402, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmaddsd, 4, 0x0f2403, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmsubps, 4, 0x0f2408, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmsubpd, 4, 0x0f2409, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmsubss, 4, 0x0f240a, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fmsubsd, 4, 0x0f240b, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmaddps, 4, 0x0f2410, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmaddpd, 4, 0x0f2411, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmaddss, 4, 0x0f2412, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmaddsd, 4, 0x0f2413, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmsubps, 4, 0x0f2418, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmsubpd, 4, 0x0f2419, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmsubss, 4, 0x0f241a, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
fnmsubsd, 4, 0x0f241b, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pmacssww, 4, 0x0f2485, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacsww, 4, 0x0f2495, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacsswd, 4, 0x0f2486, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacswd, 4, 0x0f2496, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacssdd, 4, 0x0f248e, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacsdd, 4, 0x0f249e, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacssdql, 4, 0x0f2487, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacssdqh, 4, 0x0f248f, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacsdql, 4, 0x0f2497, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmacsdqh, 4, 0x0f249f, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmadcsswd, 4, 0x0f24a6, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pmadcswd, 4, 0x0f24b6, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
phaddbw, 2, 0x0f7a41, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddbd, 2, 0x0f7a42, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddbq, 2, 0x0f7a43, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddwd, 2, 0x0f7a46, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddwq, 2, 0x0f7a47, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phadddq, 2, 0x0f7a4b, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddubw, 2, 0x0f7a51, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddubd, 2, 0x0f7a52, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddubq, 2, 0x0f7a53, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phadduwd, 2, 0x0f7a56, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phadduwq, 2, 0x0f7a57, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phaddudq, 2, 0x0f7a5b, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phsubbw, 2, 0x0f7a61, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phsubwd, 2, 0x0f7a62, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
phsubdq, 2, 0x0f7a63, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pcmov, 4, 0x0f2422, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pperm, 4, 0x0f2423, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
permps, 4, 0x0f2420, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
permpd, 4, 0x0f2421, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
protb, 3, 0x0f2440, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
protb, 3, 0x0f7b40, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM, RegXMM }
protw, 3, 0x0f2441, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
protw, 3, 0x0f7b41, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM, RegXMM }
protd, 3, 0x0f2442, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
protd, 3, 0x0f7b42, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM, RegXMM }
protq, 3, 0x0f2443, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
protq, 3, 0x0f7b43, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM, RegXMM }
pshlb, 3, 0x0f2444, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshlw, 3, 0x0f2445, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshld, 3, 0x0f2446, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshlq, 3, 0x0f2447, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshab, 3, 0x0f2448, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshaw, 3, 0x0f2449, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshad, 3, 0x0f244a, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
pshaq, 3, 0x0f244b, 0x0, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
comps, 4, 0x0f252c, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comeqps, 3, 0x0f252c, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comltps, 3, 0x0f252c, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungeps, 3, 0x0f252c, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comleps, 3, 0x0f252c, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungtps, 3, 0x0f252c, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunordps, 3, 0x0f252c, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comneps, 3, 0x0f252c, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comneqps, 3, 0x0f252c, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnltps, 3, 0x0f252c, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugeps, 3, 0x0f252c, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnleps, 3, 0x0f252c, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugtps, 3, 0x0f252c, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comordps, 3, 0x0f252c, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comueqps, 3, 0x0f252c, 0x8, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comultps, 3, 0x0f252c, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngeps, 3, 0x0f252c, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuleps, 3, 0x0f252c, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngtps, 3, 0x0f252c, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comfalseps, 3, 0x0f252c, 0xb, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuneps, 3, 0x0f252c, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuneqps, 3, 0x0f252c, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunltps, 3, 0x0f252c, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgeps, 3, 0x0f252c, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunleps, 3, 0x0f252c, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgtps, 3, 0x0f252c, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comtrueps, 3, 0x0f252c, 0xf, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
compd, 4, 0x0f252d, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comeqpd, 3, 0x0f252d, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comltpd, 3, 0x0f252d, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungepd, 3, 0x0f252d, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comlepd, 3, 0x0f252d, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungtpd, 3, 0x0f252d, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunordpd, 3, 0x0f252d, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnepd, 3, 0x0f252d, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comneqpd, 3, 0x0f252d, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnltpd, 3, 0x0f252d, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugepd, 3, 0x0f252d, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnlepd, 3, 0x0f252d, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugtpd, 3, 0x0f252d, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comordpd, 3, 0x0f252d, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comueqpd, 3, 0x0f252d, 0x8, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comultpd, 3, 0x0f252d, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngepd, 3, 0x0f252d, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comulepd, 3, 0x0f252d, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngtpd, 3, 0x0f252d, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comfalsepd, 3, 0x0f252d, 0xb, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunepd, 3, 0x0f252d, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuneqpd, 3, 0x0f252d, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunltpd, 3, 0x0f252d, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgepd, 3, 0x0f252d, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunlepd, 3, 0x0f252d, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgtpd, 3, 0x0f252d, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comtruepd, 3, 0x0f252d, 0xf, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comss, 4, 0x0f252e, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comeqss, 3, 0x0f252e, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comltss, 3, 0x0f252e, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungess, 3, 0x0f252e, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comless, 3, 0x0f252e, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungtss, 3, 0x0f252e, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunordss, 3, 0x0f252e, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comness, 3, 0x0f252e, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comneqss, 3, 0x0f252e, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnltss, 3, 0x0f252e, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugess, 3, 0x0f252e, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnless, 3, 0x0f252e, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugtss, 3, 0x0f252e, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comordss, 3, 0x0f252e, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comueqss, 3, 0x0f252e, 0x8, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comultss, 3, 0x0f252e, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngess, 3, 0x0f252e, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuless, 3, 0x0f252e, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngtss, 3, 0x0f252e, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comfalsess, 3, 0x0f252e, 0xb, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuness, 3, 0x0f252e, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuneqss, 3, 0x0f252e, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunltss, 3, 0x0f252e, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgess, 3, 0x0f252e, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunless, 3, 0x0f252e, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgtss, 3, 0x0f252e, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comtruess, 3, 0x0f252e, 0xf, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comsd, 4, 0x0f252f, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comeqsd, 3, 0x0f252f, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comltsd, 3, 0x0f252f, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungesd, 3, 0x0f252f, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comlesd, 3, 0x0f252f, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comungtsd, 3, 0x0f252f, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunordsd, 3, 0x0f252f, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnesd, 3, 0x0f252f, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comneqsd, 3, 0x0f252f, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnltsd, 3, 0x0f252f, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugesd, 3, 0x0f252f, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comnlesd, 3, 0x0f252f, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comugtsd, 3, 0x0f252f, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comordsd, 3, 0x0f252f, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comueqsd, 3, 0x0f252f, 0x8, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comultsd, 3, 0x0f252f, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngesd, 3, 0x0f252f, 0x9, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comulesd, 3, 0x0f252f, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comngtsd, 3, 0x0f252f, 0xa, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comfalsesd, 3, 0x0f252f, 0xb, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunesd, 3, 0x0f252f, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comuneqsd, 3, 0x0f252f, 0xc, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunltsd, 3, 0x0f252f, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgesd, 3, 0x0f252f, 0xd, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comunlesd, 3, 0x0f252f, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comgtsd, 3, 0x0f252f, 0xe, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
comtruesd, 3, 0x0f252f, 0xf, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomub, 4, 0x0f256c, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltub, 3, 0x0f256c, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomleub, 3, 0x0f256c, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtub, 3, 0x0f256c, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgeub, 3, 0x0f256c, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomequb, 3, 0x0f256c, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomnequb, 3, 0x0f256c, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneub, 3, 0x0f256c, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalseub,3, 0x0f256c, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrueub, 3, 0x0f256c, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomuw, 4, 0x0f256d, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltuw, 3, 0x0f256d, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomleuw, 3, 0x0f256d, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtuw, 3, 0x0f256d, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgeuw, 3, 0x0f256d, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomequw, 3, 0x0f256d, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomnequw, 3, 0x0f256d, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneuw, 3, 0x0f256d, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalseuw,3, 0x0f256d, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrueuw, 3, 0x0f256d, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomud, 4, 0x0f256e, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltud, 3, 0x0f256e, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomleud, 3, 0x0f256e, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtud, 3, 0x0f256e, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgeud, 3, 0x0f256e, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomequd, 3, 0x0f256e, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomnequd, 3, 0x0f256e, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneud, 3, 0x0f256e, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalseud,3, 0x0f256e, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrueud, 3, 0x0f256e, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomuq, 4, 0x0f256f, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltuq, 3, 0x0f256f, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomleuq, 3, 0x0f256f, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtuq, 3, 0x0f256f, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgeuq, 3, 0x0f256f, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomequq, 3, 0x0f256f, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomnequq, 3, 0x0f256f, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneuq, 3, 0x0f256f, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalseuq,3, 0x0f256f, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrueuq, 3, 0x0f256f, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomb, 4, 0x0f254c, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltb, 3, 0x0f254c, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomleb, 3, 0x0f254c, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtb, 3, 0x0f254c, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgeb, 3, 0x0f254c, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomeqb, 3, 0x0f254c, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneqb, 3, 0x0f254c, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneb, 3, 0x0f254c, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalseb, 3, 0x0f254c, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrueb, 3, 0x0f254c, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomw, 4, 0x0f254d, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltw, 3, 0x0f254d, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomlew, 3, 0x0f254d, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtw, 3, 0x0f254d, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgew, 3, 0x0f254d, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomeqw, 3, 0x0f254d, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneqw, 3, 0x0f254d, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomnew, 3, 0x0f254d, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalsew, 3, 0x0f254d, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtruew, 3, 0x0f254d, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomd, 4, 0x0f254e, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltd, 3, 0x0f254e, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomled, 3, 0x0f254e, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtd, 3, 0x0f254e, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomged, 3, 0x0f254e, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomeqd, 3, 0x0f254e, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneqd, 3, 0x0f254e, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomned, 3, 0x0f254e, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalsed, 3, 0x0f254e, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrued, 3, 0x0f254e, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomq, 4, 0x0f254f, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|Drexc, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomltq, 3, 0x0f254f, 0x0, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomleq, 3, 0x0f254f, 0x1, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgtq, 3, 0x0f254f, 0x2, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomgeq, 3, 0x0f254f, 0x3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomeqq, 3, 0x0f254f, 0x4, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneqq, 3, 0x0f254f, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomneq, 3, 0x0f254f, 0x5, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomfalseq, 3, 0x0f254f, 0x6, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
pcomtrueq, 3, 0x0f254f, 0x7, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm|ImmExt|Drexc, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM, RegXMM }
frczps, 2, 0x0f7a10, None, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
frczpd, 2, 0x0f7a11, None, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
frczss, 2, 0x0f7a12, None, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
frczsd, 2, 0x0f7a13, None, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
cvtph2ps, 2, 0x0f7a30, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex, RegXMM }
cvtps2ph, 2, 0x0f7a31, None, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex }
// VIA PadLock extensions.
xstore-rng, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 }

7577
opcodes/i386-tbl.h
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