Apply patch for 100679
This commit is contained in:
Nick Clifton
parent
4cd9361480
commit
866afedcb4
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@ -1,3 +1,14 @@
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2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
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* d30v.h:
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(SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
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(SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
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(SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
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(SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
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(SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
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(LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
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(LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
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2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au>
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* i386.h (fild, fistp): Change intel d_Suf form to fildd and
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@ -1,5 +1,5 @@
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/* d30v.h -- Header file for D30V opcode table
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Copyright 1997 Free Software Foundation, Inc.
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Copyright (C) 1997, 2000 Free Software Foundation, Inc.
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Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
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This file is part of GDB, GAS, and the GNU binutils.
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@ -85,40 +85,46 @@ struct d30v_opcode
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#define SHORT_A 9
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#define SHORT_B1 11
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#define SHORT_B2 12
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#define SHORT_B3 13
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#define SHORT_B3b 15
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#define SHORT_D1 17
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#define SHORT_D2 19
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#define SHORT_D2B 21
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#define SHORT_U 23 /* unary SHORT_A. ABS for example */
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#define SHORT_F 25 /* SHORT_A with flag registers */
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#define SHORT_AF 27 /* SHORT_A with only the first register a flag register */
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#define SHORT_T 29 /* for trap instruction */
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#define SHORT_A5 30 /* SHORT_A with a 5-bit immediate instead of 6 */
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#define SHORT_CMP 32 /* special form for CMPcc */
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#define SHORT_CMPU 34 /* special form for CMPUcc */
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#define SHORT_A1 36 /* special form of SHORT_A for MACa opcodes where a=1 */
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#define SHORT_AA 38 /* SHORT_A with the first register an accumulator */
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#define SHORT_RA 40 /* SHORT_A with the second register an accumulator */
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#define SHORT_MODINC 42
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#define SHORT_MODDEC 43
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#define SHORT_C1 44
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#define SHORT_C2 45
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#define SHORT_UF 46
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#define SHORT_A2 47
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#define SHORT_A5S 49
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#define SHORT_NONE 51 /* no operands */
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#define LONG 52
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#define LONG_U 53 /* unary LONG */
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#define LONG_AF 54 /* LONG with the first register a flag register */
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#define LONG_CMP 55 /* special form for CMPcc and CMPUcc */
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#define LONG_M 56 /* Memory long for ldb, stb */
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#define LONG_M2 57 /* Memory long for ld2w, st2w */
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#define LONG_2 58 /* LONG with 2 operands; bratnz */
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#define LONG_2b 59 /* LONG_2 with modifier of 3 */
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#define LONG_D 60 /* for DBRAI*/
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#define LONG_Db 61 /* for repeati*/
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#define SHORT_AR 62 /* like SHORT_AA but only accept register as third parameter */
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#define SHORT_B2r 13
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#define SHORT_B3 14
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#define SHORT_B3r 16
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#define SHORT_B3b 18
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#define SHORT_B3br 20
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#define SHORT_D1r 22
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#define SHORT_D2 24
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#define SHORT_D2r 26
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#define SHORT_D2Br 28
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#define SHORT_U 30 /* unary SHORT_A. ABS for example */
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#define SHORT_F 31 /* SHORT_A with flag registers */
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#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */
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#define SHORT_T 35 /* for trap instruction */
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#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */
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#define SHORT_CMP 38 /* special form for CMPcc */
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#define SHORT_CMPU 40 /* special form for CMPUcc */
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#define SHORT_A1 48 /* special form of SHORT_A for MACa opcodes where a=1 */
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#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */
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#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */
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#define SHORT_MODINC 48
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#define SHORT_MODDEC 49
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#define SHORT_C1 50
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#define SHORT_C2 51
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#define SHORT_UF 52
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#define SHORT_A2 53
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#define SHORT_NONE 55 /* no operands */
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#define LONG 56
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#define LONG_U 57 /* unary LONG */
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#define LONG_Ur 58 /* LONG pc-relative */
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#define LONG_CMP 59 /* special form for CMPcc and CMPUcc */
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#define LONG_M 60 /* Memory long for ldb, stb */
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#define LONG_M2 61 /* Memory long for ld2w, st2w */
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#define LONG_2 62 /* LONG with 2 operands; jmptnz */
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#define LONG_2r 63 /* LONG with 2 operands; bratnz */
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#define LONG_2b 64 /* LONG_2 with modifier of 3 */
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#define LONG_2br 65 /* LONG_2r with modifier of 3 */
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#define LONG_D 66 /* for DJMPI*/
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#define LONG_Dr 67 /* for DBRAI*/
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#define LONG_Dbr 68 /* for repeati*/
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#define SHORT_AR 69 /* like SHORT_AA but only accept register as third parameter */
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/* the execution unit(s) used */
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int unit;
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@ -249,6 +255,10 @@ extern const struct d30v_operand d30v_operand_table[];
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/* let the optimizer know that two registers are affected */
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#define OPERAND_2REG (0x10000)
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/* This operand is pc-relative. Note that repeati can have two immediate
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operands, one of which is pcrel, the other (the IMM6U one) is not. */
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#define OPERAND_PCREL (0x20000)
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/* The format table is an array of struct d30v_format. */
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struct d30v_format
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{
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@ -1,3 +1,24 @@
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2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
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* d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
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flag to determine if operand is pc-relative.
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* d30v-opc.c:
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(d30v_format_table):
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(REL6S3): Renamed from IMM6S3.
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Added flag OPERAND_PCREL.
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(REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
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added flag OPERAND_PCREL.
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(IMM12S3U): Replaced with REL12S3.
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(SHORT_D2, LONG_D): Delay target is pc-relative.
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(SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
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Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
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using the REL* operands.
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(LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
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(SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
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LONG_Db, using REL* operands.
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(SHORT_U, SHORT_A5S): Removed stray alternatives.
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(d30v_opcode_table): Use new *r formats.
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2000-02-28 Nick Clifton <nickc@cygnus.com>
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* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
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@ -1,5 +1,5 @@
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/* Disassemble D30V instructions.
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Copyright (C) 1997, 1998 Free Software Foundation, Inc.
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Copyright (C) 1997, 1998, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -305,38 +305,41 @@ print_insn ( info, memaddr, num, insn, is_long, show_ext )
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(info->stream, _("<unknown register %d>"), val & 0x3F);
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}
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}
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else if (insn->op->reloc_flag == RELOC_PCREL ||
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(opind == 1 && (insn->form->form == SHORT_D2 || insn->form->form == LONG_D)))
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/* repeati has a relocation, but its first argument is a plain
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immediate. OTOH instructions like djsri have a pc-relative
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delay target, but a absolute jump target. Therefore, a test
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of insn->op->reloc_flag is not specific enough; we must test
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if the actual operand we are handling now is pc-relative. */
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else if (oper->flags & OPERAND_PCREL)
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{
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long max;
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int neg=0;
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max = (1 << (bits - 1));
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if (val & max)
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int neg = 0;
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/* IMM6S3 is unsigned. */
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if (oper->flags & OPERAND_SIGNED || bits == 32)
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{
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if (bits == 32)
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val = -val;
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else
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val = -val & ((1 << bits)-1);
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neg = 1;
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long max;
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max = (1 << (bits - 1));
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if (val & max)
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{
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if (bits == 32)
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val = -val;
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else
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val = -val & ((1 << bits)-1);
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neg = 1;
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}
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}
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if (opind == 1 && (insn->form->form == SHORT_D2 || insn->form->form == LONG_D))
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if (neg)
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{
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(*info->fprintf_func) (info->stream, "%x",val);
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(*info->fprintf_func) (info->stream, "-%x\t(",val);
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(*info->print_address_func) ((memaddr - val) & PC_MASK, info);
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(*info->fprintf_func) (info->stream, ")");
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}
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else
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{
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(*info->fprintf_func) (info->stream, "%x\t(",val);
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(*info->print_address_func) ((memaddr + val) & PC_MASK, info);
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(*info->fprintf_func) (info->stream, ")");
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}
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else {
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if (neg)
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{
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(*info->fprintf_func) (info->stream, "-%x\t(",val);
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(*info->print_address_func) ((memaddr - val) & PC_MASK, info);
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(*info->fprintf_func) (info->stream, ")");
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}
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else
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{
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(*info->fprintf_func) (info->stream, "%x\t(",val);
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(*info->print_address_func) ((memaddr + val) & PC_MASK, info);
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(*info->fprintf_func) (info->stream, ")");
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}
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}
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}
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else if (insn->op->reloc_flag == RELOC_ABS)
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{
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@ -1,5 +1,5 @@
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/* d30v-opc.c -- D30V opcode list
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Copyright 1997, 1998 Free Software Foundation, Inc.
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Copyright (C) 1997, 1998, 2000 Free Software Foundation, Inc.
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Written by Martin Hunt, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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@ -222,20 +222,20 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
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{ "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
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{ "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
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{ "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
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{ "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
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@ -290,8 +290,8 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
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{ "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
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{ "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
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{ "repeati", BRA, 0x1a, { SHORT_D2B, LONG_Db }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
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{ "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
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{ "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
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{ "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
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@ -357,25 +357,29 @@ const struct d30v_operand d30v_operand_table[] =
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{ 6, 1, 6, OPERAND_ACC|OPERAND_REG },
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#define IMM5 (Ab + 1)
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{ 6, 5, 12, OPERAND_NUM },
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#define IMM5U (IMM5 + 1)
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{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM5S3 (IMM5U + 1)
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{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM6 (IMM5S3 + 1)
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#define IMM5U (IMM5 + 1)
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{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
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#define IMM5S3 (IMM5U + 1)
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{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
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#define IMM6 (IMM5S3 + 1)
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{ 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
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#define IMM6U (IMM6 + 1)
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#define IMM6U (IMM6 + 1)
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{ 6, 6, 0, OPERAND_NUM },
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#define IMM6U2 (IMM6U + 1)
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#define IMM6U2 (IMM6U + 1)
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{ 6, 6, 12, OPERAND_NUM },
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#define IMM6S3 (IMM6U2 + 1)
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{ 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT },
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#define IMM12S3 (IMM6S3 + 1)
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#define REL6S3 (IMM6U2 + 1)
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{ 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL },
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#define REL12S3 (REL6S3 + 1)
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{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
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#define IMM12S3 (REL12S3 + 1)
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{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
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#define IMM12S3U (IMM12S3 + 1)
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{ 12, 12, 12, OPERAND_NUM|OPERAND_SHIFT },
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#define IMM18S3 (IMM12S3U + 1)
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#define REL18S3 (IMM12S3 + 1)
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{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
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#define IMM18S3 (REL18S3 + 1)
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{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
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#define IMM32 (IMM18S3 + 1)
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#define REL32 (IMM18S3 + 1)
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{ 32, 32, 0, OPERAND_NUM|OPERAND_PCREL },
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#define IMM32 (REL32 + 1)
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{ 32, 32, 0, OPERAND_NUM },
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#define Fa (IMM32 + 1)
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{ 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
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@ -414,25 +418,31 @@ const struct d30v_format d30v_format_table[] =
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{ SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
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{ SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
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{ SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
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{ SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
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{ SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */
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{ SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
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{ SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
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{ SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */
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{ SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
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{ SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
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||||
{ SHORT_B1, 0, { Rc } }, /* Rc */
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||||
{ SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
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||||
{ SHORT_B2r, 2, { REL18S3 } }, /* rel18 */
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||||
{ SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */
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||||
{ SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */
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||||
{ SHORT_B3r, 0, { Ra3, Rc } }, /* Ra,Rc */
|
||||
{ SHORT_B3r, 2, { Ra3, REL12S3 } }, /* Ra,rel12 */
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||||
{ SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */
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||||
{ SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */
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||||
{ SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */
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||||
{ SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */
|
||||
{ SHORT_D2, 0, { IMM6S3, Rc } }, /* imm6s3,Rc */
|
||||
{ SHORT_D2, 2, { IMM6S3, IMM12S3 } }, /* imm6s3,imm12s3 */
|
||||
{ SHORT_D2B, 0, { IMM6U, Rc } }, /* imm6u,Rc */
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||||
{ SHORT_D2B, 2, { IMM6U, IMM12S3U } }, /* imm6u,imm12s3u */
|
||||
{ SHORT_B3br, 1, { Ra3, Rc } }, /* Ra,Rc */
|
||||
{ SHORT_B3br, 3, { Ra3, REL12S3 } }, /* Ra,rel12 */
|
||||
{ SHORT_D1r, 0, { Ra, Rc } }, /* Ra,Rc */
|
||||
{ SHORT_D1r, 2, { Ra, REL12S3 } }, /* Ra,rel12s3 */
|
||||
{ SHORT_D2, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
|
||||
{ SHORT_D2, 2, { REL6S3, IMM12S3 } }, /* rel6s3,imm12s3 */
|
||||
{ SHORT_D2r, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
|
||||
{ SHORT_D2r, 2, { REL6S3, REL12S3 } }, /* rel6s3,rel12s3 */
|
||||
{ SHORT_D2Br, 0, { IMM6U, Rc } }, /* imm6u,Rc */
|
||||
{ SHORT_D2Br, 2, { IMM6U, REL12S3 } }, /* imm6u,rel12s3 */
|
||||
{ SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
|
||||
{ SHORT_U, 2, { Ra, IMM12S3 } }, /* Ra,imm12 (repeat) */
|
||||
{ SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
|
||||
{ SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
|
||||
{ SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
|
||||
|
|
@ -457,19 +467,20 @@ const struct d30v_format d30v_format_table[] =
|
|||
{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
|
||||
{ SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
|
||||
{ SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
|
||||
{ SHORT_A5S, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
|
||||
{ SHORT_A5S, 2, { Ra, Rb, IMM5U } }, /* Ra,Rb,imm5u (shifts) */
|
||||
{ SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
|
||||
{ LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
|
||||
{ LONG_U, 2, { IMM32 } }, /* imm32 */
|
||||
{ LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */
|
||||
{ LONG_Ur, 2, { REL32 } }, /* rel32 */
|
||||
{ LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
|
||||
{ LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
|
||||
{ LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
|
||||
{ LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */
|
||||
{ LONG_2r, 2, { Ra3, REL32 } }, /* Ra,rel32 */
|
||||
{ LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */
|
||||
{ LONG_D, 2, { IMM6S3, IMM32 } }, /* imm6s3,imm32 */
|
||||
{ LONG_Db, 2, { IMM6U, IMM32 } }, /* imm6,imm32 */
|
||||
{ LONG_2br, 3, { Ra3, REL32 } }, /* Ra,rel32 */
|
||||
{ LONG_D, 2, { REL6S3, IMM32 } }, /* rel6s3,imm32 */
|
||||
{ LONG_Dr, 2, { REL6S3, REL32 } }, /* rel6s3,rel32 */
|
||||
{ LONG_Dbr, 2, { IMM6U, REL32 } }, /* imm6,rel32 */
|
||||
{ SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
|
||||
{ 0, 0, { 0 } },
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue