Enhance debug support
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9811b59602
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@ -1,3 +1,22 @@
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Wed Sep 4 11:35:17 1996 Michael Meissner <meissner@tiktok.cygnus.com>
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* d10v_sim.h (DEBUG_*): Add bit flags for controlling debug
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output.
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(_ins_type): New enumeration to specify which container an
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instruction is in, and whether it is part of a parallel operation.
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(_state): Add ins_type field.
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* simops.c: Change all #ifdef DEBUG code so that the input and
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output values can be traced, along with the instruction type.
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* interp.c (_leftright): New enumeration to say whether 2 short
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instructions are done left first or right first.
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(do_{long,2_short,parallel}): Indicate in the machine state which
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type of instruction this is.
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(sim_size): Only print the memory sizes if DEBUG_MEMSIZE debug
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flag is set.
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(sim_resume): Pass left/right indication to do_2_short.
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Wed Sep 04 04:45:34 1996 Mark Alexander <marka@cygnus.com>
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* simops.c: Include correct syscall.h for d10v, not host's.
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@ -1,8 +1,17 @@
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#include <stdio.h>
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#include <ctype.h>
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#include "ansidecl.h"
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#include "callback.h"
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#include "opcode/d10v.h"
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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#define DEBUG_MEMSIZE 0x00000004
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#ifndef DEBUG
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#define DEBUG 0
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#endif
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/* FIXME: host defines */
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typedef unsigned char uint8;
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typedef unsigned short uint16;
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@ -28,6 +37,16 @@ struct simops
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int operands[9];
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};
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enum _ins_type
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{
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INS_UNKNOWN,
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INS_LEFT,
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INS_RIGHT,
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INS_LEFT_PARALLEL,
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INS_RIGHT_PARALLEL,
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INS_LONG
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};
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struct _state
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{
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reg_t regs[16]; /* general-purpose registers */
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@ -48,8 +67,10 @@ struct _state
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uint8 *imem;
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uint8 *dmem;
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int exception;
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enum _ins_type ins_type;
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} State;
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extern host_callback *d10v_callback;
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extern uint16 OP[4];
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extern struct simops Simops[];
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@ -102,6 +123,7 @@ extern struct simops Simops[];
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#define RW(x) (*((uint16 *)((x)+State.imem)))
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#define RLW(x) (*((uint32 *)((x)+State.imem)))
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#define SW(addr,data) RW(addr)=data
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#define SLW(addr,data) RLW(addr)=data
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#define READ_16(x) (*((int16 *)(x)))
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#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
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#define READ_64(x) (*((int64 *)(x)))
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@ -113,10 +135,12 @@ uint32 get_longword PARAMS ((uint8 *));
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uint16 get_word PARAMS ((uint8 *));
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int64 get_longlong PARAMS ((uint8 *));
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void write_word PARAMS ((uint8 *addr, uint16 data));
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void write_longword PARAMS ((uint8 *addr, uint32 data));
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void write_longlong PARAMS ((uint8 *addr, int64 data));
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#define SW(addr,data) write_word((long)(addr)+State.imem,data)
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#define RW(x) get_word((long)(x)+State.imem)
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#define SLW(addr,data) write_longword((long)(addr)+State.imem,data)
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#define RLW(x) get_longword((long)(x)+State.imem)
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#define READ_16(x) get_word(x)
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#define WRITE_16(addr,data) write_word(addr,data)
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@ -2,13 +2,16 @@
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#include "sysdep.h"
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#include "bfd.h"
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#include "remote-sim.h"
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#include "callback.h"
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#include "d10v_sim.h"
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#define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
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#define DMEM_SIZE 16 /* Data memory */
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enum _leftright { LEFT_FIRST, RIGHT_FIRST };
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host_callback *d10v_callback;
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uint16 OP[4];
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static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size));
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@ -51,7 +54,7 @@ lookup_hash (ins, size)
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{
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if (h->next == NULL)
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{
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printf ("ERROR looking up hash for %x\n",ins);
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printf ("ERROR looking up hash for %x at PC %x\n",ins, PC);
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exit(1);
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}
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h = h->next;
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@ -84,6 +87,7 @@ get_word (x)
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return ((uint16)a[0]<<8) + a[1];
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}
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void
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write_word (addr, data)
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uint8 *addr;
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@ -94,6 +98,17 @@ write_word (addr, data)
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a[1] = data & 0xff;
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}
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void
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write_longword (addr, data)
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uint8 *addr;
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uint32 data;
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{
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addr[0] = (data >> 24) & 0xff;
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addr[1] = (data >> 16) & 0xff;
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addr[2] = (data >> 8) & 0xff;
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addr[3] = data & 0xff;
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}
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void
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write_longlong (addr, data)
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uint8 *addr;
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@ -110,7 +125,6 @@ write_longlong (addr, data)
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a[7] = data & 0xff;
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}
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static void
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get_operands (struct simops *s, uint32 ins)
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{
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@ -134,19 +148,23 @@ do_long (ins)
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/* printf ("do_long %x\n",ins); */
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h = lookup_hash (ins, 1);
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get_operands (h->ops, ins);
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State.ins_type = INS_LONG;
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(h->ops->func)();
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}
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static void
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do_2_short (ins1, ins2)
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do_2_short (ins1, ins2, leftright)
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uint16 ins1, ins2;
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enum _leftright leftright;
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{
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struct hash_entry *h;
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/* printf ("do_2_short %x -> %x\n",ins1,ins2); */
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h = lookup_hash (ins1, 0);
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get_operands (h->ops, ins1);
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State.ins_type = (leftright == LEFT_FIRST) ? INS_LEFT : INS_RIGHT;
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(h->ops->func)();
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h = lookup_hash (ins2, 0);
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get_operands (h->ops, ins2);
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State.ins_type = (leftright == LEFT_FIRST) ? INS_RIGHT : INS_LEFT;
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(h->ops->func)();
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}
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static void
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@ -161,28 +179,34 @@ do_parallel (ins1, ins2)
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if (h1->ops->exec_type == PARONLY)
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT;
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(h1->ops->func)();
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if (State.exe)
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{
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT;
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(h2->ops->func)();
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}
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}
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else if (h2->ops->exec_type == PARONLY)
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{
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT;
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(h2->ops->func)();
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if (State.exe)
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT;
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(h1->ops->func)();
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}
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}
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else
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT_PARALLEL;
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(h1->ops->func)();
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT_PARALLEL;
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(h2->ops->func)();
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}
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}
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@ -206,8 +230,10 @@ sim_size (power)
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fprintf (stderr,"Memory allocation failed.\n");
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exit(1);
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}
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#if (DEBUG & DEBUG_MEMSIZE) != 0
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printf ("Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE);
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printf (" %d bytes data memory.\n",1<<DMEM_SIZE);
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#endif
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}
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static void
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@ -312,11 +338,11 @@ sim_resume (step, siggnal)
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break;
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case 0x80000000:
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/* R -> L */
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do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15);
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do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, 0);
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break;
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case 0x40000000:
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/* L -> R */
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do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
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do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, 1);
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break;
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case 0:
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do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
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@ -374,8 +400,8 @@ void
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sim_set_callbacks(p)
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host_callback *p;
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{
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printf ("sim_set_callbacks\n");
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/* callback = p; */
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/* printf ("sim_set_callbacks\n"); */
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d10v_callback = p;
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}
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void
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1146
sim/d10v/simops.c
1146
sim/d10v/simops.c
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