Currently CYGNUS local
This commit is contained in:
Nick Clifton
parent
a4cb37cb10
commit
87673fab32
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@ -1,250 +0,0 @@
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/* Disassemble Motorolla M*Core instructions.
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Copyright (C) 1993, 1999 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdio.h>
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#define STATIC_TABLE
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#define DEFINE_TABLE
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#include "mcore-opc.h"
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#include "dis-asm.h"
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/* Mask for each mcore_opclass: */
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static const unsigned short imsk[] =
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{
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/* O0 */ 0xFFFF,
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/* OT */ 0xFFFC,
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/* O1 */ 0xFFF0,
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/* OC */ 0xFFE0,
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/* O2 */ 0xFF00,
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/* X1 */ 0xFFF0,
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/* OI */ 0xFE00,
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/* OB */ 0xFE00,
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/* OMa */ 0xFFF0,
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/* SI */ 0xFE00,
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/* I7 */ 0xF800,
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/* LS */ 0xF000,
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/* BR */ 0xF800,
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/* BL */ 0xFF00,
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/* LR */ 0xF000,
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/* LJ */ 0xFF00,
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/* RM */ 0xFFF0,
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/* RQ */ 0xFFF0,
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/* JSR */ 0xFFF0,
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/* JMP */ 0xFFF0,
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/* OBRa*/ 0xFFF0,
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/* OBRb*/ 0xFF80,
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/* OBRc*/ 0xFF00,
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/* OBR2*/ 0xFE00,
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/* O1R1*/ 0xFFF0,
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/* OMb */ 0xFF80,
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/* OMc */ 0xFF00,
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/* SIa */ 0xFE00,
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/* JC */ 0, /* JC,JU,JL don't appear in object */
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/* JU */ 0,
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/* JL */ 0,
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/* RSI */ 0,
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/* DO21*/ 0,
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/* OB2 */ 0 /* OB2 won't appear in object. */
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};
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static const char * grname[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
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};
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static const char X[] = "??";
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static const char * crname[] =
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{
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"psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
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"ss2", "ss3", "ss4", "gcr", "gsr", X, X, X,
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X, X, X, X, X, X, X, X,
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X, X, X, X, X, X, X, X
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};
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static const unsigned isiz[] = { 2, 0, 1, 0 };
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int
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print_insn_mcore (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info * info;
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{
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unsigned char ibytes[4];
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fprintf_ftype fprintf = info->fprintf_func;
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void * stream = info->stream;
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unsigned short inst;
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mcore_opcode_info * op;
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int status;
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status = info->read_memory_func (memaddr, ibytes, 2, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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inst = (ibytes[0] << 8) | ibytes[1];
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/* Just a linear search of the table. */
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for (op = mcore_table; op->name != 0; op ++)
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{
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if (op->inst == (inst & imsk[op->opclass]))
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break;
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}
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if (op->name == 0)
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fprintf (stream, ".word 0x%04x", inst);
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else
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{
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const char * name = grname[inst & 0x0F];
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fprintf (stream, "%s", op->name);
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switch (op->opclass)
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{
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case O0: break;
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case OT: fprintf (stream, "\t%d", inst & 0x3); break;
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case O1:
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case JMP:
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case JSR: fprintf (stream, "\t%s", name); break;
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case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
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case O1R1: fprintf (stream, "\t%s, r1", name); break;
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case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
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case X1: fprintf (stream, "\tr1, %s", name); break;
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case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
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case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
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case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
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case OB:
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case OBRa:
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case OBRb:
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case OBRc:
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case SI:
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case SIa:
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case OMa:
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case OMb:
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case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
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case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
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case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
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name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
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break;
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case BR:
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{
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long val = inst & 0x3FF;
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if (inst & 0x400)
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val |= 0xFFFFFC00;
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fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1));
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if (strcmp (op->name, "bsr") == 0)
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{
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/* for bsr, we'll try to get a symbol for the target */
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val = memaddr + 2 + (val << 1);
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if (info->print_address_func && val != 0)
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{
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fprintf (stream, "\t// ");
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info->print_address_func (val, info);
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}
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}
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}
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break;
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case BL:
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{
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long val;
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val = (inst & 0x000F);
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fprintf (stream, "\t%s, 0x%x",
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grname[(inst >> 4) & 0xF], memaddr - (val << 1));
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}
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break;
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case LR:
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{
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unsigned long val;
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val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
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status = info->read_memory_func (val, ibytes, 4, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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val = (ibytes[0] << 24) | (ibytes[1] << 16)
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| (ibytes[2] << 8) | (ibytes[3]);
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/* Removed [] around literal value to match ABI syntax 12/95. */
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fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);
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if (val == 0)
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fprintf (stream, "\t// from address pool at 0x%x",
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(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
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}
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break;
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case LJ:
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{
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unsigned long val;
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val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
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status = info->read_memory_func (val, ibytes, 4, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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val = (ibytes[0] << 24) | (ibytes[1] << 16)
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| (ibytes[2] << 8) | (ibytes[3]);
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/* Removed [] around literal value to match ABI syntax 12/95. */
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fprintf (stream, "\t0x%X", val);
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/* For jmpi/jsri, we'll try to get a symbol for the target. */
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if (info->print_address_func && val != 0)
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{
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fprintf (stream, "\t// ");
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info->print_address_func (val, info);
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}
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else
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{
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fprintf (stream, "\t// from address pool at 0x%x",
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(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
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}
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}
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break;
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default:
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/* if the disassembler lags the instruction set */
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fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
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break;
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}
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}
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/* Say how many bytes we consumed? */
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return 2;
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}
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@ -1,202 +0,0 @@
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/* Assembler instructions for Motorolla's Mcore processor
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Copyright (C) 1999 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "ansidecl.h"
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typedef enum
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{
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O0, OT, O1, OC, O2, X1, OI, OB,
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OMa, SI, I7, LS, BR, BL, LR, LJ,
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RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2,
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O1R1, OMb, OMc, SIa,
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JC, JU, JL, RSI, DO21, OB2
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}
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mcore_opclass;
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typedef struct inst
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{
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char * name;
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mcore_opclass opclass;
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unsigned char transfer;
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unsigned short inst;
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}
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mcore_opcode_info;
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#ifdef DEFINE_TABLE
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mcore_opcode_info mcore_table[] =
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{
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{ "bkpt", O0, 0, 0x0000 },
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{ "sync", O0, 0, 0x0001 },
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{ "rte", O0, 1, 0x0002 },
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{ "rfe", O0, 1, 0x0002 },
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{ "rfi", O0, 1, 0x0003 },
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{ "stop", O0, 0, 0x0004 },
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{ "wait", O0, 0, 0x0005 },
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{ "doze", O0, 0, 0x0006 },
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{ "trap", OT, 0, 0x0008 },
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/* SPACE: 0x000C - 0x000F */
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/* SPACE: 0x0010 - 0x001F */
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{ "mvc", O1, 0, 0x0020 },
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{ "mvcv", O1, 0, 0x0030 },
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{ "ldq", RQ, 0, 0x0040 },
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{ "stq", RQ, 0, 0x0050 },
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{ "ldm", RM, 0, 0x0060 },
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{ "stm", RM, 0, 0x0070 },
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{ "dect", O1, 0, 0x0080 },
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{ "decf", O1, 0, 0x0090 },
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{ "inct", O1, 0, 0x00A0 },
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{ "incf", O1, 0, 0x00B0 },
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{ "jmp", JMP, 2, 0x00C0 },
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#define MCORE_INST_JMP 0x00C0
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{ "jsr", JSR, 0, 0x00D0 },
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#define MCORE_INST_JSR 0x00E0
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{ "ff1", O1, 0, 0x00E0 },
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{ "brev", O1, 0, 0x00F0 },
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{ "xtrb3", X1, 0, 0x0100 },
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{ "xtrb2", X1, 0, 0x0110 },
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{ "xtrb1", X1, 0, 0x0120 },
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{ "xtrb0", X1, 0, 0x0130 },
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{ "zextb", O1, 0, 0x0140 },
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{ "sextb", O1, 0, 0x0150 },
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{ "zexth", O1, 0, 0x0160 },
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{ "sexth", O1, 0, 0x0170 },
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{ "declt", O1, 0, 0x0180 },
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{ "tstnbz", O1, 0, 0x0190 },
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{ "decgt", O1, 0, 0x01A0 },
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{ "decne", O1, 0, 0x01B0 },
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{ "clrt", O1, 0, 0x01C0 },
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{ "clrf", O1, 0, 0x01D0 },
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{ "abs", O1, 0, 0x01E0 },
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{ "not", O1, 0, 0x01F0 },
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{ "movt", O2, 0, 0x0200 },
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{ "mult", O2, 0, 0x0300 },
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{ "loopt", BL, 0, 0x0400 },
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{ "subu", O2, 0, 0x0500 },
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{ "sub", O2, 0, 0x0500 }, /* Official alias. */
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{ "addc", O2, 0, 0x0600 },
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{ "subc", O2, 0, 0x0700 },
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/* SPACE: 0x0800-0x08ff for a diadic operation */
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/* SPACE: 0x0900-0x09ff for a diadic operation */
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{ "movf", O2, 0, 0x0A00 },
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{ "lsr", O2, 0, 0x0B00 },
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{ "cmphs", O2, 0, 0x0C00 },
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{ "cmplt", O2, 0, 0x0D00 },
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{ "tst", O2, 0, 0x0E00 },
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{ "cmpne", O2, 0, 0x0F00 },
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{ "mfcr", OC, 0, 0x1000 },
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{ "mov", O2, 0, 0x1200 },
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{ "bgenr", O2, 0, 0x1300 },
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{ "rsub", O2, 0, 0x1400 },
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{ "ixw", O2, 0, 0x1500 },
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{ "and", O2, 0, 0x1600 },
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{ "xor", O2, 0, 0x1700 },
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{ "mtcr", OC, 0, 0x1800 },
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{ "asr", O2, 0, 0x1A00 },
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{ "lsl", O2, 0, 0x1B00 },
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{ "addu", O2, 0, 0x1C00 },
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{ "ixh", O2, 0, 0x1D00 },
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{ "or", O2, 0, 0x1E00 },
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{ "andn", O2, 0, 0x1F00 },
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{ "addi", OI, 0, 0x2000 },
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#define MCORE_INST_ADDI 0x2000
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{ "cmplti", OI, 0, 0x2200 },
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{ "subi", OI, 0, 0x2400 },
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/* SPACE: 0x2600-0x27ff open for a register+immediate operation */
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{ "rsubi", OB, 0, 0x2800 },
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{ "cmpnei", OB, 0, 0x2A00 },
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{ "bmaski", OMa, 0, 0x2C00 },
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{ "divu", O1R1, 0, 0x2C10 },
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/* SPACE: 0x2c20 - 0x2c7f */
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{ "bmaski", OMb, 0, 0x2C80 },
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{ "bmaski", OMc, 0, 0x2D00 },
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{ "andi", OB, 0, 0x2E00 },
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{ "bclri", OB, 0, 0x3000 },
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/* SPACE: 0x3200 - 0x320f */
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{ "divs", O1R1, 0, 0x3210 },
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/* SPACE: 0x3220 - 0x326f */
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{ "bgeni", OBRa, 0, 0x3270 },
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{ "bgeni", OBRb, 0, 0x3280 },
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{ "bgeni", OBRc, 0, 0x3300 },
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{ "bseti", OB, 0, 0x3400 },
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{ "btsti", OB, 0, 0x3600 },
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{ "xsr", O1, 0, 0x3800 },
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{ "rotli", SIa, 0, 0x3800 },
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{ "asrc", O1, 0, 0x3A00 },
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{ "asri", SIa, 0, 0x3A00 },
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{ "lslc", O1, 0, 0x3C00 },
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{ "lsli", SIa, 0, 0x3C00 },
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{ "lsrc", O1, 0, 0x3E00 },
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{ "lsri", SIa, 0, 0x3E00 },
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/* SPACE: 0x4000 - 0x5fff */
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{ "movi", I7, 0, 0x6000 },
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#define MCORE_INST_BMASKI_ALT 0x6000
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#define MCORE_INST_BGENI_ALT 0x6000
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/* SPACE: 0x6900 - 0x6FFF */
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{ "jmpi", LJ, 1, 0x7000 },
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{ "jsri", LJ, 0, 0x7F00 },
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#define MCORE_INST_JMPI 0x7000
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{ "lrw", LR, 0, 0x7000 },
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#define MCORE_INST_JSRI 0x7F00
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{ "ld", LS, 0, 0x8000 },
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{ "ldw", LS, 0, 0x8000 },
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{ "ld.w", LS, 0, 0x8000 },
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{ "st", LS, 0, 0x9000 },
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{ "stw", LS, 0, 0x9000 },
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{ "st.w", LS, 0, 0x9000 },
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{ "ldb", LS, 0, 0xA000 },
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{ "ld.b", LS, 0, 0xA000 },
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{ "stb", LS, 0, 0xB000 },
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{ "st.b", LS, 0, 0xB000 },
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{ "ldh", LS, 0, 0xC000 },
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{ "ld.h", LS, 0, 0xC000 },
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{ "sth", LS, 0, 0xD000 },
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{ "st.h", LS, 0, 0xD000 },
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{ "bt", BR, 0, 0xE000 },
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{ "bf", BR, 0, 0xE800 },
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{ "br", BR, 1, 0xF000 },
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#define MCORE_INST_BR 0xF000
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{ "bsr", BR, 0, 0xF800 },
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#define MCORE_INST_BSR 0xF800
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/* The following are relaxable branches */
|
||||
{ "jbt", JC, 0, 0xE000 },
|
||||
{ "jbf", JC, 0, 0xE800 },
|
||||
{ "jbr", JU, 1, 0xF000 },
|
||||
{ "jbsr", JL, 0, 0xF800 },
|
||||
|
||||
/* The following are aliases for other instructions */
|
||||
{ "rts", O0, 2, 0x00CF }, /* jmp r15 */
|
||||
{ "rolc", DO21, 0, 0x0600 }, /* addc rd,rd */
|
||||
{ "rotlc", DO21, 0, 0x0600 }, /* addc rd,rd */
|
||||
{ "setc", O0, 0, 0x0C00 }, /* cmphs r0,r0 */
|
||||
{ "clrc", O0, 0, 0x0F00 }, /* cmpne r0,r0 */
|
||||
{ "tstle", O1, 0, 0x2200 }, /* cmplti rd,1 */
|
||||
{ "cmplei", OB, 0, 0x2200 }, /* cmplei rd,X -> cmplti rd,X+1 */
|
||||
{ "neg", O1, 0, 0x2800 }, /* rsubi rd,0 */
|
||||
{ "tstne", O1, 0, 0x2A00 }, /* cmpnei rd,0 */
|
||||
{ "tstlt", O1, 0, 0x37F0 }, /* btsti rx,31 */
|
||||
{ "mclri", OB2, 0, 0x3000 }, /* bclri rx,log2(imm) */
|
||||
{ "mgeni", OBR2, 0, 0x3200 }, /* bgeni rx,log2(imm) */
|
||||
{ "mseti", OB2, 0, 0x3400 }, /* bseti rx,log2(imm) */
|
||||
{ "mtsti", OB2, 0, 0x3600 }, /* btsti rx,log2(imm) */
|
||||
{ "rori", RSI, 0, 0x3800 },
|
||||
{ "rotri", RSI, 0, 0x3800 },
|
||||
{ "nop", O0, 0, 0x1200 }, /* mov r0, r0 */
|
||||
{ 0, 0, 0, 0 }
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue