[AArch64] Add ARMv8.3 instructions which are in the NOP space

This patch adds support for a subset of the ARMv8.3 pointer authentication
instructions: XPACLRI, PACIA1716, PACIB1716, AUTIA1716, AUTIA1716, PACIAZ,
PACIASP, PACIBZ, PACISP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP.

These are aliases to HINT #0x7, HINT #0x8, HINT #0xa, HINT #0xc, HINT #0xe,
HINT #0x18, HINT #0x19, ..., HINT #0x1f respectively.

For more details about pointer authentication in ARMv8.3 see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

opcodes/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
	(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
	autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
	autibsp.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* testsuite/gas/aarch64/system-3.s: New.
	* testsuite/gas/aarch64/system-3.d: New.
	* testsuite/gas/aarch64/system.d: Update expected output.
This commit is contained in:
Szabolcs Nagy 2016-11-11 10:29:07 +00:00
parent 3d731f6949
commit 8787d804e1
9 changed files with 1041 additions and 907 deletions

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@ -1,3 +1,9 @@
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/system-3.s: New.
* testsuite/gas/aarch64/system-3.d: New.
* testsuite/gas/aarch64/system.d: Update expected output.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".

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@ -0,0 +1,34 @@
#as: -march=armv8.3-a
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: d50320ff xpaclri
4: d50320ff xpaclri
8: d503211f pacia1716
c: d503211f pacia1716
10: d503215f pacib1716
14: d503215f pacib1716
18: d503219f autia1716
1c: d503219f autia1716
20: d50321df autib1716
24: d50321df autib1716
28: d503231f paciaz
2c: d503231f paciaz
30: d503233f paciasp
34: d503233f paciasp
38: d503235f pacibz
3c: d503235f pacibz
40: d503237f pacibsp
44: d503237f pacibsp
48: d503239f autiaz
4c: d503239f autiaz
50: d50323bf autiasp
54: d50323bf autiasp
58: d50323df autibz
5c: d50323df autibz
60: d50323ff autibsp
64: d50323ff autibsp

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@ -0,0 +1,41 @@
/* ARMv8.3 Pointer authentication, HINT alias instructions. */
.text
xpaclri
hint #0x7
pacia1716
hint #0x8
pacib1716
hint #0xa
autia1716
hint #0xc
autib1716
hint #0xe
paciaz
hint #0x18
paciasp
hint #0x19
pacibz
hint #0x1a
pacibsp
hint #0x1b
autiaz
hint #0x1c
autiasp
hint #0x1d
autibz
hint #0x1e
autibsp
hint #0x1f

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@ -19,14 +19,14 @@ Disassembly of section \.text:
2c: d503209f sev
30: d50320bf sevl
34: d50320df hint #0x6
38: d50320ff hint #0x7
3c: d503211f hint #0x8
38: d50320ff (hint #0x7|xpaclri)
3c: d503211f (hint #0x8|pacia1716)
40: d503213f hint #0x9
44: d503215f hint #0xa
44: d503215f (hint #0xa|pacib1716)
48: d503217f hint #0xb
4c: d503219f hint #0xc
4c: d503219f (hint #0xc|autia1716)
50: d50321bf hint #0xd
54: d50321df hint #0xe
54: d50321df (hint #0xe|autib1716)
58: d50321ff hint #0xf
5c: d503221f (hint #0x10|esb)
60: d503223f (hint #0x11|psb csync)
@ -36,14 +36,14 @@ Disassembly of section \.text:
70: d50322bf hint #0x15
74: d50322df hint #0x16
78: d50322ff hint #0x17
7c: d503231f hint #0x18
80: d503233f hint #0x19
84: d503235f hint #0x1a
88: d503237f hint #0x1b
8c: d503239f hint #0x1c
90: d50323bf hint #0x1d
94: d50323df hint #0x1e
98: d50323ff hint #0x1f
7c: d503231f (hint #0x18|paciaz)
80: d503233f (hint #0x19|paciasp)
84: d503235f (hint #0x1a|pacibz)
88: d503237f (hint #0x1b|pacibsp)
8c: d503239f (hint #0x1c|autiaz)
90: d50323bf (hint #0x1d|autiasp)
94: d50323df (hint #0x1e|autibz)
98: d50323ff (hint #0x1f|autibsp)
9c: d503241f hint #0x20
a0: d503243f hint #0x21
a4: d503245f hint #0x22

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@ -1,3 +1,12 @@
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
autibsp.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.

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@ -422,8 +422,21 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1112: /* movz */
value = 1112; /* --> movz. */
break;
case 1126: /* psb */
case 1125: /* esb */
case 1151: /* autibsp */
case 1150: /* autibz */
case 1149: /* autiasp */
case 1148: /* autiaz */
case 1147: /* pacibsp */
case 1146: /* pacibz */
case 1145: /* paciasp */
case 1144: /* paciaz */
case 1131: /* psb */
case 1130: /* esb */
case 1129: /* autib1716 */
case 1128: /* autia1716 */
case 1127: /* pacib1716 */
case 1126: /* pacia1716 */
case 1125: /* xpaclri */
case 1124: /* sevl */
case 1123: /* sev */
case 1122: /* wfi */
@ -433,131 +446,131 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1118: /* hint */
value = 1118; /* --> hint. */
break;
case 1135: /* tlbi */
case 1134: /* ic */
case 1133: /* dc */
case 1132: /* at */
case 1131: /* sys */
value = 1131; /* --> sys. */
case 1140: /* tlbi */
case 1139: /* ic */
case 1138: /* dc */
case 1137: /* at */
case 1136: /* sys */
value = 1136; /* --> sys. */
break;
case 1881: /* bic */
case 1186: /* and */
value = 1186; /* --> and. */
case 1894: /* bic */
case 1199: /* and */
value = 1199; /* --> and. */
break;
case 1169: /* mov */
case 1188: /* and */
value = 1188; /* --> and. */
case 1182: /* mov */
case 1201: /* and */
value = 1201; /* --> and. */
break;
case 1173: /* movs */
case 1189: /* ands */
value = 1189; /* --> ands. */
case 1186: /* movs */
case 1202: /* ands */
value = 1202; /* --> ands. */
break;
case 1882: /* cmple */
case 1224: /* cmpge */
value = 1224; /* --> cmpge. */
case 1895: /* cmple */
case 1237: /* cmpge */
value = 1237; /* --> cmpge. */
break;
case 1885: /* cmplt */
case 1227: /* cmpgt */
value = 1227; /* --> cmpgt. */
case 1898: /* cmplt */
case 1240: /* cmpgt */
value = 1240; /* --> cmpgt. */
break;
case 1883: /* cmplo */
case 1229: /* cmphi */
value = 1229; /* --> cmphi. */
case 1896: /* cmplo */
case 1242: /* cmphi */
value = 1242; /* --> cmphi. */
break;
case 1884: /* cmpls */
case 1232: /* cmphs */
value = 1232; /* --> cmphs. */
case 1897: /* cmpls */
case 1245: /* cmphs */
value = 1245; /* --> cmphs. */
break;
case 1166: /* mov */
case 1254: /* cpy */
value = 1254; /* --> cpy. */
case 1179: /* mov */
case 1267: /* cpy */
value = 1267; /* --> cpy. */
break;
case 1168: /* mov */
case 1255: /* cpy */
value = 1255; /* --> cpy. */
case 1181: /* mov */
case 1268: /* cpy */
value = 1268; /* --> cpy. */
break;
case 1892: /* fmov */
case 1171: /* mov */
case 1256: /* cpy */
value = 1256; /* --> cpy. */
case 1905: /* fmov */
case 1184: /* mov */
case 1269: /* cpy */
value = 1269; /* --> cpy. */
break;
case 1161: /* mov */
case 1268: /* dup */
value = 1268; /* --> dup. */
case 1174: /* mov */
case 1281: /* dup */
value = 1281; /* --> dup. */
break;
case 1163: /* mov */
case 1160: /* mov */
case 1269: /* dup */
value = 1269; /* --> dup. */
case 1176: /* mov */
case 1173: /* mov */
case 1282: /* dup */
value = 1282; /* --> dup. */
break;
case 1891: /* fmov */
case 1165: /* mov */
case 1270: /* dup */
value = 1270; /* --> dup. */
case 1904: /* fmov */
case 1178: /* mov */
case 1283: /* dup */
value = 1283; /* --> dup. */
break;
case 1164: /* mov */
case 1271: /* dupm */
value = 1271; /* --> dupm. */
case 1177: /* mov */
case 1284: /* dupm */
value = 1284; /* --> dupm. */
break;
case 1886: /* eon */
case 1273: /* eor */
value = 1273; /* --> eor. */
case 1899: /* eon */
case 1286: /* eor */
value = 1286; /* --> eor. */
break;
case 1174: /* not */
case 1275: /* eor */
value = 1275; /* --> eor. */
case 1187: /* not */
case 1288: /* eor */
value = 1288; /* --> eor. */
break;
case 1175: /* nots */
case 1276: /* eors */
value = 1276; /* --> eors. */
case 1188: /* nots */
case 1289: /* eors */
value = 1289; /* --> eors. */
break;
case 1887: /* facle */
case 1281: /* facge */
value = 1281; /* --> facge. */
case 1900: /* facle */
case 1294: /* facge */
value = 1294; /* --> facge. */
break;
case 1888: /* faclt */
case 1282: /* facgt */
value = 1282; /* --> facgt. */
case 1901: /* faclt */
case 1295: /* facgt */
value = 1295; /* --> facgt. */
break;
case 1889: /* fcmle */
case 1291: /* fcmge */
value = 1291; /* --> fcmge. */
case 1902: /* fcmle */
case 1304: /* fcmge */
value = 1304; /* --> fcmge. */
break;
case 1890: /* fcmlt */
case 1293: /* fcmgt */
value = 1293; /* --> fcmgt. */
case 1903: /* fcmlt */
case 1306: /* fcmgt */
value = 1306; /* --> fcmgt. */
break;
case 1158: /* fmov */
case 1299: /* fcpy */
value = 1299; /* --> fcpy. */
case 1171: /* fmov */
case 1312: /* fcpy */
value = 1312; /* --> fcpy. */
break;
case 1157: /* fmov */
case 1316: /* fdup */
value = 1316; /* --> fdup. */
case 1170: /* fmov */
case 1329: /* fdup */
value = 1329; /* --> fdup. */
break;
case 1159: /* mov */
case 1614: /* orr */
value = 1614; /* --> orr. */
case 1172: /* mov */
case 1627: /* orr */
value = 1627; /* --> orr. */
break;
case 1893: /* orn */
case 1615: /* orr */
value = 1615; /* --> orr. */
case 1906: /* orn */
case 1628: /* orr */
value = 1628; /* --> orr. */
break;
case 1162: /* mov */
case 1617: /* orr */
value = 1617; /* --> orr. */
case 1175: /* mov */
case 1630: /* orr */
value = 1630; /* --> orr. */
break;
case 1172: /* movs */
case 1618: /* orrs */
value = 1618; /* --> orrs. */
case 1185: /* movs */
case 1631: /* orrs */
value = 1631; /* --> orrs. */
break;
case 1167: /* mov */
case 1674: /* sel */
value = 1674; /* --> sel. */
case 1180: /* mov */
case 1687: /* sel */
value = 1687; /* --> sel. */
break;
case 1170: /* mov */
case 1675: /* sel */
value = 1675; /* --> sel. */
case 1183: /* mov */
case 1688: /* sel */
value = 1688; /* --> sel. */
break;
default: return NULL;
}

File diff suppressed because it is too large Load Diff

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@ -276,17 +276,17 @@ static const unsigned op_enum_table [] =
382,
404,
406,
1162,
1167,
1160,
1159,
1163,
1170,
1172,
1173,
1169,
1175,
1174,
1180,
1173,
1172,
1176,
1183,
1185,
1186,
1182,
1188,
1187,
};
/* Given the opcode enumerator OP, return the pointer to the corresponding

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@ -1904,6 +1904,8 @@ static const aarch64_feature_set aarch64_feature_stat_profile =
AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
static const aarch64_feature_set aarch64_feature_sve =
AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0);
static const aarch64_feature_set aarch64_feature_v8_3 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@ -1919,6 +1921,7 @@ static const aarch64_feature_set aarch64_feature_sve =
#define STAT_PROFILE &aarch64_feature_stat_profile
#define ARMV8_2 &aarch64_feature_v8_2
#define SVE &aarch64_feature_sve
#define ARMV8_3 &aarch64_feature_v8_3
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
@ -1945,6 +1948,8 @@ static const aarch64_feature_set aarch64_feature_sve =
#define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
FLAGS | F_STRICT, TIED, NULL }
#define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
@ -3144,6 +3149,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
V8_3_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
{"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, 0, NULL},
{"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, 0, NULL},
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
@ -3158,6 +3168,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, 0),
CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0),
CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, 0),
V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
/* Test & branch (immediate). */
CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),