* MIPS CPU-specific dissasembly extensions. Now TM_PRINT_INSN_MACH from tm.h
sets a default mach for disassembly, just like sparc port. c.f. PR 15371. Tue Apr 21 11:20:54 1998 Frank Ch. Eigler <fche@cygnus.com> * mips-tdep.c (gdb_print_insn_mips): Disassemble MIPS instructions with subtarget-specific `mach', rather than fixed default. * config/mips/tm-mips.h (TM_PRINT_INSN_MACH): New macro, default disassembly `mach'. start-sanitize-r5900 * config/mips/tm-r5900.h (TM_PRINT_INSN_MACH): Override. end-sanitize-r5900 start-sanitize-sky * config/mips/tm-txvu.h (TM_PRINT_INSN_MACH): Override. end-sanitize-sky
This commit is contained in:
Frank Ch. Eigler
parent
171c7bbffe
commit
88ff9e0600
@ -1,3 +1,22 @@
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Tue Apr 21 11:20:54 1998 Frank Ch. Eigler <fche@cygnus.com>
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* mips-tdep.c (gdb_print_insn_mips): Disassemble MIPS instructions
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with subtarget-specific `mach', rather than fixed default.
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* config/mips/tm-mips.h (TM_PRINT_INSN_MACH): New macro, default
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disassembly `mach'.
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start-sanitize-r5900
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* config/mips/tm-r5900.h (TM_PRINT_INSN_MACH): Override.
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end-sanitize-r5900
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start-sanitize-sky
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* config/mips/tm-txvu.h (TM_PRINT_INSN_MACH): Override.
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end-sanitize-sky
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Mon Apr 20 15:35:03 1998 Philippe De Muyter <phdm@macqel.be>
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* coffread.c (decode_base_type): Treat a long field with size greater
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than TARGET_LONG_BIT as long long.
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* values.c (value_from_longest): Print code value in error message.
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Mon Apr 20 15:32:21 1998 Mark Kettenis <kettenis@phys.uva.nl>
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* gdb/gdb_string.h (strdup): Declare only if not defined as a
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@ -529,6 +529,11 @@ extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
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#define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
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/* Select the default mips disassembler */
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#define TM_PRINT_INSN_MACH 0
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/* These are defined in mdebugread.c and are used in mips-tdep.c */
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extern CORE_ADDR sigtramp_address, sigtramp_end;
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extern void fixup_sigtramp PARAMS ((void));
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443
gdb/mips-tdep.c
443
gdb/mips-tdep.c
@ -353,6 +353,445 @@ mips_fetch_instruction (addr)
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}
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/* These the fields of 32 bit mips instructions */
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#define mips32_op(x) (x >> 25)
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#define itype_op(x) (x >> 25)
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#define itype_rs(x) ((x >> 21)& 0x1f)
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#define itype_rt(x) ((x >> 16) & 0x1f)
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#define itype_immediate(x) ( x & 0xffff)
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#define jtype_op(x) (x >> 25)
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#define jtype_target(x) ( x & 0x03fffff)
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#define rtype_op(x) (x >>25)
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#define rtype_rs(x) ((x>>21) & 0x1f)
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#define rtype_rt(x) ((x>>16) & 0x1f)
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#define rtype_rd(x) ((x>>11) & 0x1f)
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#define rtype_shamt(x) ((x>>6) & 0x1f)
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#define rtype_funct(x) (x & 0x3f )
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static CORE_ADDR
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mips32_relative_offset(unsigned long inst)
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{ long x ;
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x = itype_immediate(inst) ;
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if (x & 0x8000) /* sign bit set */
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{
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x |= 0xffff0000 ; /* sign extension */
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}
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x = x << 2 ;
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return x ;
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}
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/* Determine whate to set a single step breakpoint while considering
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branch prediction */
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CORE_ADDR
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mips32_next_pc(CORE_ADDR pc)
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{
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unsigned long inst ;
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int op ;
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inst = mips_fetch_instruction(pc) ;
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if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */
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{ if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
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{ op = ((inst >> 25) & 0x03) ;
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switch (op)
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{
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case 0 : goto equal_branch ; /* BEQL */
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case 1 : goto neq_branch ; /* BNEZ */
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case 2 : goto less_branch ; /* BLEZ */
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case 3 : goto greater_branch ; /* BGTZ */
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default : pc += 4 ;
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}
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}
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else pc += 4 ; /* Not a branch, next instruction is easy */
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}
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else
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{ /* This gets way messy */
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/* Further subdivide into SPECIAL, REGIMM and other */
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switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */
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{
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case 0 : /* SPECIAL */
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op = rtype_funct(inst) ;
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switch (op)
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{
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case 8 : /* JR */
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case 9 : /* JALR */
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pc = read_register(rtype_rs(inst)) ; /* Set PC to that address */
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break ;
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default: pc += 4 ;
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}
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break ; /* end special */
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case 1 : /* REGIMM */
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{
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op = jtype_op(inst) ; /* branch condition */
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switch (jtype_op(inst))
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{
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case 0 : /* BLTZ */
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case 2 : /* BLTXL */
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case 16 : /* BLTZALL */
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case 18 : /* BLTZALL */
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less_branch:
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if (read_register(itype_rs(inst)) < 0)
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pc += mips32_relative_offset(inst) + 4 ;
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else pc += 8 ; /* after the delay slot */
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break ;
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case 1 : /* GEZ */
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case 3 : /* BGEZL */
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case 17 : /* BGEZAL */
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case 19 : /* BGEZALL */
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greater_equal_branch:
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if (read_register(itype_rs(inst)) >= 0)
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pc += mips32_relative_offset(inst) + 4 ;
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else pc += 8 ; /* after the delay slot */
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break ;
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/* All of the other intructions in the REGIMM catagory */
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default: pc += 4 ;
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}
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}
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break ; /* end REGIMM */
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case 2 : /* J */
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case 3 : /* JAL */
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{ unsigned long reg ;
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reg = jtype_target(inst) << 2 ;
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pc = reg + ((pc+4) & 0xf0000000) ;
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/* Whats this mysterious 0xf000000 adjustment ??? */
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}
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break ;
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/* FIXME case JALX :*/
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{ unsigned long reg ;
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reg = jtype_target(inst) << 2 ;
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pc = reg + ((pc+4) & 0xf0000000) + 1 ; /* yes, +1 */
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/* Add 1 to indicate 16 bit mode - Invert ISA mode */
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}
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break ; /* The new PC will be alternate mode */
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case 4 : /* BEQ , BEQL */
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equal_branch :
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if (read_register(itype_rs(inst)) ==
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read_register(itype_rt(inst)))
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pc += mips32_relative_offset(inst) + 4 ;
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else pc += 8 ;
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break ;
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case 5 : /* BNE , BNEL */
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neq_branch :
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if (read_register(itype_rs(inst)) !=
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read_register(itype_rs(inst)))
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pc += mips32_relative_offset(inst) + 4 ;
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else pc += 8 ;
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break ;
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case 6 : /* BLEZ , BLEZL */
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less_zero_branch:
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if (read_register(itype_rs(inst) <= 0))
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pc += mips32_relative_offset(inst) + 4 ;
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else pc += 8 ;
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break ;
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case 7 :
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greater_branch : /* BGTZ BGTZL */
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if (read_register(itype_rs(inst) > 0))
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pc += mips32_relative_offset(inst) + 4 ;
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else pc += 8 ;
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break ;
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default : pc += 8 ;
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} /* switch */
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} /* else */
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return pc ;
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} /* mips32_next_pc */
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/* Decoding the next place to set a breakpoint is irregular for the
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mips 16 variant, but fortunatly, there fewer instructions. We have to cope
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ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
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We dont want to set a single step instruction on the extend instruction
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either.
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*/
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/* Lots of mips16 instruction formats */
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/* Predicting jumps requires itype,ritype,i8type
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and their extensions extItype,extritype,extI8type
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*/
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enum mips16_inst_fmts
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{
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itype, /* 0 immediate 5,10 */
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ritype, /* 1 5,3,8 */
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rrtype, /* 2 5,3,3,5 */
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rritype, /* 3 5,3,3,5 */
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rrrtype, /* 4 5,3,3,3,2 */
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rriatype, /* 5 5,3,3,1,4 */
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shifttype, /* 6 5,3,3,3,2 */
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i8type, /* 7 5,3,8 */
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i8movtype, /* 8 5,3,3,5 */
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i8mov32rtype, /* 9 5,3,5,3 */
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i64type, /* 10 5,3,8 */
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ri64type, /* 11 5,3,3,5 */
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jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
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exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
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extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
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extRRItype, /* 15 5,5,5,5,3,3,5 */
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extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
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EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
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extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
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extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
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extRi64type, /* 20 5,6,5,5,3,3,5 */
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extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
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} ;
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/* I am heaping all the fields of the formats into one structure and then,
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only the fields which are involved in instruction extension */
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struct upk_mips16
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{
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unsigned short inst ;
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enum mips16_inst_fmts fmt ;
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unsigned long offset ;
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unsigned int regx ; /* Function in i8 type */
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unsigned int regy ;
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} ;
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static void print_unpack(char * comment,
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struct upk_mips16 * u)
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{
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printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
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comment,u->inst,u->fmt,u->offset,u->regx,u->regy) ;
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}
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/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
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format for the bits which make up the immediatate extension.
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*/
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static unsigned long
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extended_offset(unsigned long extension)
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{
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unsigned long value ;
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value = (extension >> 21) & 0x3f ; /* * extract 15:11 */
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value = value << 6 ;
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value |= (extension >> 16) & 0x1f ; /* extrace 10:5 */
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value = value << 5 ;
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value |= extension & 0x01f ; /* extract 4:0 */
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return value ;
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}
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/* Only call this function if you know that this is an extendable
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instruction, It wont malfunction, but why make excess remote memory references?
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If the immediate operands get sign extended or somthing, do it after
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the extension is performed.
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*/
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/* FIXME: Every one of these cases needs to worry about sign extension
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when the offset is to be used in relative addressing */
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static unsigned short fetch_mips_16(CORE_ADDR pc)
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{
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char buf[8] ;
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pc &= 0xfffffffe ; /* clear the low order bit */
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target_read_memory(pc,buf,2) ;
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return extract_unsigned_integer(buf,2) ;
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}
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static void
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unpack_mips16(CORE_ADDR pc,
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struct upk_mips16 * upk)
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{
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CORE_ADDR extpc ;
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unsigned long extension ;
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int extended ;
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extpc = (pc - 4) & ~0x01 ; /* Extensions are 32 bit instructions */
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/* Decrement to previous address and loose the 16bit mode flag */
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/* return if the instruction was extendable, but not actually extended */
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extended = ((mips32_op(extension) == 30) ? 1 : 0) ;
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if (extended) { extension = mips_fetch_instruction(extpc) ;}
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switch (upk->fmt)
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{
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case itype :
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{
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unsigned long value ;
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if (extended)
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{ value = extended_offset(extension) ;
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value = value << 11 ; /* rom for the original value */
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value |= upk->inst & 0x7ff ; /* eleven bits from instruction */
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}
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else
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{ value = upk->inst & 0x7ff ;
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/* FIXME : Consider sign extension */
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}
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upk->offset = value ;
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}
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break ;
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case ritype :
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case i8type :
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{ /* A register identifier and an offset */
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/* Most of the fields are the same as I type but the
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immediate value is of a different length */
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unsigned long value ;
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if (extended)
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{
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value = extended_offset(extension) ;
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value = value << 8 ; /* from the original instruction */
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value |= upk->inst & 0xff ; /* eleven bits from instruction */
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upk->regx = (extension >> 8) & 0x07 ; /* or i8 funct */
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if (value & 0x4000) /* test the sign bit , bit 26 */
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{ value &= ~ 0x3fff ; /* remove the sign bit */
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value = -value ;
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}
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}
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else {
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value = upk->inst & 0xff ; /* 8 bits */
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upk->regx = (upk->inst >> 8) & 0x07 ; /* or i8 funct */
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/* FIXME: Do sign extension , this format needs it */
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if (value & 0x80) /* THIS CONFUSES ME */
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{ value &= 0xef ; /* remove the sign bit */
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value = -value ;
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}
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}
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upk->offset = value ;
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break ;
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}
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case jalxtype :
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{
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unsigned long value ;
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unsigned short nexthalf ;
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value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f) ;
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value = value << 16 ;
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nexthalf = mips_fetch_instruction(pc+2) ; /* low bit still set */
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value |= nexthalf ;
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upk->offset = value ;
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break ;
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}
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default:
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printf_filtered("Decoding unimplemented instruction format type\n") ;
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break ;
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}
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/* print_unpack("UPK",upk) ; */
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}
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#define mips16_op(x) (x >> 11)
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/* This is a map of the opcodes which ae known to perform branches */
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static unsigned char map16[32] =
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{ 0,0,1,1,1,1,0,0,
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0,0,0,0,1,0,0,0,
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0,0,0,0,0,0,0,0,
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0,0,0,0,0,1,1,0
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} ;
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static CORE_ADDR add_offset_16(CORE_ADDR pc, int offset)
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{
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return ((offset << 2) | ((pc + 2) & (0xf0000000))) ;
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}
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static struct upk_mips16 upk ;
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CORE_ADDR mips16_next_pc(CORE_ADDR pc)
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{
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int op ;
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t_inst inst ;
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/* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
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inst = fetch_mips_16(pc) ;
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upk.inst = inst ;
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op = mips16_op(upk.inst) ;
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if (map16[op])
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{
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int reg ;
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switch (op)
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{
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case 2 : /* Branch */
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upk.fmt = itype ;
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unpack_mips16(pc,&upk) ;
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{ long offset ;
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offset = upk.offset ;
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if (offset & 0x800)
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{ offset &= 0xeff ;
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offset = - offset ;
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}
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pc += (offset << 1) + 2 ;
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}
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break ;
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case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
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upk.fmt = jalxtype ;
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unpack_mips16(pc,&upk) ;
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pc = add_offset_16(pc,upk.offset) ;
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if ((upk.inst >> 10) & 0x01) /* Exchange mode */
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pc = pc & ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
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else pc |= 0x01 ;
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break ;
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case 4 : /* beqz */
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upk.fmt = ritype ;
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unpack_mips16(pc,&upk) ;
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reg = read_register(upk.regx) ;
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if (reg == 0)
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pc += (upk.offset << 1) + 2 ;
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else pc += 2 ;
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break ;
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case 5 : /* bnez */
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upk.fmt = ritype ;
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unpack_mips16(pc,&upk) ;
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reg = read_register(upk.regx) ;
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if (reg != 0)
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pc += (upk.offset << 1) + 2 ;
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else pc += 2 ;
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break ;
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case 12 : /* I8 Formats btez btnez */
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upk.fmt = i8type ;
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unpack_mips16(pc,&upk) ;
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/* upk.regx contains the opcode */
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reg = read_register(24) ; /* Test register is 24 */
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if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
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|| ((upk.regx == 1 ) && (reg != 0))) /* BTNEZ */
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/* pc = add_offset_16(pc,upk.offset) ; */
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pc += (upk.offset << 1) + 2 ;
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else pc += 2 ;
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break ;
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case 29 : /* RR Formats JR, JALR, JALR-RA */
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upk.fmt = rrtype ;
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op = upk.inst & 0x1f ;
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if (op == 0)
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{
|
||||
upk.regx = (upk.inst >> 8) & 0x07 ;
|
||||
upk.regy = (upk.inst >> 5) & 0x07 ;
|
||||
switch (upk.regy)
|
||||
{
|
||||
case 0 : reg = upk.regx ; break ;
|
||||
case 1 : reg = 31 ; break ; /* Function return instruction*/
|
||||
case 2 : reg = upk.regx ; break ;
|
||||
default: reg = 31 ; break ; /* BOGUS Guess */
|
||||
}
|
||||
pc = read_register(reg) ;
|
||||
}
|
||||
else pc += 2 ;
|
||||
break ;
|
||||
case 30 : /* This is an extend instruction */
|
||||
pc += 4 ; /* Dont be setting breakpints on the second half */
|
||||
break ;
|
||||
default :
|
||||
printf("Filtered - next PC probably incorrrect due to jump inst\n");
|
||||
pc += 2 ;
|
||||
break ;
|
||||
}
|
||||
}
|
||||
else pc+= 2 ; /* just a good old instruction */
|
||||
/* See if we CAN actually break on the next instruction */
|
||||
/* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
|
||||
return pc ;
|
||||
} /* mips16_next_pc */
|
||||
|
||||
/* The mips_next_pc function supports single_tep when the remote target monitor or
|
||||
stub is not developed enough to so a single_step.
|
||||
It works by decoding the current instruction and predicting where a branch
|
||||
will go. This isnt hard because all the data is available.
|
||||
The MIPS32 and MIPS16 variants are quite different
|
||||
*/
|
||||
CORE_ADDR mips_next_pc(CORE_ADDR pc)
|
||||
{
|
||||
t_inst inst ;
|
||||
/* inst = mips_fetch_instruction(pc) ; */
|
||||
/* if (pc_is_mips16) <----- This is failing */
|
||||
if (pc & 0x01)
|
||||
return mips16_next_pc(pc) ;
|
||||
else return mips32_next_pc(pc) ;
|
||||
} /* mips_next_pc */
|
||||
|
||||
/* Guaranteed to set fci->saved_regs to some values (it never leaves it
|
||||
NULL). */
|
||||
|
||||
@ -2385,9 +2824,9 @@ gdb_print_insn_mips (memaddr, info)
|
||||
it's definitely a 16-bit function. Otherwise, we have to just
|
||||
guess that if the address passed in is odd, it's 16-bits. */
|
||||
if (proc_desc)
|
||||
info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : 0;
|
||||
info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH;
|
||||
else
|
||||
info->mach = pc_is_mips16 (memaddr) ? 16 : 0;
|
||||
info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH;
|
||||
|
||||
/* Round down the instruction address to the appropriate boundary. */
|
||||
memaddr &= (info->mach == 16 ? ~1 : ~3);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user