* armemu.h (WRITEDESTB): New macro.
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to modify PC. Moved the existing logic... (WriteR15Branch): ... here. New function. (WriteR15, WriteSR15): Drop the two least significant bits. (LoadSMult): Use WriteR15Branch() to modify PC. (LoadMult): Use WRITEDESTB() instead of WRITEDEST().
This commit is contained in:
Alexandre Oliva
parent
cf52c765b0
commit
892c6b9d8f
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@ -1,5 +1,13 @@
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2000-07-04 Alexandre Oliva <aoliva@redhat.com>
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* armemu.h (WRITEDESTB): New macro.
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* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
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modify PC. Moved the existing logic...
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(WriteR15Branch): ... here. New function.
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(WriteR15, WriteSR15): Drop the two least significant bits.
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(LoadSMult): Use WriteR15Branch() to modify PC.
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(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
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* armemu.h (GETSPSR): Call ARMul_GetSPSR().
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* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
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extracted from state->Cpsr, but preserve the unused bits.
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@ -24,6 +24,7 @@ static ARMword GetDPRegRHS (ARMul_State * state, ARMword instr);
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static ARMword GetDPSRegRHS (ARMul_State * state, ARMword instr);
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static void WriteR15 (ARMul_State * state, ARMword src);
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static void WriteSR15 (ARMul_State * state, ARMword src);
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static void WriteR15Branch (ARMul_State * state, ARMword src);
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static ARMword GetLSRegRHS (ARMul_State * state, ARMword instr);
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static ARMword GetLS7RHS (ARMul_State * state, ARMword instr);
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static unsigned LoadWord (ARMul_State * state, ARMword instr,
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@ -1082,35 +1083,8 @@ ARMul_Emulate26 (register ARMul_State * state)
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#ifdef MODET
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if (BITS (4, 27) == 0x12FFF1)
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{ /* BX */
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/* Branch to the address in RHSReg. If bit0 of
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destination address is 1 then switch to Thumb mode: */
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ARMword addr = state->Reg[RHSReg];
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/* If we read the PC then the bottom bit is clear */
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if (RHSReg == 15)
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addr &= ~1;
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/* Enable this for a helpful bit of debugging when
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GDB is not yet fully working...
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fprintf (stderr, "BX at %x to %x (go %s)\n",
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state->Reg[15], addr, (addr & 1) ? "thumb": "arm" ); */
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if (addr & (1 << 0))
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{ /* Thumb bit */
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SETT;
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state->Reg[15] = addr & 0xfffffffe;
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/* NOTE: The other CPSR flag setting blocks do not
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seem to update the state->Cpsr state, but just do
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the explicit flag. The copy from the seperate
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flags to the register must happen later. */
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FLUSHPIPE;
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}
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else
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{
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CLEART;
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state->Reg[15] = addr & 0xfffffffc;
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FLUSHPIPE;
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}
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WriteR15Branch (state, state->Reg[RHSReg]);
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break;
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}
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#endif
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if (DESTReg == 15)
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@ -3128,11 +3102,14 @@ GetDPSRegRHS (ARMul_State * state, ARMword instr)
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static void
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WriteR15 (ARMul_State * state, ARMword src)
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{
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/* The ARM documentation implies (but doe snot state) that the bottom bit of the PC is never set */
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/* The ARM documentation states that the two least significant bits
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are discarded when setting PC, except in the cases handled by
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WriteR15Branch() below. */
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src &= 0xfffffffc;
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#ifdef MODE32
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state->Reg[15] = src & PCBITS & ~0x1;
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state->Reg[15] = src & PCBITS;
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#else
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state->Reg[15] = (src & R15PCBITS & ~0x1) | ECC | ER15INT | EMODE;
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state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE;
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ARMul_R15Altered (state);
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#endif
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FLUSHPIPE;
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@ -3145,6 +3122,7 @@ WriteR15 (ARMul_State * state, ARMword src)
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static void
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WriteSR15 (ARMul_State * state, ARMword src)
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{
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src &= 0xfffffffc;
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#ifdef MODE32
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state->Reg[15] = src & PCBITS;
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if (state->Bank > 0)
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@ -3162,6 +3140,29 @@ WriteSR15 (ARMul_State * state, ARMword src)
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FLUSHPIPE;
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}
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/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
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will switch to Thumb mode if the least significant bit is set. */
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static void
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WriteR15Branch (ARMul_State * state, ARMword src)
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{
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#ifdef MODET
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if (src & 1)
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{ /* Thumb bit */
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SETT;
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state->Reg[15] = src & 0xfffffffe;
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}
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else
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{
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CLEART;
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state->Reg[15] = src & 0xfffffffc;
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}
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FLUSHPIPE;
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#else
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WriteR15 (state, src);
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#endif
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}
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/***************************************************************************\
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* This routine evaluates most Load and Store register RHS's. It is *
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* intended to be called from the macro LSRegRHS, which filters the *
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@ -3249,7 +3250,7 @@ LoadWord (ARMul_State * state, ARMword instr, ARMword address)
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}
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if (address & 3)
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dest = ARMul_Align (state, address, dest);
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WRITEDEST (dest);
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WRITEDESTB (dest);
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ARMul_Icycles (state, 1, 0L);
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return (DESTReg != LHSReg);
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@ -3471,10 +3472,7 @@ LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
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if (BIT (15) && !state->Aborted)
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{ /* PC is in the reg list */
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#ifdef MODE32
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state->Reg[15] = PC;
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#endif
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FLUSHPIPE;
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WriteR15Branch(state, PC);
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}
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ARMul_Icycles (state, 1, 0L); /* to write back the final register */
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@ -332,6 +332,11 @@ extern ARMword isize;
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ARMul_NegZero(state, d) ; \
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}
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#define WRITEDESTB(d) if (DESTReg == 15) \
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WriteR15Branch(state, d) ; \
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else \
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DEST = d
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#define BYTETOBUS(data) ((data & 0xff) | \
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((data & 0xff) << 8) | \
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((data & 0xff) << 16) | \
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