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[AArch64] Fix bogus MOVPRFX warning for GPR form of CPY 

One of the MOVPRFX tests has:

  output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'

But X1 and Z1 are not the same register, so the instruction is
actually OK.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
	registers in an instruction prefixed by MOVPRFX.

gas/
	* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
	to be prefixed by MOVPRFX.
	* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
This commit is contained in:
Richard Sandiford 2019-07-02 10:51:05 +01:00
parent 390b205f45
commit 8941884429
6 changed files with 14 additions and 8 deletions
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7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
to be prefixed by MOVPRFX.
* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
2019-07-01 Nick Clifton <nickc@redhat.com>
PR 24748

2
gas/testsuite/gas/aarch64/sve-movprfx_25.d
View File

@ -21,7 +21,7 @@ Disassembly of section .*:
[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
[^:]+: 05e8a441 mov z1.d, p1/m, x2
[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
[^:]+: 05e8a421 mov z1.d, p1/m, x1 // note: output register of preceding `movprfx' used as input at operand 3
[^:]+: 05e8a421 mov z1.d, p1/m, x1
[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
[^:]+: 05e08441 mov z1.d, p1/m, d2
[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d

1
gas/testsuite/gas/aarch64/sve-movprfx_25.l
View File

@ -1,5 +1,4 @@
[^:]*: Assembler messages:
.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `cpy z1.d,p9/m,#12'
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `cpy z1.d,p1/z,#12'
.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'
.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,d1'

2
gas/testsuite/gas/aarch64/sve-movprfx_25.s
View File

@ -29,7 +29,7 @@ f:
movprfx z1.d, p1/m, z3.d
cpy z1.d, p1/m, x2
/* Not OK, scalar but register z1 and x1 are architecturally the same. */
/* OK, scalar predicated, alias mov. */
movprfx z1.d, p1/m, z3.d
cpy z1.d, p1/m, x1

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
registers in an instruction prefixed by MOVPRFX.
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new

5
opcodes/aarch64-opc.c
View File

@ -4968,11 +4968,6 @@ verify_constraints (const struct aarch64_inst *inst,
case AARCH64_OPND_Vm:
case AARCH64_OPND_Sn:
case AARCH64_OPND_Sm:
case AARCH64_OPND_Rn:
case AARCH64_OPND_Rm:
case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_Rt_SP:
case AARCH64_OPND_Rm_SP:
if (inst_op.reg.regno == blk_dest.reg.regno)
{
num_op_used++;