[PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (is_mve_encoding_conflict): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_rotate): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
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Andre Vieira
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897b9bbcff
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@ -1,3 +1,13 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_unpredictable): Likewise.
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(print_mve_rotate): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -179,6 +179,11 @@ enum mve_instructions
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MVE_VDWDUP,
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MVE_VIWDUP,
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MVE_VIDUP,
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MVE_VCADD_FP,
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MVE_VCADD_VEC,
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MVE_VHCADD,
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MVE_VCMLA_FP,
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MVE_VCMUL_FP,
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MVE_NONE
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};
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@ -1964,6 +1969,7 @@ static const struct opcode32 neon_opcodes[] =
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%<bitfield>h print high half of 64-bit destination reg
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%<bitfield>k print immediate for vector conversion instruction
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%<bitfield>l print low half of 64-bit destination reg
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%<bitfield>o print rotate value for vcmul
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%<bitfield>u print immediate value for vddup/vdwdup
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%<bitfield>x print the bitfield in hex.
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*/
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@ -2044,6 +2050,24 @@ static const struct mopcode32 mve_opcodes[] =
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0xeef10f00, 0xeff31fd1,
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"vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
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/* Vector VCADD floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCADD_FP,
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0xfc800840, 0xfea11f51,
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"vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
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/* Vector VCADD. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VCADD_VEC,
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0xfe000f00, 0xff810f51,
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"vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
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/* Vector VCMLA. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCMLA_FP,
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0xfc200840, 0xfe211f51,
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"vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
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/* Vector VCMP floating point T1. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCMP_FP_T1,
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@ -2147,6 +2171,12 @@ static const struct mopcode32 mve_opcodes[] =
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0xee001f40, 0xef811f70,
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"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VCMUL. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCMUL_FP,
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0xee300e00, 0xefb10f50,
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"vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
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/* Vector VDUP. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VDUP,
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@ -2201,6 +2231,12 @@ static const struct mopcode32 mve_opcodes[] =
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0xee011f60, 0xff811f70,
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"vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
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/* Vector VHCADD. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VHCADD,
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0xee000f00, 0xff810f51,
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"vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
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/* Vector VIWDUP. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VIWDUP,
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@ -4698,6 +4734,8 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VCADD_VEC:
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case MVE_VHCADD:
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case MVE_VDDUP:
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case MVE_VIDUP:
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case MVE_VQRDMLADH:
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@ -5518,6 +5556,7 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VCMUL_FP:
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case MVE_VQDMULL_T1:
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{
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unsigned long Qd;
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@ -5596,6 +5635,58 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VCADD_VEC:
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case MVE_VHCADD:
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{
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unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
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if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
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{
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*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
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return TRUE;
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}
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else
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return FALSE;
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}
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case MVE_VCADD_FP:
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{
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unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
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if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
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{
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*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
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return TRUE;
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}
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else
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return FALSE;
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}
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case MVE_VCMLA_FP:
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{
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unsigned long Qda;
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unsigned long Qm;
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unsigned long Qn;
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if (arm_decode_field (given, 20, 20) == 1)
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{
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Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
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Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
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Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
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if ((Qda == Qn) || (Qda == Qm))
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{
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*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
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return TRUE;
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}
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else
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return FALSE;
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}
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else
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -6203,6 +6294,49 @@ print_mve_vcvt_size (struct disassemble_info *info,
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}
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}
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static void
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print_mve_rotate (struct disassemble_info *info, unsigned long rot,
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unsigned long rot_width)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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if (rot_width == 1)
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{
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switch (rot)
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{
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case 0:
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func (stream, "90");
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break;
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case 1:
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func (stream, "270");
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break;
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default:
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break;
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}
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}
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else if (rot_width == 2)
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{
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switch (rot)
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{
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case 0:
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func (stream, "0");
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break;
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case 1:
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func (stream, "90");
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break;
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case 2:
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func (stream, "180");
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break;
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case 3:
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func (stream, "270");
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break;
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default:
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break;
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}
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}
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}
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static void
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print_instruction_predicate (struct disassemble_info *info)
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{
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@ -6226,6 +6360,7 @@ print_mve_size (struct disassemble_info *info,
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switch (matched_insn)
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{
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case MVE_VADDV:
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case MVE_VCADD_VEC:
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case MVE_VCMP_VEC_T1:
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case MVE_VCMP_VEC_T2:
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case MVE_VCMP_VEC_T3:
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@ -6236,6 +6371,7 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VDWDUP:
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case MVE_VHADD_T1:
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case MVE_VHADD_T2:
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case MVE_VHCADD:
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case MVE_VHSUB_T1:
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case MVE_VHSUB_T2:
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case MVE_VIDUP:
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@ -6296,6 +6432,9 @@ print_mve_size (struct disassemble_info *info,
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func (stream, "16");
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break;
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case MVE_VCADD_FP:
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case MVE_VCMLA_FP:
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case MVE_VCMUL_FP:
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case MVE_VMLADAV_T1:
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case MVE_VMLALDAV:
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case MVE_VMLSDAV_T1:
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@ -8061,6 +8200,9 @@ print_insn_mve (struct disassemble_info *info, long given)
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break;
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}
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break;
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case 'o':
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print_mve_rotate (info, value, width);
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break;
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case 'r':
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func (stream, "%s", arm_regnames[value]);
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break;
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