[AArch64, Binutils] Make hint space instructions valid for Armv8-a
There are a few instruction in AArch64 that are in the HINT space. Any of these instructions should be accepted by the assembler/disassembler at any architecture version. This patch fixes the existing instructions that are not behaving accordingly. I have used all of the instructions mentioned in the following to make the changes: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ hint-hint-instruction gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/bti.d: Update -march option. * testsuite/gas/aarch64/illegal-bti.d: Remove. * testsuite/gas/aarch64/illegal-bti.l: Remove. * testsuite/gas/aarch64/illegal-ras-1.l: Remove esb. * testsuite/gas/aarch64/illegal-ras-1.s: Remove esb. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. (aarch64_feature_ras, RAS): Likewise. (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz, autibsp to be CORE_INSN. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
This commit is contained in:
Sudakshina Das
parent
3052c068aa
commit
8a6e1d1d7f
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@ -1,3 +1,11 @@
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/bti.d: Update -march option.
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* testsuite/gas/aarch64/illegal-bti.d: Remove.
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* testsuite/gas/aarch64/illegal-bti.l: Remove.
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* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
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* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
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2020-04-17 Alan Modra <amodra@gmail.com>
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* config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
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@ -1,4 +1,4 @@
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#as: -march=armv8.5-a
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#as: -march=armv8-a
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#objdump: -dr
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.*: file format .*
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@ -1,3 +0,0 @@
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#as: -march=armv8-a
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#source: bti.s
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#error_output: illegal-bti.l
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@ -1,8 +0,0 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: selected processor does not support `bti'
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[^:]*:[0-9]+: Error: selected processor does not support `bti c'
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[^:]*:[0-9]+: Error: selected processor does not support `bti j'
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[^:]*:[0-9]+: Error: selected processor does not support `bti jc'
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[^:]*:[0-9]+: Error: selected processor does not support `bti C'
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[^:]*:[0-9]+: Error: selected processor does not support `bti J'
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[^:]*:[0-9]+: Error: selected processor does not support `bti JC'
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@ -1,5 +1,4 @@
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[^:]+: Assembler messages:
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^[^:]+:[0-9]+: Error: selected processor does not support `esb'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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@ -18,7 +17,6 @@
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
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^[^:]+:[0-9]+: Error: selected processor does not support `esb'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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@ -12,7 +12,6 @@
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/* ARMv8-A. */
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.arch armv8-a
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esb
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hint #0x10
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rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
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@ -33,7 +32,6 @@
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/* ARMv8.1-A. */
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.arch armv8.1-a
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esb
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hint #0x10
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rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
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@ -1,3 +1,15 @@
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
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(aarch64_feature_ras, RAS): Likewise.
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(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
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(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
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autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
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autiaz, autiasp, autibz, autibsp to be CORE_INSN.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2020-04-17 Fredrik Strupe <fredrik@strupe.net>
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* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
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@ -426,21 +426,21 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1183: /* movz */
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value = 1183; /* --> movz. */
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break;
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case 1235: /* autibsp */
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case 1234: /* autibz */
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case 1233: /* autiasp */
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case 1232: /* autiaz */
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case 1231: /* pacibsp */
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case 1230: /* pacibz */
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case 1229: /* paciasp */
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case 1228: /* paciaz */
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case 1208: /* psb */
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case 1207: /* esb */
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case 1206: /* autib1716 */
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case 1205: /* autia1716 */
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case 1204: /* pacib1716 */
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case 1203: /* pacia1716 */
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case 1202: /* xpaclri */
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case 1236: /* autibsp */
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case 1235: /* autibz */
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case 1234: /* autiasp */
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case 1233: /* autiaz */
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case 1232: /* pacibsp */
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case 1231: /* pacibz */
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case 1230: /* paciasp */
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case 1229: /* paciaz */
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case 1209: /* psb */
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case 1208: /* esb */
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case 1207: /* autib1716 */
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case 1206: /* autia1716 */
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case 1205: /* pacib1716 */
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case 1204: /* pacia1716 */
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case 1203: /* xpaclri */
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case 1201: /* sevl */
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case 1200: /* sev */
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case 1199: /* wfi */
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@ -452,140 +452,140 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1193: /* hint */
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value = 1193; /* --> hint. */
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break;
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case 1212: /* pssbb */
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case 1211: /* ssbb */
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case 1210: /* dsb */
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value = 1210; /* --> dsb. */
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case 1213: /* pssbb */
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case 1212: /* ssbb */
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case 1211: /* dsb */
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value = 1211; /* --> dsb. */
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break;
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case 1223: /* cpp */
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case 1222: /* dvp */
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case 1221: /* cfp */
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case 1220: /* tlbi */
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case 1219: /* ic */
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case 1218: /* dc */
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case 1217: /* at */
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case 1216: /* sys */
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value = 1216; /* --> sys. */
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case 1224: /* cpp */
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case 1223: /* dvp */
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case 1222: /* cfp */
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case 1221: /* tlbi */
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case 1220: /* ic */
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case 1219: /* dc */
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case 1218: /* at */
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case 1217: /* sys */
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value = 1217; /* --> sys. */
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break;
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case 2033: /* bic */
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case 1283: /* and */
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value = 1283; /* --> and. */
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case 2034: /* bic */
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case 1284: /* and */
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value = 1284; /* --> and. */
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break;
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case 1266: /* mov */
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case 1285: /* and */
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value = 1285; /* --> and. */
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case 1267: /* mov */
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case 1286: /* and */
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value = 1286; /* --> and. */
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break;
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case 1270: /* movs */
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case 1286: /* ands */
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value = 1286; /* --> ands. */
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case 1271: /* movs */
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case 1287: /* ands */
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value = 1287; /* --> ands. */
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break;
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case 2034: /* cmple */
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case 1321: /* cmpge */
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value = 1321; /* --> cmpge. */
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case 2035: /* cmple */
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case 1322: /* cmpge */
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value = 1322; /* --> cmpge. */
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break;
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case 2037: /* cmplt */
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case 1324: /* cmpgt */
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value = 1324; /* --> cmpgt. */
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case 2038: /* cmplt */
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case 1325: /* cmpgt */
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value = 1325; /* --> cmpgt. */
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break;
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case 2035: /* cmplo */
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case 1326: /* cmphi */
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value = 1326; /* --> cmphi. */
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case 2036: /* cmplo */
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case 1327: /* cmphi */
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value = 1327; /* --> cmphi. */
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break;
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case 2036: /* cmpls */
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case 1329: /* cmphs */
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value = 1329; /* --> cmphs. */
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case 2037: /* cmpls */
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case 1330: /* cmphs */
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value = 1330; /* --> cmphs. */
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break;
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case 1263: /* mov */
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case 1351: /* cpy */
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value = 1351; /* --> cpy. */
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break;
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case 1265: /* mov */
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case 1264: /* mov */
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case 1352: /* cpy */
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value = 1352; /* --> cpy. */
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break;
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case 2044: /* fmov */
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case 1268: /* mov */
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case 1266: /* mov */
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case 1353: /* cpy */
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value = 1353; /* --> cpy. */
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break;
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case 1258: /* mov */
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case 1365: /* dup */
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value = 1365; /* --> dup. */
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case 2045: /* fmov */
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case 1269: /* mov */
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case 1354: /* cpy */
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value = 1354; /* --> cpy. */
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break;
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case 1260: /* mov */
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case 1257: /* mov */
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case 1259: /* mov */
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case 1366: /* dup */
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value = 1366; /* --> dup. */
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break;
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case 2043: /* fmov */
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case 1262: /* mov */
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case 1261: /* mov */
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case 1258: /* mov */
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case 1367: /* dup */
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value = 1367; /* --> dup. */
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break;
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case 1261: /* mov */
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case 1368: /* dupm */
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value = 1368; /* --> dupm. */
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case 2044: /* fmov */
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case 1263: /* mov */
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case 1368: /* dup */
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value = 1368; /* --> dup. */
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break;
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case 2038: /* eon */
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case 1370: /* eor */
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value = 1370; /* --> eor. */
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case 1262: /* mov */
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case 1369: /* dupm */
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value = 1369; /* --> dupm. */
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break;
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case 1271: /* not */
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case 1372: /* eor */
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value = 1372; /* --> eor. */
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case 2039: /* eon */
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case 1371: /* eor */
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value = 1371; /* --> eor. */
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break;
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case 1272: /* nots */
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case 1373: /* eors */
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value = 1373; /* --> eors. */
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case 1272: /* not */
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case 1373: /* eor */
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value = 1373; /* --> eor. */
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break;
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case 2039: /* facle */
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case 1378: /* facge */
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value = 1378; /* --> facge. */
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case 1273: /* nots */
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case 1374: /* eors */
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value = 1374; /* --> eors. */
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break;
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case 2040: /* faclt */
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case 1379: /* facgt */
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value = 1379; /* --> facgt. */
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case 2040: /* facle */
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case 1379: /* facge */
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value = 1379; /* --> facge. */
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break;
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case 2041: /* fcmle */
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case 1392: /* fcmge */
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value = 1392; /* --> fcmge. */
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case 2041: /* faclt */
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case 1380: /* facgt */
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value = 1380; /* --> facgt. */
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break;
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case 2042: /* fcmlt */
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case 1394: /* fcmgt */
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value = 1394; /* --> fcmgt. */
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case 2042: /* fcmle */
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case 1393: /* fcmge */
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value = 1393; /* --> fcmge. */
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break;
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case 2043: /* fcmlt */
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case 1395: /* fcmgt */
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value = 1395; /* --> fcmgt. */
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break;
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case 1256: /* fmov */
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case 1401: /* fcpy */
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value = 1401; /* --> fcpy. */
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break;
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case 1255: /* fmov */
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case 1400: /* fcpy */
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value = 1400; /* --> fcpy. */
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case 1424: /* fdup */
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value = 1424; /* --> fdup. */
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break;
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case 1254: /* fmov */
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case 1423: /* fdup */
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value = 1423; /* --> fdup. */
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break;
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case 1256: /* mov */
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case 1754: /* orr */
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value = 1754; /* --> orr. */
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break;
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case 2045: /* orn */
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case 1257: /* mov */
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case 1755: /* orr */
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value = 1755; /* --> orr. */
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break;
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case 1259: /* mov */
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case 1757: /* orr */
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value = 1757; /* --> orr. */
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case 2046: /* orn */
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case 1756: /* orr */
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value = 1756; /* --> orr. */
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break;
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case 1269: /* movs */
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case 1758: /* orrs */
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value = 1758; /* --> orrs. */
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case 1260: /* mov */
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case 1758: /* orr */
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value = 1758; /* --> orr. */
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break;
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case 1264: /* mov */
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case 1820: /* sel */
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value = 1820; /* --> sel. */
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case 1270: /* movs */
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case 1759: /* orrs */
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value = 1759; /* --> orrs. */
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break;
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case 1267: /* mov */
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case 1265: /* mov */
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case 1821: /* sel */
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value = 1821; /* --> sel. */
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break;
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case 1268: /* mov */
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case 1822: /* sel */
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value = 1822; /* --> sel. */
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break;
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default: return NULL;
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}
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File diff suppressed because it is too large
Load Diff
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@ -309,17 +309,17 @@ static const unsigned op_enum_table [] =
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391,
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413,
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415,
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1259,
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1264,
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1257,
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1256,
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1260,
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1267,
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1269,
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1265,
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1258,
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1257,
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1261,
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1268,
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1270,
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1266,
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1272,
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1271,
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1267,
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1273,
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1272,
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131,
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};
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@ -2332,16 +2332,12 @@ static const aarch64_feature_set aarch64_feature_lor =
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AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
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static const aarch64_feature_set aarch64_feature_rdma =
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AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
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static const aarch64_feature_set aarch64_feature_ras =
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AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
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static const aarch64_feature_set aarch64_feature_v8_2 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
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static const aarch64_feature_set aarch64_feature_fp_f16 =
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AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
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static const aarch64_feature_set aarch64_feature_simd_f16 =
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AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
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static const aarch64_feature_set aarch64_feature_stat_profile =
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AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
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static const aarch64_feature_set aarch64_feature_sve =
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AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0);
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static const aarch64_feature_set aarch64_feature_v8_3 =
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@ -2379,8 +2375,6 @@ static const aarch64_feature_set aarch64_feature_sb =
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AARCH64_FEATURE (AARCH64_FEATURE_SB, 0);
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static const aarch64_feature_set aarch64_feature_predres =
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AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
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static const aarch64_feature_set aarch64_feature_bti =
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AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
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static const aarch64_feature_set aarch64_feature_memtag =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
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static const aarch64_feature_set aarch64_feature_bfloat16 =
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||||
|
|
@ -2423,8 +2417,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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|||
#define RDMA &aarch64_feature_rdma
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||||
#define FP_F16 &aarch64_feature_fp_f16
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||||
#define SIMD_F16 &aarch64_feature_simd_f16
|
||||
#define RAS &aarch64_feature_ras
|
||||
#define STAT_PROFILE &aarch64_feature_stat_profile
|
||||
#define ARMV8_2 &aarch64_feature_v8_2
|
||||
#define SVE &aarch64_feature_sve
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||||
#define ARMV8_3 &aarch64_feature_v8_3
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||||
|
|
@ -2443,7 +2435,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
|
|||
#define FRINTTS &aarch64_feature_frintts
|
||||
#define SB &aarch64_feature_sb
|
||||
#define PREDRES &aarch64_feature_predres
|
||||
#define BTI &aarch64_feature_bti
|
||||
#define MEMTAG &aarch64_feature_memtag
|
||||
#define TME &aarch64_feature_tme
|
||||
#define SVE2 &aarch64_feature_sve2
|
||||
|
|
@ -2518,8 +2509,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
|
|||
{ NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
|
||||
|
|
@ -3838,19 +3827,20 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
|
||||
CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
BTI_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
|
||||
CORE_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, 0, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
|
||||
CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
{"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, 0, 0, NULL},
|
||||
{"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, 0, 0, NULL},
|
||||
CORE_INSN ("dgh", 0xd50320df, 0xffffffff, ic_system, 0, OP0 (), {}, 0),
|
||||
CORE_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
|
||||
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
|
||||
CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
|
||||
CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
|
|
@ -3877,14 +3867,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
|
||||
CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
|
||||
CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
|
||||
V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
V8_3_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
/* Test & branch (immediate). */
|
||||
CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
|
||||
CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
|
||||
|
|
@ -5069,9 +5059,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
|
||||
V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
|
||||
|
||||
/* V8.6 instructions */
|
||||
V8_6_INSN("dgh", 0xd50320df, 0xffffffff, aarch64_misc, OP0 (), {}, 0),
|
||||
|
||||
/* Matrix Multiply instructions. */
|
||||
INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
|
||||
INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
|
||||
|
|
|
|||
Loading…
Reference in New Issue