Initial check-in of the MIPS simulator. Work still needs to be done on

the run-time support code (interp.c) to provide better tracing, and
also to add profiling and architecture specific support. At the moment
the simulator has a fixed size, fixed address memory area, and
simulates a subset of the IDT monitor calls (enough to execute test
programs).

The other major feature (could even be a bug) is that the simulator
makes use of the GCC "long long" extension. Work has been started to
make this a build configuration option... but there is still a lot of
this to be done.

sim/mips/README.Cygnus

@@ -0,0 +1,38 @@
+> README.Cygnus
+-------------------------------------------------------------------------------
+
+The following are the main reasons for constructing the simulator as a
+generator:
+
+1) Avoid large fixed decode source file, with lots of #ifs controlling
+   the compilation. i.e. keep the source cleaner, smaller and easier
+   to parse.
+
+2) Allow optimum code to be created, without run-time checks on
+   instruction types. Ensure that the simulator engine only includes
+   code for the architecture being targetted. e.g. This avoids
+   run-time checks on ISA conformance, aswell as increasing
+   throughput.
+
+3) Allow updates to the instruction sets to be added quickly. Having a
+   table means that the information is together, and is easier to
+   manipulate. Having the table generate the engine, rather than the
+   run-time parse the table gives higher performance at simulation
+   time.
+
+4) Keep all the similar simulation code together. i.e. have a single
+   place where, for example, the addition code is held. This ensures that
+   updates to the simulation are not spread over a large flat source
+   file maintained by the developer.
+
+-------------------------------------------------------------------------------
+
+To keep the simulator simple (and to avoid the slight chance of
+mis-matched files) the manifests describing an engine, and the
+simulator engine itself, are held in the same source file.
+
+This means that the engine must be included twice, with the first pass
+controlled by the SIM_MANIFESTS definition.
+
+-------------------------------------------------------------------------------
+> EOF README.Cygnus

sim/mips/configure.in

@@ -0,0 +1,27 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.3)dnl
+AC_INIT(Makefile.in)
+
+AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../..)
+AC_CANONICAL_SYSTEM
+AC_ARG_PROGRAM
+
+. ${srcdir}/../../bfd/configure.host
+
+AC_PROG_CC
+AC_SUBST(CFLAGS)
+AC_SUBST(HDEFINES)
+AR=${AR-ar}
+AC_SUBST(AR)
+AC_PROG_RANLIB
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+AC_C_CROSS
+if test "x$cross_compiling" = "xno"; then
+  CC_FOR_BUILD='$(CC)'
+else
+  CC_FOR_BUILD=gcc
+fi
+AC_SUBST(CC_FOR_BUILD)
+
+AC_OUTPUT(Makefile)

sim/mips/support.h

@@ -0,0 +1,73 @@
+/*> support.h <*/
+
+#ifndef __support_h
+#define __support_h
+
+/* For 64bit values either use the GCC "long long" feature, or have a
+   structure made from two 32bit values. We can then have macros for
+   accessing the LO and HI parts of the value. Also we can provide
+   macros for the basic operations we want to perform on 64bit values
+   (i.e. ADD64,SUB64,SHIFTLEFT64, etc.). This means we should be able
+   to host the simulator on non-GCC compilers, and 32bit only
+   architectures if desired. */
+
+/* Control via a build boolean for the moment */
+#if 1 && defined(__GNUC__)
+
+typedef long long word64;
+typedef unsigned long long uword64;
+
+#define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
+#define WORD64HI(t)     (unsigned int)((t)>>32)
+
+/* Sign-extend the given value (e) as a value (b) bits long. We cannot
+   assume the HI32bits of the operand are zero, so we must perform a
+   mask to ensure we can use the simple subtraction to sign-extend. */
+#define SIGNEXTEND(e,b) (((e) & ((unsigned long long)1 << ((b) - 1))) ? (((e) & (((unsigned long long)1 << (b)) - 1)) - ((unsigned long long)1 << (b))) : (e))
+
+/* Check if a value will fit within a word (unsigned int): */
+#define NOTWORDVALUE(v) ((((((unsigned long long)(v)>>32) == 0) && !((v) & ((unsigned)1 << 31))) || ((((unsigned long long)(v)>>32) == 0xFFFFFFFF) && ((v) & ((unsigned)1 << 31)))) ? (1 == 0) : (1 == 1))
+
+/* Check if a value will fit within a halfword: */
+#define NOTHALFWORDVALUE(v) ((((((unsigned long long)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((unsigned long long)(v)>>32) == 0xFFFFFFFF) && ((((unsigned long long)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
+
+/* The following should be executed once at the start of day in the
+   main emulator control function. The simulator assumes char is
+   8bits, and from this: */
+#define CHECKSIM() {\
+                     if (sizeof(int) != (4 * sizeof(char)))\
+                      SignalException(SimulatorFault,"sizeof(int) != 4");\
+                     if (sizeof(long long) != (8 * sizeof(char)))\
+                      SignalException(SimulatorFault,"sizeof(long long) != 8");\
+                   }
+
+#else /* non-GCC build */
+
+#error "non-GCC build to be completed" /* avoid using long long */
+
+typedef struct word64 {
+ unsigned int lo;
+ unsigned int hi;
+} word64;
+
+#define WORD64LO(t)     (unsigned int)(t.lo)
+#define WORD64HI(t)     (unsigned int)(t.hi)
+
+/* TODO: Update these to manipulate the split structure values */
+#define SIGNEXTEND(e,b)         /* TODO */
+#define NOTWORDVALUE(v)         /* TODO */
+#define NOTHALFWORDVALUE(v)     /* TODO */
+
+/* The following should be executed once at the start of day in the
+   main emulator control function. The simulator assumes char is
+   8bits, and from this: */
+#define CHECKSIM() {\
+                     if (sizeof(int) != (4 * sizeof(char)))\
+                      SignalException(SimulatorFault,"sizeof(int) != 4");\a
+                   }
+
+#endif /* non-GCC build */
+
+#endif /* __support_h */
+
+/*> EOF support.h <*/