Refactor gdb.reverse/insn-reverse.c
Changes in v2: - Renamed arch-specific files to insn-reverse-<arch>.c. - Adjusted according to reviews. This patch prepares things for an upcoming testcase for record/replay support on x86. As is, gdb.reverse/insn-reverse.c is divided into sections guarded by a few #if blocks, and right now it only handles arm/aarch64. If we move forward with requiring more tests for record/replay on different architectures, i think this has the potential to become cluttered with a lot of differing arch-specific code in the same file. I've broken up the main file into other files with arch-specific bits (insn-reverse-<arch>.c). The main file will hold the generic pieces that will take care of calling the tests. The arch-specific c files are then included at the top of the generic c file. I've also added a generic initialize function since we need to run pre-test checks on x86 to make sure the rdrand/rdseed instructions are supported, otherwise we will run into a SIGILL. The arch-specific files will implement their own initialize function with whatever makes sense. Right now the aarch64 and arm files have an empty initialization function. Does this look reasonable? gdb/testsuite/ChangeLog: 2017-01-26 Luis Machado <lgustavo@codesourcery.com> * gdb.reverse/insn-reverse.c: Move arm and aarch64 code to their own files. (initialize): New function conditionally defined. (testcases): Move within conditional block. (main): Call initialize. * gdb.reverse/insn-reverse-aarch64.c: New file, based on aarch64 bits of gdb.reverse/insn-reverse.c. * gdb.reverse/insn-reverse-arm.c: New file, based on arm bits of gdb.reverse/insn-reverse.c.
This commit is contained in:
Luis Machado
parent
874a1c8c32
commit
8b00c17616
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@ -15,141 +15,32 @@
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#if (defined __aarch64__)
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#include <arm_neon.h>
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#endif
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#if (defined __aarch64__)
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static void
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load (void)
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{
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int buf[8];
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asm ("ld1 { v1.8b }, [%[buf]]\n"
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"ld1 { v2.8b, v3.8b }, [%[buf]]\n"
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"ld1 { v3.8b, v4.8b, v5.8b }, [%[buf]]\n"
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:
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: [buf] "r" (buf)
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: /* No clobbers */);
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}
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static void
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move (void)
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{
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float32x2_t b1_ = vdup_n_f32(123.0f);
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float32_t a1_ = 0;
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float64x1_t b2_ = vdup_n_f64(456.0f);
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float64_t a2_ = 0;
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asm ("ins %0.s[0], %w1\n"
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: "=w"(b1_)
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: "r"(a1_), "0"(b1_)
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: /* No clobbers */);
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asm ("ins %0.d[1], %x1\n"
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: "=w"(b2_)
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: "r"(a2_), "0"(b2_)
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: /* No clobbers */);
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}
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static void
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adv_simd_mod_imm (void)
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{
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float32x2_t a1 = {2.0, 4.0};
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asm ("bic %0.2s, #1\n"
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"bic %0.2s, #1, lsl #8\n"
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: "=w"(a1)
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: "0"(a1)
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: /* No clobbers */);
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}
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static void
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adv_simd_scalar_index (void)
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{
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float64x2_t b_ = {0.0, 0.0};
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float64_t a_ = 1.0;
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float64_t result;
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asm ("fmla %d0,%d1,%2.d[1]"
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: "=w"(result)
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: "w"(a_), "w"(b_)
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: /* No clobbers */);
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}
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static void
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adv_simd_smlal (void)
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{
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asm ("smlal v13.2d, v8.2s, v0.2s");
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}
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static void
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adv_simd_vect_shift (void)
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{
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asm ("fcvtzs s0, s0, #1");
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}
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#elif (defined __arm__)
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static void
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ext_reg_load (void)
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{
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char in[8];
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asm ("vldr d0, [%0]" : : "r" (in));
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asm ("vldr s3, [%0]" : : "r" (in));
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asm ("vldm %0, {d3-d4}" : : "r" (in));
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asm ("vldm %0, {s9-s11}" : : "r" (in));
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}
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static void
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ext_reg_mov (void)
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{
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int i, j;
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double d;
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i = 1;
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j = 2;
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asm ("vmov s4, s5, %0, %1" : "=r" (i), "=r" (j): );
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asm ("vmov s7, s8, %0, %1" : "=r" (i), "=r" (j): );
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asm ("vmov %0, %1, s10, s11" : : "r" (i), "r" (j));
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asm ("vmov %0, %1, s1, s2" : : "r" (i), "r" (j));
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asm ("vmov %P2, %0, %1" : "=r" (i), "=r" (j): "w" (d));
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asm ("vmov %1, %2, %P0" : "=w" (d) : "r" (i), "r" (j));
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}
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static void
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ext_reg_push_pop (void)
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{
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double d;
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asm ("vpush {%P0}" : : "w" (d));
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asm ("vpop {%P0}" : : "w" (d));
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}
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#endif
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typedef void (*testcase_ftype) (void);
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/* Functions testing instruction decodings. GDB will read n_testcases
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to know how many functions to test. */
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/* The arch-specific files need to implement both the initialize function
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and define the testcases array. */
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static testcase_ftype testcases[] =
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{
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#if (defined __aarch64__)
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load,
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move,
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adv_simd_mod_imm,
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adv_simd_scalar_index,
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adv_simd_smlal,
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adv_simd_vect_shift,
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#include "insn-reverse-aarch64.c"
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#elif (defined __arm__)
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ext_reg_load,
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ext_reg_mov,
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ext_reg_push_pop,
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#endif
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};
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#include "insn-reverse-arm.c"
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#else
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/* We get here if the current architecture being tested doesn't have any
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record/replay instruction decoding tests implemented. */
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static testcase_ftype testcases[] = {};
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/* Dummy implementation in case this target doesn't have any record/replay
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instruction decoding tests implemented. */
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static void
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initialize (void)
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{
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}
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#endif
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/* GDB will read n_testcases to know how many functions to test. The
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functions are implemented in arch-specific files and the testcases
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array is defined together with them. */
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static int n_testcases = (sizeof (testcases) / sizeof (testcase_ftype));
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int
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@ -157,6 +48,9 @@ main ()
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{
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int i = 0;
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/* Initialize any required arch-specific bits. */
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initialize ();
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for (i = 0; i < n_testcases; i++)
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testcases[i] ();
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