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Simulate XScale BCUMOD register

This commit is contained in:
Nick Clifton 2002-05-21 20:28:26 +00:00
parent fa70f2ed23
commit 8b2440b731
2 changed files with 15 additions and 3 deletions
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6
sim/arm/ChangeLog
View File

@ -1,3 +1,9 @@
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* armcopro.c (check_cp13_access): Allow access to register 1 when
CRm is 1.
(write_cp13_reg): Allow bit 0 of reg 1 of CRm 1 to be written to.
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* Makefile.in (SWI_TARGET_SWITCHES): Define.

12
sim/arm/armcopro.c
View File

@ -587,7 +587,7 @@ check_cp13_access (ARMul_State * state,
unsigned opcode_1,
unsigned opcode_2)
{
/* Do not allow access to these register in USER mode. */
/* Do not allow access to these registers in USER mode. */
if (state->Mode == USER26MODE || state->Mode == USER32MODE)
return ARMul_CANT;
@ -601,7 +601,7 @@ check_cp13_access (ARMul_State * state,
return ARMul_CANT;
/* Registers 0, 4 and 8 are defined when CRm == 0.
Registers 0, 4, 5, 6, 7, 8 are defined when CRm == 1.
Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
For all other CRm values undefined behaviour results. */
if (CRm == 0)
{
@ -610,7 +610,7 @@ check_cp13_access (ARMul_State * state,
}
else if (CRm == 1)
{
if (reg == 0 || (reg >= 4 && reg <= 8))
if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
return ARMul_DONE;
}
@ -659,6 +659,12 @@ write_cp13_reg (unsigned reg, unsigned CRm, ARMword value)
value |= XScale_cp13_CR1_Regs[0] & (1UL << 31);
break;
case 1: /* BCUMOD */
/* Only bit 0 is accecssible. */
value &= 1;
value |= XScale_cp13_CR1_Regs[1] & ~ 1;
break;
case 4: /* ELOG0 */
case 5: /* ELOG1 */
case 6: /* ECAR0 */