* genmloop.sh (eng.hin): Rename HAVE_PARALLEL_EXEC to
HAVE_PARALLEL_INSNS, define as 0 or 1. Emit decls of fns in mloop.cin. * cgen-engine.h: Typedefs of IADDR,CIA,SEM_ARG,SEM_PC moved ... * cgen-sim.h: ... to here.
This commit is contained in:
Doug Evans
parent
7192be38cc
commit
8c7dc9ffc8
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@ -1,3 +1,10 @@
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Wed Nov 4 23:51:19 1998 Doug Evans <devans@seba.cygnus.com>
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* genmloop.sh (eng.hin): Rename HAVE_PARALLEL_EXEC to
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HAVE_PARALLEL_INSNS, define as 0 or 1. Emit decls of fns in mloop.cin.
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* cgen-engine.h: Typedefs of IADDR,CIA,SEM_ARG,SEM_PC moved ...
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* cgen-sim.h: ... to here.
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Wed Oct 28 12:00:57 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* aclocal.m4 (enable-build-warnings): Replace
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@ -18,46 +18,11 @@ You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* This file must be included after eng.h has been included
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as it specifies the configuration of the engine. */
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/* This file must be included after eng.h and ${cpu}.h have been included. */
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#ifndef CGEN_ENGINE_H
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#define CGEN_ENGINE_H
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/* Execution support. */
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#if WITH_SCACHE
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/* instruction address
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??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB
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case. The first element is the PCADDR, the second element is the SCACHE *.
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Haven't found the time yet to make this work, but it is a nicer approach
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than the current br_cache stuff. */
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typedef PCADDR IADDR;
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/* current instruction address */
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typedef PCADDR CIA;
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/* argument to semantic functions */
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typedef SCACHE *SEM_ARG;
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/* semantic code's version of pc */
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#if WITH_SCACHE_PBB
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typedef SCACHE *SEM_PC;
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#else
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typedef PCADDR SEM_PC;
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#endif
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#else /* ! WITH_SCACHE */
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/* instruction address */
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typedef PCADDR IADDR;
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/* current instruction address */
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typedef PCADDR CIA;
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/* argument to semantic functions */
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typedef ARGBUF *SEM_ARG;
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/* semantic code's version of pc */
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typedef PCADDR SEM_PC;
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#endif /* ! WITH_SCACHE */
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/* Semantic functions come in six versions on two axes:
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fast/full-featured, and using one of the simple/scache/compilation engines.
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A full featured simulator is always provided. --enable-sim-fast includes
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@ -69,7 +34,7 @@ typedef PCADDR SEM_PC;
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/* Types of the machine generated extract and semantic fns. */
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typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
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#ifdef HAVE_PARALLEL_EXEC
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#if HAVE_PARALLEL_INSNS
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typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *);
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#else
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typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG);
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@ -136,8 +101,6 @@ do { \
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((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->opcode)) \
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& CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
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!= 0)
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/* Engine support. */
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/* These are used so that we can compile two copies of the semantic code,
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one with full feature support and one without that runs fast(er). */
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@ -21,8 +21,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#ifndef CGEN_SIM_H
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#define CGEN_SIM_H
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#define PC CPU (h_pc)
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/* Instruction field support macros. */
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#define EXTRACT_SIGNED(val, total, start, length) \
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@ -37,24 +35,54 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#define HOST_LONGS_FOR_BITS(n) \
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(((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
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/* Execution support. */
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/* Forward decls. Defined in the machine generated files. */
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/* This holds the contents of the extracted insn.
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There are a few common entries (e.g. pc address), and then one big
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union with an entry for each of the instruction formats. */
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typedef struct argbuf ARGBUF;
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/* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support.
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At present there is nothing else, but it also provides a level of
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abstraction. */
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typedef struct scache SCACHE;
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/* This is a union with one entry for each instruction format.
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Each entry contains all of the non-constant inputs of the instruction. */
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typedef struct parexec PAREXEC;
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/* An "Instruction DESCriptor".
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This is the main handle on an instruction for the simulator. */
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typedef struct idesc IDESC;
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/* Engine support.
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??? This is here because it's needed before eng.h (built by genmloop.sh)
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which is needed before cgen-engine.h and cpu.h.
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??? This depends on a cpu family specific type, PCADDR, but no machine
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generated headers will have been included yet. sim/common currently
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requires the typedef of sim_cia in sim-main.h between the inclusion of
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sim-basics.h and sim-base.h so this is no different. */
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#ifdef SCACHE_P
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#if WITH_SCACHE
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/* instruction address */
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/* instruction address
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??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB
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case. The first element is the PCADDR, the second element is the SCACHE *.
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Haven't found the time yet to make this work, but it is a nicer approach
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than the current br_cache stuff. */
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typedef PCADDR IADDR;
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/* current instruction address */
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typedef PCADDR CIA;
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/* argument to semantic functions */
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typedef SCACHE *SEM_ARG;
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/* semantic code's version of pc */
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#if WITH_SCACHE_PBB
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typedef SCACHE *SEM_PC;
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#else
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typedef PCADDR SEM_PC;
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#endif
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#else /* ! SCACHE_P */
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#else /* ! WITH_SCACHE */
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/* instruction address */
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typedef PCADDR IADDR;
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@ -62,148 +90,34 @@ typedef PCADDR IADDR;
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typedef PCADDR CIA;
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/* argument to semantic functions */
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typedef ARGBUF *SEM_ARG;
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/* semantic code's version of pc */
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typedef PCADDR SEM_PC;
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#endif /* ! SCACHE_P */
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/* Semantic functions come in two versions on two axes:
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fast and full (featured), and using or not using scache.
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A full featured simulator is always provided. --enable-sim-fast includes
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support for fast execution by duplicating the semantic code but leaving
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out all features like tracing and profiling.
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Using the scache is selected with --enable-sim-scache. */
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/* FIXME: --enable-sim-fast not implemented yet. */
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/* Types of the machine generated extract and semantic fns. */
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/* FIXME: Eventually conditionalize EXTRACT_FN on WITH_SCACHE. */
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typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
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#if WITH_SCACHE
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#ifdef HAVE_PARALLEL_EXEC
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, SCACHE *, PAREXEC *);
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#else
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, SCACHE *);
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#endif
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#else /* ! WITH_SCACHE */
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#ifdef HAVE_PARALLEL_EXEC
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *, PAREXEC *);
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#else
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
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#endif
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#endif
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/* Scache data for each cpu. */
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typedef struct cpu_scache {
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/* Simulator cache size. */
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int size;
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#define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size)
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/* Cache. */
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SCACHE *cache;
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#define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache)
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#if 0 /* FIXME: wip */
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/* Free list. */
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SCACHE *free;
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#define CPU_SCACHE_FREE(cpu) ((cpu) -> cgen_cpu.scache.free)
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/* Hash table. */
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SCACHE **hash_table;
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#define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table)
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#endif
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#if WITH_PROFILE_SCACHE_P
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/* Cache hits, misses. */
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unsigned long hits, misses;
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#define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits)
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#define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses)
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#endif
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} CPU_SCACHE;
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/* Default number of cached blocks. */
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#ifdef CONFIG_SIM_CACHE_SIZE
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#define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
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#else
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#define SCACHE_DEFAULT_CACHE_SIZE 1024
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#endif
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/* Hash a PC value. */
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/* FIXME: cpu specific */
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#define SCACHE_HASH_PC(state, pc) \
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(((pc) >> 1) & (STATE_SCACHE_SIZE (sd) - 1))
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/* Non-zero if cache is in use. */
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#define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0)
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/* Install the simulator cache into the simulator. */
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MODULE_INSTALL_FN scache_install;
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/* Flush all cpu's caches. */
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void scache_flush (SIM_DESC);
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#endif /* ! WITH_SCACHE */
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/* Scache profiling support. */
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/* Additional opcode table support. */
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/* Print summary scache usage information. */
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void scache_print_profile (SIM_CPU *cpu, int verbose);
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/* Opcode table for virtual insns (only used by the simulator). */
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extern const struct cgen_insn cgen_virtual_opcode_table[];
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#if WITH_PROFILE_SCACHE_P
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#define PROFILE_COUNT_SCACHE_HIT(cpu) \
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do { \
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if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
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++ CPU_SCACHE_HITS (cpu); \
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} while (0)
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#define PROFILE_COUNT_SCACHE_MISS(cpu) \
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do { \
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if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
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++ CPU_SCACHE_MISSES (cpu); \
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} while (0)
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#else
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#define PROFILE_COUNT_SCACHE_HIT(cpu)
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#define PROFILE_COUNT_SCACHE_MISS(cpu)
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#endif
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/* -ve of indices of virtual insns in cgen_virtual_opcode_table. */
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typedef enum {
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VIRTUAL_INSN_X_INVALID = 0,
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VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2,
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VIRTUAL_INSN_X_BEGIN = -3,
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VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5
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} CGEN_INSN_VIRTUAL_TYPE;
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/* Return non-zero if OPCODE is a virtual insn. */
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#define CGEN_INSN_VIRTUAL_P(opcode) \
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CGEN_INSN_ATTR ((opcode), CGEN_INSN_VIRTUAL)
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/* Engine support. */
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/* Values to denote parallel/sequential execution. */
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#define EXEC_SEQUENCE 0
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#define EXEC_PARALLEL 1
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/* These are used so that we can compile two copies of the semantic code,
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one with full feature support and one without. */
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/* FIXME: Eventually delete extraction if not using scache. */
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#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
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#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
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#ifdef SCACHE_P
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#define CIA_ADDR(cia) (cia)
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/* semantics.c support */
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#define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf)
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#define SEM_INSN(sem_arg) shouldnt_be_used
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#define SEM_NEXT_PC(sc, len) ((sc) -> next)
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#define SEM_BRANCH_VIA_CACHE(sc, newval) (newval)
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#define SEM_BRANCH_VIA_ADDR(sc, newval) (newval)
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/* Return address a branch insn will branch to.
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This is only used during tracing. */
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#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
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#else /* ! SCACHE_P */
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#define CIA_ADDR(cia) (cia)
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/* semantics.c support */
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#define SEM_ARGBUF(sem_arg) (sem_arg)
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#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
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/* FIXME:wip */
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#define SEM_NEXT_PC(abuf, len) (abuf -> addr + abuf -> length)
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#define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval)
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#define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval)
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#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
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#endif /* ! SCACHE_P */
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/* GNU C's "computed goto" facility is used to speed things up where
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possible. These macros provide a portable way to use them.
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Nesting of these switch statements is done by providing an extra argument
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that distinguishes them. `N' can be a number or symbol.
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Variable `labels_##N' must be initialized with the labels of each case. */
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#ifdef __GNUC__
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#define SWITCH(N, X) goto *X;
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#define CASE(N, X) case_##N##_##X
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@ -217,11 +131,6 @@ do { \
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#define DEFAULT(N) default
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#define ENDSWITCH(N)
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#endif
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/* Engine control (FIXME). */
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int engine_stop (SIM_DESC);
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void engine_run (SIM_DESC, int, int);
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/*void engine_resume (SIM_DESC, int, int);*/
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/* Simulator state. */
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@ -246,50 +155,30 @@ typedef struct cgen_state {
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/* Non-zero if no tracing or profiling is selected. */
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int run_fast_p;
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#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
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/* Opcode table. */
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CGEN_OPCODE_DESC opcode_table;
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#define STATE_OPCODE_TABLE(sd) ((sd) -> cgen_state.opcode_table)
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} CGEN_STATE;
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/* Additional non-machine generated per-cpu data to go in SIM_CPU.
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The member's name must be `cgen_cpu'. */
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typedef struct {
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/* Simulator's execution cache.
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Allocate space for this even if not used as some simulators may have
|
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one machine variant that uses the scache and another that doesn't and
|
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we don't want members in this struct to move about. */
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CPU_SCACHE scache;
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/* Instruction descriptor table. */
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IDESC *idesc;
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#define CPU_IDESC(cpu) ((cpu)->cgen_cpu.idesc)
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/* Whether the read,semantic entries have been initialized or not.
|
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These are computed goto labels. */
|
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int idesc_read_init_p;
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#define CPU_IDESC_READ_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_read_init_p)
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int idesc_sem_init_p;
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#define CPU_IDESC_SEM_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_sem_init_p)
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/* Function to fetch the opcode table entry in the IDESC. */
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const CGEN_INSN * (*opcode) (SIM_CPU *, int);
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#define CPU_OPCODE(cpu) ((cpu)->cgen_cpu.opcode)
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/* Return name of instruction numbered INUM. */
|
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#define INSN_NAME(cpu, inum) CGEN_INSN_NAME ((* CPU_OPCODE (cpu)) ((cpu), (inum)))
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|
||||
/* Allow slop in size calcs for case where multiple cpu types are supported
|
||||
and space for the specified cpu is malloc'd at run time. */
|
||||
double slop;
|
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} CGEN_CPU;
|
||||
|
||||
/* Various utilities. */
|
||||
|
||||
/* Called after sim_post_argv_init to do any cgen initialization. */
|
||||
extern void cgen_init (SIM_DESC);
|
||||
|
||||
/* Return the name of an insn. */
|
||||
extern CPU_INSN_NAME_FN cgen_insn_name;
|
||||
|
||||
/* Return the maximum number of extra bytes required for a sim_cpu struct. */
|
||||
/* ??? Ok, yes, this is less pretty than it should be. Give me a better
|
||||
language [or suggest a better way]. */
|
||||
extern int cgen_cpu_max_extra_bytes (void);
|
||||
|
||||
extern void
|
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sim_disassemble_insn (SIM_CPU *, const CGEN_INSN *,
|
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const struct argbuf *, PCADDR, char *);
|
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|
||||
/* Called to process an invalid instruction. */
|
||||
extern void sim_engine_invalid_insn (SIM_CPU *, PCADDR);
|
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|
||||
#endif /* CGEN_SIM_H */
|
||||
|
|
|
|||
|
|
@ -75,6 +75,10 @@
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|||
# -parallel: cpu can execute multiple instructions parallely
|
||||
#
|
||||
# This option is specified in addition to -simple, -scache, -pbb.
|
||||
# Note that while the code can determine if the cpu supports parallel
|
||||
# execution with HAVE_PARALLEL_INSNS [and thus this option is
|
||||
# technically unnecessary], having this option cuts down on the clutter
|
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# in the result.
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#
|
||||
# -switch file: specify file containing semantics implemented as a switch()
|
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#
|
||||
|
|
@ -171,11 +175,11 @@ else
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|||
fi
|
||||
|
||||
echo ""
|
||||
echo "/* HAVE_PARALLEL_EXEC: defined if cpu can parallelly execute > 1 insn. */"
|
||||
echo "/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */"
|
||||
if [ x$parallel = xyes ] ; then
|
||||
echo "#define HAVE_PARALLEL_EXEC"
|
||||
echo "#define HAVE_PARALLEL_INSNS 1"
|
||||
else
|
||||
echo "#undef HAVE_PARALLEL_EXEC"
|
||||
echo "#define HAVE_PARALLEL_INSNS 0"
|
||||
fi
|
||||
|
||||
if [ "x$switch" != x ] ; then
|
||||
|
|
@ -197,6 +201,21 @@ if [ "x$switch" != x ] ; then
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|||
fi
|
||||
fi
|
||||
|
||||
# Decls of functions we define.
|
||||
|
||||
echo ""
|
||||
echo "/* Functions defined in the generated mainloop.c file"
|
||||
echo " (which doesn't necessarily have that file name). */"
|
||||
echo ""
|
||||
echo "extern ENGINE_FN ${cpu}_engine_run_full;"
|
||||
echo "extern ENGINE_FN ${cpu}_engine_run_fast;"
|
||||
echo ""
|
||||
echo "extern SEM_PC ${cpu}_pbb_begin (SIM_CPU *, int);"
|
||||
echo "extern SEM_PC ${cpu}_pbb_chain (SIM_CPU *, SEM_ARG);"
|
||||
echo "extern SEM_PC ${cpu}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_PC *, PCADDR);"
|
||||
echo "extern void ${cpu}_pbb_before (SIM_CPU *, SCACHE *);"
|
||||
echo "extern void ${cpu}_pbb_after (SIM_CPU *, SCACHE *);"
|
||||
|
||||
##########################################################################
|
||||
|
||||
rm -f tmp-mloop.cin mloop.cin
|
||||
|
|
|
|||
Loading…
Reference in New Issue