/bfd:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* archures.c: Add AVR XMEGA architecture information.
* cpu-avr.c (arch_info_struct): Likewise.
* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
(elf32_avr_object_p): Likewise.
/gas:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
(AVR_INSN): Change definition to match.
(avr_opcodes): Likewise, change to match.
(mcu_types): Add XMEGA architecture names and new XMEGA device names.
(md_show_usage): Add XMEGA architecture names.
(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
Add support for SPM Z+ instruction.
* doc/c-avr.texi: Add documentation for XMEGA architectures and
devices.
/include/opcode:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
New instruction set flags.
(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
/ld:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
(eavrxmega?.c): Likewise.
* configure.tgt (targ_extra_emuls): Likewise.
* emulparams/avrxmega1.sh: New file.
* emulparams/avrxmega2.sh: Likewise.
* emulparams/avrxmega3.sh: Likewise.
* emulparams/avrxmega4.sh: Likewise.
* emulparams/avrxmega5.sh: Likewise.
* emulparams/avrxmega6.sh: Likewise.
* emulparams/avrxmega7.sh: Likewise.
* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
Add avrxmega6, avrxmega7 to list of architectures for no stubs.
/opcodes:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
post-increment to support LPM Z+ instruction. Add support for 'E'
constraint for DES instruction.
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
This commit is contained in:
Eric B. Weddington
parent
3167638f1e
commit
8cc66334fa
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@ -1,3 +1,10 @@
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2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
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* archures.c: Add AVR XMEGA architecture information.
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* cpu-avr.c (arch_info_struct): Likewise.
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* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
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(elf32_avr_object_p): Likewise.
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2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
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* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
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@ -376,6 +376,13 @@ DESCRIPTION
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.#define bfd_mach_avr5 5
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.#define bfd_mach_avr51 51
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.#define bfd_mach_avr6 6
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.#define bfd_mach_avrxmega1 101
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.#define bfd_mach_avrxmega2 102
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.#define bfd_mach_avrxmega3 103
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.#define bfd_mach_avrxmega4 104
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.#define bfd_mach_avrxmega5 105
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.#define bfd_mach_avrxmega6 106
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.#define bfd_mach_avrxmega7 107
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. bfd_arch_bfin, {* ADI Blackfin *}
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.#define bfd_mach_bfin 1
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. bfd_arch_cr16, {* National Semiconductor CompactRISC (ie CR16). *}
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@ -133,7 +133,29 @@ static const bfd_arch_info_type arch_info_struct[] =
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N (22, bfd_mach_avr51, "avr:51", FALSE, & arch_info_struct[9]),
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/* 3-Byte PC. */
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N (22, bfd_mach_avr6, "avr:6", FALSE, NULL)
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N (22, bfd_mach_avr6, "avr:6", FALSE, & arch_info_struct[10]),
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/* Xmega 1 */
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N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[11]),
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/* Xmega 2 */
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N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[12]),
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/* Xmega 3 */
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N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[13]),
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/* Xmega 4 */
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N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[14]),
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/* Xmega 5 */
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N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[15]),
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/* Xmega 6 */
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N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[16]),
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/* Xmega 7 */
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N (24, bfd_mach_avrxmega7, "avr:107", FALSE, NULL)
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};
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const bfd_arch_info_type bfd_avr_arch =
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@ -1298,6 +1298,34 @@ bfd_elf_avr_final_write_processing (bfd *abfd,
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case bfd_mach_avr6:
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val = E_AVR_MACH_AVR6;
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break;
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case bfd_mach_avrxmega1:
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val = E_AVR_MACH_XMEGA1;
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break;
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case bfd_mach_avrxmega2:
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val = E_AVR_MACH_XMEGA2;
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break;
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case bfd_mach_avrxmega3:
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val = E_AVR_MACH_XMEGA3;
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break;
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case bfd_mach_avrxmega4:
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val = E_AVR_MACH_XMEGA4;
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break;
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case bfd_mach_avrxmega5:
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val = E_AVR_MACH_XMEGA5;
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break;
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case bfd_mach_avrxmega6:
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val = E_AVR_MACH_XMEGA6;
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break;
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case bfd_mach_avrxmega7:
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val = E_AVR_MACH_XMEGA7;
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break;
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}
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elf_elfheader (abfd)->e_machine = EM_AVR;
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@ -1360,6 +1388,34 @@ elf32_avr_object_p (bfd *abfd)
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case E_AVR_MACH_AVR6:
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e_set = bfd_mach_avr6;
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break;
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case E_AVR_MACH_XMEGA1:
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e_set = bfd_mach_avrxmega1;
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break;
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case E_AVR_MACH_XMEGA2:
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e_set = bfd_mach_avrxmega2;
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break;
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case E_AVR_MACH_XMEGA3:
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e_set = bfd_mach_avrxmega3;
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break;
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case E_AVR_MACH_XMEGA4:
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e_set = bfd_mach_avrxmega4;
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break;
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case E_AVR_MACH_XMEGA5:
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e_set = bfd_mach_avrxmega5;
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break;
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case E_AVR_MACH_XMEGA6:
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e_set = bfd_mach_avrxmega6;
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break;
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case E_AVR_MACH_XMEGA7:
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e_set = bfd_mach_avrxmega7;
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break;
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}
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}
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return bfd_default_set_arch_mach (abfd, bfd_arch_avr,
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@ -1,3 +1,15 @@
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2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
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* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
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(AVR_INSN): Change definition to match.
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(avr_opcodes): Likewise, change to match.
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(mcu_types): Add XMEGA architecture names and new XMEGA device names.
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(md_show_usage): Add XMEGA architecture names.
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(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
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Add support for SPM Z+ instruction.
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* doc/c-avr.texi: Add documentation for XMEGA architectures and
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devices.
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2011-03-21 Eric B. Weddington <eric.weddington@atmel.com>
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* config/tc-avr.c (md_show_usage): Add "Assembler" text to output.
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@ -29,18 +29,19 @@ struct avr_opcodes_s
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{
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char * name;
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char * constraints;
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char * opcode;
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int insn_size; /* In words. */
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int isa;
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unsigned int bin_opcode;
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};
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#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
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{#NAME, CONSTR, SIZE, ISA, BIN},
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{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
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struct avr_opcodes_s avr_opcodes[] =
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{
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#include "opcode/avr.h"
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{NULL, NULL, 0, 0, 0}
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{NULL, NULL, NULL, 0, 0, 0}
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};
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const char comment_chars[] = ";";
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@ -79,6 +80,13 @@ static struct mcu_type_s mcu_types[] =
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{"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
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{"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
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{"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
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{"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
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{"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
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{"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
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{"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
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{"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
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{"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
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{"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
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{"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
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{"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
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@ -237,6 +245,21 @@ static struct mcu_type_s mcu_types[] =
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{"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
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{"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
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{"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
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{"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
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{"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
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{"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
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{"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
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{"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
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{"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
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{"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
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{"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
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{"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
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{NULL, 0, 0}
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};
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@ -413,6 +436,11 @@ md_show_usage (FILE *stream)
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" avr5 - enhanced AVR core with up to 64K program memory\n"
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" avr51 - enhanced AVR core with up to 128K program memory\n"
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" avr6 - enhanced AVR core with up to 256K program memory\n"
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" avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
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" avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
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" avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
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" avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
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" avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
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" or immediate microcontroller name.\n"));
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fprintf (stream,
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_(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
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@ -840,7 +868,12 @@ avr_operand (struct avr_opcodes_s *opcode,
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if (*str == '+')
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{
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++str;
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op_mask |= 1;
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char *s;
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for (s = opcode->opcode; *s; ++s)
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{
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if (*s == '+')
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op_mask |= (1 << (15 - (s - opcode->opcode)));
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}
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}
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/* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
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@ -957,6 +990,16 @@ avr_operand (struct avr_opcodes_s *opcode,
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}
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break;
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case 'E':
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{
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unsigned int x;
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x = avr_get_constant (str, 15);
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str = input_line_pointer;
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op_mask |= (x << 4);
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}
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break;
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case '?':
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break;
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@ -85,6 +85,27 @@ atmega128rfa1, at90can128, at90usb1286, at90usb1287, m3000).
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Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types:
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atmega2560, atmega2561).
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Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program
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memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4,
|
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atxmega32d4).
|
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Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program
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memory space and greater than 64K data space (MCU types: atxmega32a4).
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Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
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memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).
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Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
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memory space and greater than 64K data space (MCU types: atxmega64a1).
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Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
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memory space and less than 64K data space (MCU types: atxmega128a3,
|
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atxmega128d3, atxmega192a3, atxmega192d3, atxmega256a3, atxmega256a3b,
|
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atxmega192d3).
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Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
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memory space and greater than 64K data space (MCU types: atxmega128a1).
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@cindex @code{-mall-opcodes} command line option, AVR
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@item -mall-opcodes
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Accept all AVR opcodes, even if not supported by @code{-mmcu}.
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|
|
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@ -40,6 +40,13 @@
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#define E_AVR_MACH_AVR5 5
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#define E_AVR_MACH_AVR51 51
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#define E_AVR_MACH_AVR6 6
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#define E_AVR_MACH_XMEGA1 101
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#define E_AVR_MACH_XMEGA2 102
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#define E_AVR_MACH_XMEGA3 103
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#define E_AVR_MACH_XMEGA4 104
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#define E_AVR_MACH_XMEGA5 105
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#define E_AVR_MACH_XMEGA6 106
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#define E_AVR_MACH_XMEGA7 107
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/* Relocations. */
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START_RELOC_NUMBERS (elf_avr_reloc_type)
|
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|
|
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|
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@ -1,3 +1,9 @@
|
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2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
|
||||
|
||||
* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
|
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New instruction set flags.
|
||||
(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
|
||||
|
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2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (M_PREF_AB): New enum value.
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@
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#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */
|
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#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */
|
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#define AVR_ISA_MOVW 0x1000 /* device has MOVW */
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#define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */
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#define AVR_ISA_DES 0x4000 /* device has DES */
|
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|
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#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
|
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#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
|
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|
|
@ -49,6 +51,8 @@
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#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
|
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#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
|
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#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
|
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#define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND)
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#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
|
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|
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#define AVR_ISA_AVR1 AVR_ISA_TINY1
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#define AVR_ISA_AVR2 AVR_ISA_2xxx
|
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|
|
@ -109,6 +113,7 @@
|
|||
L - signed pc relative offset from -2048 to 2047
|
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h - absolute code address (call, jmp)
|
||||
S - immediate value from 0 to 7 (S = s << 4)
|
||||
E - immediate value from 0 to 15, shifted left by 4 (des)
|
||||
? - use this opcode entry if no parameters, else use next opcode entry
|
||||
|
||||
Order is important - some binary opcodes have more than one name,
|
||||
|
|
@ -169,7 +174,8 @@ AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518)
|
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AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588)
|
||||
AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598)
|
||||
AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
|
||||
AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8)
|
||||
AVR_INSN (spm, "?", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8)
|
||||
AVR_INSN (spm, "z", "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8)
|
||||
|
||||
AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
|
||||
AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
|
||||
|
|
@ -283,3 +289,6 @@ AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
|
|||
AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
|
||||
AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
|
||||
|
||||
/* DES instruction for encryption and decryption */
|
||||
AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B)
|
||||
|
||||
|
|
|
|||
15
ld/ChangeLog
15
ld/ChangeLog
|
|
@ -1,3 +1,18 @@
|
|||
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
|
||||
|
||||
* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
|
||||
(eavrxmega?.c): Likewise.
|
||||
* configure.tgt (targ_extra_emuls): Likewise.
|
||||
* emulparams/avrxmega1.sh: New file.
|
||||
* emulparams/avrxmega2.sh: Likewise.
|
||||
* emulparams/avrxmega3.sh: Likewise.
|
||||
* emulparams/avrxmega4.sh: Likewise.
|
||||
* emulparams/avrxmega5.sh: Likewise.
|
||||
* emulparams/avrxmega6.sh: Likewise.
|
||||
* emulparams/avrxmega7.sh: Likewise.
|
||||
* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
|
||||
Add avrxmega6, avrxmega7 to list of architectures for no stubs.
|
||||
|
||||
2011-03-21 Eric B. Weddington <eric.weddington@atmel.com>
|
||||
|
||||
* scripttempl/avr.sc: Add fuse, lock, and signature memory regions.
|
||||
|
|
|
|||
|
|
@ -163,6 +163,13 @@ ALL_EMULATION_SOURCES = \
|
|||
eavr5.c \
|
||||
eavr51.c \
|
||||
eavr6.c \
|
||||
eavrxmega1.o \
|
||||
eavrxmega2.o \
|
||||
eavrxmega3.o \
|
||||
eavrxmega4.o \
|
||||
eavrxmega5.o \
|
||||
eavrxmega6.o \
|
||||
eavrxmega7.o \
|
||||
ecoff_i860.c \
|
||||
ecoff_sparc.c \
|
||||
ecrisaout.c \
|
||||
|
|
@ -773,6 +780,34 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(srcdir)/emultempl/avrelf.em \
|
|||
$(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avr6 "$(tdir_avr2)"
|
||||
eavrxmega1.c: $(srcdir)/emulparams/avrxmega1.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega1 "$(tdir_avr2)"
|
||||
eavrxmega2.c: $(srcdir)/emulparams/avrxmega2.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega2 "$(tdir_avr2)"
|
||||
eavrxmega3.c: $(srcdir)/emulparams/avrxmega3.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega3 "$(tdir_avr2)"
|
||||
eavrxmega4.c: $(srcdir)/emulparams/avrxmega4.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega4 "$(tdir_avr2)"
|
||||
eavrxmega5.c: $(srcdir)/emulparams/avrxmega5.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega5 "$(tdir_avr2)"
|
||||
eavrxmega6.c: $(srcdir)/emulparams/avrxmega6.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega6 "$(tdir_avr2)"
|
||||
eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \
|
||||
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
|
||||
${GEN_DEPENDS}
|
||||
${GENSCRIPTS} avrxmega7 "$(tdir_avr2)"
|
||||
ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
|
||||
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ xscale-*-coff) targ_emul=armcoff ;;
|
|||
xscale-*-elf) targ_emul=armelf
|
||||
;;
|
||||
avr-*-*) targ_emul=avr2
|
||||
targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
|
||||
targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7"
|
||||
;;
|
||||
bfin-*-elf) targ_emul=elf32bfin;
|
||||
targ_extra_emuls="elf32bfinfd"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:101
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:102
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:103
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:104
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:105
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:106
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ARCH=avr:107
|
||||
MACHINE=
|
||||
SCRIPT_NAME=avr
|
||||
OUTPUT_FORMAT="elf32-avr"
|
||||
MAXPAGESIZE=1
|
||||
EMBEDDED=yes
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
TEXT_LENGTH=1024K
|
||||
DATA_ORIGIN=0x802000
|
||||
DATA_LENGTH=0xffa0
|
||||
EXTRA_EM_FILE=avrelf
|
||||
|
|
@ -71,8 +71,10 @@ avr_elf_${EMULATION_NAME}_before_allocation (void)
|
|||
|
||||
gld${EMULATION_NAME}_before_allocation ();
|
||||
|
||||
/* We only need stubs for the avr6 family. */
|
||||
if (strcmp ("${EMULATION_NAME}","avr6"))
|
||||
/* We only need stubs for avr6, avrxmega6, and avrxmega7. */
|
||||
if (strcmp ("${EMULATION_NAME}","avr6")
|
||||
&& strcmp ("${EMULATION_NAME}","avrxmega6")
|
||||
&& strcmp ("${EMULATION_NAME}","avrxmega7") )
|
||||
avr_no_stubs = TRUE;
|
||||
|
||||
avr_elf_set_global_bfd_parameters ();
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
|
||||
|
||||
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
|
||||
post-increment to support LPM Z+ instruction. Add support for 'E'
|
||||
constraint for DES instruction.
|
||||
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
|
||||
|
||||
2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
|
||||
|
||||
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ static const char * comment_start = "0x";
|
|||
|
||||
static int
|
||||
avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
|
||||
char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
|
||||
char *opcode_str, char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
|
||||
{
|
||||
int ok = 1;
|
||||
*sym = 0;
|
||||
|
|
@ -118,8 +118,18 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
|
|||
|
||||
case 'z':
|
||||
*buf++ = 'Z';
|
||||
if (insn & 0x1)
|
||||
|
||||
/* Check for post-increment. */
|
||||
char *s;
|
||||
for (s = opcode_str; *s; ++s)
|
||||
{
|
||||
if (*s == '+')
|
||||
{
|
||||
*buf++ = '+';
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
*buf = '\0';
|
||||
if (AVR_UNDEF_P (insn))
|
||||
sprintf (comment, _("undefined"));
|
||||
|
|
@ -227,6 +237,10 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
|
|||
}
|
||||
break;
|
||||
|
||||
case 'E':
|
||||
sprintf (buf, "%d", (insn >> 4) & 15);
|
||||
break;
|
||||
|
||||
case '?':
|
||||
*buf = '\0';
|
||||
break;
|
||||
|
|
@ -331,7 +345,8 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
|
|||
|
||||
if (opcode->name)
|
||||
{
|
||||
char *op = opcode->constraints;
|
||||
char *constraints = opcode->constraints;
|
||||
char *opcode_str = opcode->opcode;
|
||||
|
||||
insn2 = 0;
|
||||
ok = 1;
|
||||
|
|
@ -342,14 +357,14 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
|
|||
cmd_len = 4;
|
||||
}
|
||||
|
||||
if (*op && *op != '?')
|
||||
if (*constraints && *constraints != '?')
|
||||
{
|
||||
int regs = REGISTER_P (*op);
|
||||
int regs = REGISTER_P (*constraints);
|
||||
|
||||
ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0, &sym_op1, &sym_addr1);
|
||||
ok = avr_operand (insn, insn2, addr, *constraints, opcode_str, op1, comment1, 0, &sym_op1, &sym_addr1);
|
||||
|
||||
if (ok && *(++op) == ',')
|
||||
ok = avr_operand (insn, insn2, addr, *(++op), op2,
|
||||
if (ok && *(++constraints) == ',')
|
||||
ok = avr_operand (insn, insn2, addr, *(++constraints), opcode_str, op2,
|
||||
*comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue