* sparc-desc.c: New file.

* sparc-desc.h: New file.
	* sparc-opc.h: New file.
	* decode64.c: New file.
	* decode64.h: New file.
	* sem64.c: New file.
	* cpu64.c: New file.
	* cpu64.h: New file.
	* model64.h: New file.
	* mloop64.in: New file.
	* regs64.h: New file.
	* trap64.c: New file.
	* cpu32.h,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.

sim/sparc/.Sanitize

@@ -33,17 +33,25 @@ configure
 configure.in
 cpu32.c
 cpu32.h
+cpu64.c
+cpu64.h
 cpuall.h
 decode32.c
 decode32.h
+decode64.c
+decode64.h
 dev32.c
 dev32.h
 dev64.c
 dev64.h
 mloop32.in
+mloop64.in
 model32.c
+model64.c
 regs32.h
+regs64.h
 sem32.c
+sem64.c
 sim-if.c
 sim-main.h
 sparc-sim.h
@@ -53,6 +61,7 @@ sparc64.c
 tconfig.in
 trap32.c
 trap32.h
+trap64.c
 trap64.h
 
 Things-to-lose:

sim/sparc/cpu64.c

@@ -0,0 +1,759 @@
+/* Misc. support for CPU family sparc64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1999 Cygnus Solutions, Inc.
+
+This file is part of the Cygnus Simulators.
+
+
+*/
+
+#define WANT_CPU sparc64
+#define WANT_CPU_SPARC64
+
+#include "sim-main.h"
+
+/* Get the value of h-pc.  */
+
+USI
+sparc64_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+sparc64_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-npc.  */
+
+SI
+sparc64_h_npc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_npc);
+}
+
+/* Set a value for h-npc.  */
+
+void
+sparc64_h_npc_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_npc) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+SI
+sparc64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_GR (regno);
+}
+
+/* Set a value for h-gr.  */
+
+void
+sparc64_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  SET_H_GR (regno, newval);
+}
+
+/* Get the value of h-icc-c.  */
+
+BI
+sparc64_h_icc_c_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_icc_c);
+}
+
+/* Set a value for h-icc-c.  */
+
+void
+sparc64_h_icc_c_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_icc_c) = newval;
+}
+
+/* Get the value of h-icc-n.  */
+
+BI
+sparc64_h_icc_n_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_icc_n);
+}
+
+/* Set a value for h-icc-n.  */
+
+void
+sparc64_h_icc_n_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_icc_n) = newval;
+}
+
+/* Get the value of h-icc-v.  */
+
+BI
+sparc64_h_icc_v_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_icc_v);
+}
+
+/* Set a value for h-icc-v.  */
+
+void
+sparc64_h_icc_v_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_icc_v) = newval;
+}
+
+/* Get the value of h-icc-z.  */
+
+BI
+sparc64_h_icc_z_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_icc_z);
+}
+
+/* Set a value for h-icc-z.  */
+
+void
+sparc64_h_icc_z_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_icc_z) = newval;
+}
+
+/* Get the value of h-xcc-c.  */
+
+BI
+sparc64_h_xcc_c_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_xcc_c);
+}
+
+/* Set a value for h-xcc-c.  */
+
+void
+sparc64_h_xcc_c_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_xcc_c) = newval;
+}
+
+/* Get the value of h-xcc-n.  */
+
+BI
+sparc64_h_xcc_n_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_xcc_n);
+}
+
+/* Set a value for h-xcc-n.  */
+
+void
+sparc64_h_xcc_n_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_xcc_n) = newval;
+}
+
+/* Get the value of h-xcc-v.  */
+
+BI
+sparc64_h_xcc_v_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_xcc_v);
+}
+
+/* Set a value for h-xcc-v.  */
+
+void
+sparc64_h_xcc_v_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_xcc_v) = newval;
+}
+
+/* Get the value of h-xcc-z.  */
+
+BI
+sparc64_h_xcc_z_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_xcc_z);
+}
+
+/* Set a value for h-xcc-z.  */
+
+void
+sparc64_h_xcc_z_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_xcc_z) = newval;
+}
+
+/* Get the value of h-y.  */
+
+SI
+sparc64_h_y_get (SIM_CPU *current_cpu)
+{
+  return GET_H_Y ();
+}
+
+/* Set a value for h-y.  */
+
+void
+sparc64_h_y_set (SIM_CPU *current_cpu, SI newval)
+{
+  SET_H_Y (newval);
+}
+
+/* Get the value of h-asr.  */
+
+SI
+sparc64_h_asr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_asr[regno]);
+}
+
+/* Set a value for h-asr.  */
+
+void
+sparc64_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_asr[regno]) = newval;
+}
+
+/* Get the value of h-annul-p.  */
+
+BI
+sparc64_h_annul_p_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_annul_p);
+}
+
+/* Set a value for h-annul-p.  */
+
+void
+sparc64_h_annul_p_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_annul_p) = newval;
+}
+
+/* Get the value of h-fr.  */
+
+SF
+sparc64_h_fr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_fr[regno]);
+}
+
+/* Set a value for h-fr.  */
+
+void
+sparc64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+  CPU (h_fr[regno]) = newval;
+}
+
+/* Get the value of h-ver.  */
+
+UDI
+sparc64_h_ver_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_ver);
+}
+
+/* Set a value for h-ver.  */
+
+void
+sparc64_h_ver_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_ver) = newval;
+}
+
+/* Get the value of h-pstate.  */
+
+UDI
+sparc64_h_pstate_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pstate);
+}
+
+/* Set a value for h-pstate.  */
+
+void
+sparc64_h_pstate_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_pstate) = newval;
+}
+
+/* Get the value of h-tba.  */
+
+UDI
+sparc64_h_tba_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tba);
+}
+
+/* Set a value for h-tba.  */
+
+void
+sparc64_h_tba_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_tba) = newval;
+}
+
+/* Get the value of h-tt.  */
+
+UDI
+sparc64_h_tt_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tt);
+}
+
+/* Set a value for h-tt.  */
+
+void
+sparc64_h_tt_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_tt) = newval;
+}
+
+/* Get the value of h-tpc.  */
+
+UDI
+sparc64_h_tpc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tpc);
+}
+
+/* Set a value for h-tpc.  */
+
+void
+sparc64_h_tpc_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_tpc) = newval;
+}
+
+/* Get the value of h-tnpc.  */
+
+UDI
+sparc64_h_tnpc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tnpc);
+}
+
+/* Set a value for h-tnpc.  */
+
+void
+sparc64_h_tnpc_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_tnpc) = newval;
+}
+
+/* Get the value of h-tstate.  */
+
+UDI
+sparc64_h_tstate_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tstate);
+}
+
+/* Set a value for h-tstate.  */
+
+void
+sparc64_h_tstate_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_tstate) = newval;
+}
+
+/* Get the value of h-tl.  */
+
+UQI
+sparc64_h_tl_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tl);
+}
+
+/* Set a value for h-tl.  */
+
+void
+sparc64_h_tl_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_tl) = newval;
+}
+
+/* Get the value of h-asi.  */
+
+UQI
+sparc64_h_asi_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_asi);
+}
+
+/* Set a value for h-asi.  */
+
+void
+sparc64_h_asi_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_asi) = newval;
+}
+
+/* Get the value of h-tick.  */
+
+UDI
+sparc64_h_tick_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tick);
+}
+
+/* Set a value for h-tick.  */
+
+void
+sparc64_h_tick_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_tick) = newval;
+}
+
+/* Get the value of h-cansave.  */
+
+UDI
+sparc64_h_cansave_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cansave);
+}
+
+/* Set a value for h-cansave.  */
+
+void
+sparc64_h_cansave_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_cansave) = newval;
+}
+
+/* Get the value of h-canrestore.  */
+
+UDI
+sparc64_h_canrestore_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_canrestore);
+}
+
+/* Set a value for h-canrestore.  */
+
+void
+sparc64_h_canrestore_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_canrestore) = newval;
+}
+
+/* Get the value of h-otherwin.  */
+
+UDI
+sparc64_h_otherwin_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_otherwin);
+}
+
+/* Set a value for h-otherwin.  */
+
+void
+sparc64_h_otherwin_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_otherwin) = newval;
+}
+
+/* Get the value of h-cleanwin.  */
+
+UDI
+sparc64_h_cleanwin_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cleanwin);
+}
+
+/* Set a value for h-cleanwin.  */
+
+void
+sparc64_h_cleanwin_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_cleanwin) = newval;
+}
+
+/* Get the value of h-wstate.  */
+
+UDI
+sparc64_h_wstate_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_wstate);
+}
+
+/* Set a value for h-wstate.  */
+
+void
+sparc64_h_wstate_set (SIM_CPU *current_cpu, UDI newval)
+{
+  CPU (h_wstate) = newval;
+}
+
+/* Get the value of h-fcc0.  */
+
+UQI
+sparc64_h_fcc0_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fcc0);
+}
+
+/* Set a value for h-fcc0.  */
+
+void
+sparc64_h_fcc0_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fcc0) = newval;
+}
+
+/* Get the value of h-fcc1.  */
+
+UQI
+sparc64_h_fcc1_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fcc1);
+}
+
+/* Set a value for h-fcc1.  */
+
+void
+sparc64_h_fcc1_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fcc1) = newval;
+}
+
+/* Get the value of h-fcc2.  */
+
+UQI
+sparc64_h_fcc2_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fcc2);
+}
+
+/* Set a value for h-fcc2.  */
+
+void
+sparc64_h_fcc2_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fcc2) = newval;
+}
+
+/* Get the value of h-fcc3.  */
+
+UQI
+sparc64_h_fcc3_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fcc3);
+}
+
+/* Set a value for h-fcc3.  */
+
+void
+sparc64_h_fcc3_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fcc3) = newval;
+}
+
+/* Get the value of h-fsr-rd.  */
+
+UQI
+sparc64_h_fsr_rd_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_rd);
+}
+
+/* Set a value for h-fsr-rd.  */
+
+void
+sparc64_h_fsr_rd_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fsr_rd) = newval;
+}
+
+/* Get the value of h-fsr-tem.  */
+
+UQI
+sparc64_h_fsr_tem_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_tem);
+}
+
+/* Set a value for h-fsr-tem.  */
+
+void
+sparc64_h_fsr_tem_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fsr_tem) = newval;
+}
+
+/* Get the value of h-fsr-ns.  */
+
+BI
+sparc64_h_fsr_ns_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_ns);
+}
+
+/* Set a value for h-fsr-ns.  */
+
+void
+sparc64_h_fsr_ns_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_fsr_ns) = newval;
+}
+
+/* Get the value of h-fsr-ver.  */
+
+UQI
+sparc64_h_fsr_ver_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_ver);
+}
+
+/* Set a value for h-fsr-ver.  */
+
+void
+sparc64_h_fsr_ver_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fsr_ver) = newval;
+}
+
+/* Get the value of h-fsr-ftt.  */
+
+UQI
+sparc64_h_fsr_ftt_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_ftt);
+}
+
+/* Set a value for h-fsr-ftt.  */
+
+void
+sparc64_h_fsr_ftt_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fsr_ftt) = newval;
+}
+
+/* Get the value of h-fsr-qne.  */
+
+BI
+sparc64_h_fsr_qne_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_qne);
+}
+
+/* Set a value for h-fsr-qne.  */
+
+void
+sparc64_h_fsr_qne_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_fsr_qne) = newval;
+}
+
+/* Get the value of h-fsr-aexc.  */
+
+UQI
+sparc64_h_fsr_aexc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_aexc);
+}
+
+/* Set a value for h-fsr-aexc.  */
+
+void
+sparc64_h_fsr_aexc_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fsr_aexc) = newval;
+}
+
+/* Get the value of h-fsr-cexc.  */
+
+UQI
+sparc64_h_fsr_cexc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fsr_cexc);
+}
+
+/* Set a value for h-fsr-cexc.  */
+
+void
+sparc64_h_fsr_cexc_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_fsr_cexc) = newval;
+}
+
+/* Get the value of h-fpsr-fef.  */
+
+BI
+sparc64_h_fpsr_fef_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fpsr_fef);
+}
+
+/* Set a value for h-fpsr-fef.  */
+
+void
+sparc64_h_fpsr_fef_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_fpsr_fef) = newval;
+}
+
+/* Get the value of h-fpsr-du.  */
+
+BI
+sparc64_h_fpsr_du_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fpsr_du);
+}
+
+/* Set a value for h-fpsr-du.  */
+
+void
+sparc64_h_fpsr_du_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_fpsr_du) = newval;
+}
+
+/* Get the value of h-fpsr-dl.  */
+
+BI
+sparc64_h_fpsr_dl_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_fpsr_dl);
+}
+
+/* Set a value for h-fpsr-dl.  */
+
+void
+sparc64_h_fpsr_dl_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_fpsr_dl) = newval;
+}
+
+/* Get the value of h-fpsr.  */
+
+UQI
+sparc64_h_fpsr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_FPSR ();
+}
+
+/* Set a value for h-fpsr.  */
+
+void
+sparc64_h_fpsr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_FPSR (newval);
+}
+
+/* Record trace results for INSN.  */
+
+void
+sparc64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}

sim/sparc/cpu64.h

@@ -0,0 +1,818 @@
+/* CPU family header for sparc64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1999 Cygnus Solutions, Inc.
+
+This file is part of the Cygnus Simulators.
+
+
+*/
+
+#ifndef CPU_SPARC64_H
+#define CPU_SPARC64_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+  /* next pc */
+  SI h_npc;
+#define GET_H_NPC() CPU (h_npc)
+#define SET_H_NPC(x) (CPU (h_npc) = (x))
+/* GET_H_GR macro user-written */
+/* SET_H_GR macro user-written */
+  /* icc carry bit */
+  BI h_icc_c;
+#define GET_H_ICC_C() CPU (h_icc_c)
+#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x))
+  /* icc negative bit */
+  BI h_icc_n;
+#define GET_H_ICC_N() CPU (h_icc_n)
+#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x))
+  /* icc overflow bit */
+  BI h_icc_v;
+#define GET_H_ICC_V() CPU (h_icc_v)
+#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x))
+  /* icc zero bit */
+  BI h_icc_z;
+#define GET_H_ICC_Z() CPU (h_icc_z)
+#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x))
+  /* xcc carry bit */
+  BI h_xcc_c;
+#define GET_H_XCC_C() CPU (h_xcc_c)
+#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x))
+  /* xcc negative bit */
+  BI h_xcc_n;
+#define GET_H_XCC_N() CPU (h_xcc_n)
+#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x))
+  /* xcc overflow bit */
+  BI h_xcc_v;
+#define GET_H_XCC_V() CPU (h_xcc_v)
+#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x))
+  /* xcc zero bit */
+  BI h_xcc_z;
+#define GET_H_XCC_Z() CPU (h_xcc_z)
+#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x))
+/* GET_H_Y macro user-written */
+/* SET_H_Y macro user-written */
+  /* ancilliary state registers */
+  SI h_asr[32];
+#define GET_H_ASR(a1) CPU (h_asr)[a1]
+#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x))
+  /* annul next insn? - assists execution */
+  BI h_annul_p;
+#define GET_H_ANNUL_P() CPU (h_annul_p)
+#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x))
+  /* floating point regs */
+  SF h_fr[32];
+#define GET_H_FR(a1) CPU (h_fr)[a1]
+#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
+  /* version */
+  UDI h_ver;
+#define GET_H_VER() CPU (h_ver)
+#define SET_H_VER(x) (CPU (h_ver) = (x))
+  /* processor state */
+  UDI h_pstate;
+#define GET_H_PSTATE() CPU (h_pstate)
+#define SET_H_PSTATE(x) (CPU (h_pstate) = (x))
+  /* trap base address */
+  UDI h_tba;
+#define GET_H_TBA() CPU (h_tba)
+#define SET_H_TBA(x) (CPU (h_tba) = (x))
+  /* trap type */
+  UDI h_tt;
+#define GET_H_TT() CPU (h_tt)
+#define SET_H_TT(x) (CPU (h_tt) = (x))
+  /* trap pc */
+  UDI h_tpc;
+#define GET_H_TPC() CPU (h_tpc)
+#define SET_H_TPC(x) (CPU (h_tpc) = (x))
+  /* trap npc */
+  UDI h_tnpc;
+#define GET_H_TNPC() CPU (h_tnpc)
+#define SET_H_TNPC(x) (CPU (h_tnpc) = (x))
+  /* trap state */
+  UDI h_tstate;
+#define GET_H_TSTATE() CPU (h_tstate)
+#define SET_H_TSTATE(x) (CPU (h_tstate) = (x))
+  /* trap level */
+  UQI h_tl;
+#define GET_H_TL() CPU (h_tl)
+#define SET_H_TL(x) (CPU (h_tl) = (x))
+  /* address space identifier */
+  UQI h_asi;
+#define GET_H_ASI() CPU (h_asi)
+#define SET_H_ASI(x) (CPU (h_asi) = (x))
+  /* tick counter */
+  UDI h_tick;
+#define GET_H_TICK() CPU (h_tick)
+#define SET_H_TICK(x) (CPU (h_tick) = (x))
+  /* savable window registers */
+  UDI h_cansave;
+#define GET_H_CANSAVE() CPU (h_cansave)
+#define SET_H_CANSAVE(x) (CPU (h_cansave) = (x))
+  /* restorable window registers */
+  UDI h_canrestore;
+#define GET_H_CANRESTORE() CPU (h_canrestore)
+#define SET_H_CANRESTORE(x) (CPU (h_canrestore) = (x))
+  /* other window registers */
+  UDI h_otherwin;
+#define GET_H_OTHERWIN() CPU (h_otherwin)
+#define SET_H_OTHERWIN(x) (CPU (h_otherwin) = (x))
+  /* clean window registers */
+  UDI h_cleanwin;
+#define GET_H_CLEANWIN() CPU (h_cleanwin)
+#define SET_H_CLEANWIN(x) (CPU (h_cleanwin) = (x))
+  /* window state */
+  UDI h_wstate;
+#define GET_H_WSTATE() CPU (h_wstate)
+#define SET_H_WSTATE(x) (CPU (h_wstate) = (x))
+  /*  */
+  UQI h_fcc0;
+#define GET_H_FCC0() CPU (h_fcc0)
+#define SET_H_FCC0(x) (CPU (h_fcc0) = (x))
+  /*  */
+  UQI h_fcc1;
+#define GET_H_FCC1() CPU (h_fcc1)
+#define SET_H_FCC1(x) (CPU (h_fcc1) = (x))
+  /*  */
+  UQI h_fcc2;
+#define GET_H_FCC2() CPU (h_fcc2)
+#define SET_H_FCC2(x) (CPU (h_fcc2) = (x))
+  /*  */
+  UQI h_fcc3;
+#define GET_H_FCC3() CPU (h_fcc3)
+#define SET_H_FCC3(x) (CPU (h_fcc3) = (x))
+  /* fsr rounding direction */
+  UQI h_fsr_rd;
+#define GET_H_FSR_RD() CPU (h_fsr_rd)
+#define SET_H_FSR_RD(x) (CPU (h_fsr_rd) = (x))
+  /* fsr trap enable mask */
+  UQI h_fsr_tem;
+#define GET_H_FSR_TEM() CPU (h_fsr_tem)
+#define SET_H_FSR_TEM(x) (CPU (h_fsr_tem) = (x))
+  /* fsr nonstandard fp */
+  BI h_fsr_ns;
+#define GET_H_FSR_NS() CPU (h_fsr_ns)
+#define SET_H_FSR_NS(x) (CPU (h_fsr_ns) = (x))
+  /* fsr version */
+  UQI h_fsr_ver;
+#define GET_H_FSR_VER() CPU (h_fsr_ver)
+#define SET_H_FSR_VER(x) (CPU (h_fsr_ver) = (x))
+  /* fsr fp trap type */
+  UQI h_fsr_ftt;
+#define GET_H_FSR_FTT() CPU (h_fsr_ftt)
+#define SET_H_FSR_FTT(x) (CPU (h_fsr_ftt) = (x))
+  /* fsr queue not empty */
+  BI h_fsr_qne;
+#define GET_H_FSR_QNE() CPU (h_fsr_qne)
+#define SET_H_FSR_QNE(x) (CPU (h_fsr_qne) = (x))
+  /* fsr accrued exception */
+  UQI h_fsr_aexc;
+#define GET_H_FSR_AEXC() CPU (h_fsr_aexc)
+#define SET_H_FSR_AEXC(x) (CPU (h_fsr_aexc) = (x))
+  /* fsr current exception */
+  UQI h_fsr_cexc;
+#define GET_H_FSR_CEXC() CPU (h_fsr_cexc)
+#define SET_H_FSR_CEXC(x) (CPU (h_fsr_cexc) = (x))
+  /* fpsr enable fp */
+  BI h_fpsr_fef;
+#define GET_H_FPSR_FEF() CPU (h_fpsr_fef)
+#define SET_H_FPSR_FEF(x) (CPU (h_fpsr_fef) = (x))
+  /* fpsr dirty upper */
+  BI h_fpsr_du;
+#define GET_H_FPSR_DU() CPU (h_fpsr_du)
+#define SET_H_FPSR_DU(x) (CPU (h_fpsr_du) = (x))
+  /* fpsr dirty lower */
+  BI h_fpsr_dl;
+#define GET_H_FPSR_DL() CPU (h_fpsr_dl)
+#define SET_H_FPSR_DL(x) (CPU (h_fpsr_dl) = (x))
+/* GET_H_FPSR macro user-written */
+/* SET_H_FPSR macro user-written */
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} SPARC64_CPU_DATA;
+
+/* Cover fns for register access.  */
+USI sparc64_h_pc_get (SIM_CPU *);
+void sparc64_h_pc_set (SIM_CPU *, USI);
+SI sparc64_h_npc_get (SIM_CPU *);
+void sparc64_h_npc_set (SIM_CPU *, SI);
+SI sparc64_h_gr_get (SIM_CPU *, UINT);
+void sparc64_h_gr_set (SIM_CPU *, UINT, SI);
+BI sparc64_h_icc_c_get (SIM_CPU *);
+void sparc64_h_icc_c_set (SIM_CPU *, BI);
+BI sparc64_h_icc_n_get (SIM_CPU *);
+void sparc64_h_icc_n_set (SIM_CPU *, BI);
+BI sparc64_h_icc_v_get (SIM_CPU *);
+void sparc64_h_icc_v_set (SIM_CPU *, BI);
+BI sparc64_h_icc_z_get (SIM_CPU *);
+void sparc64_h_icc_z_set (SIM_CPU *, BI);
+BI sparc64_h_xcc_c_get (SIM_CPU *);
+void sparc64_h_xcc_c_set (SIM_CPU *, BI);
+BI sparc64_h_xcc_n_get (SIM_CPU *);
+void sparc64_h_xcc_n_set (SIM_CPU *, BI);
+BI sparc64_h_xcc_v_get (SIM_CPU *);
+void sparc64_h_xcc_v_set (SIM_CPU *, BI);
+BI sparc64_h_xcc_z_get (SIM_CPU *);
+void sparc64_h_xcc_z_set (SIM_CPU *, BI);
+SI sparc64_h_y_get (SIM_CPU *);
+void sparc64_h_y_set (SIM_CPU *, SI);
+SI sparc64_h_asr_get (SIM_CPU *, UINT);
+void sparc64_h_asr_set (SIM_CPU *, UINT, SI);
+BI sparc64_h_annul_p_get (SIM_CPU *);
+void sparc64_h_annul_p_set (SIM_CPU *, BI);
+SF sparc64_h_fr_get (SIM_CPU *, UINT);
+void sparc64_h_fr_set (SIM_CPU *, UINT, SF);
+UDI sparc64_h_ver_get (SIM_CPU *);
+void sparc64_h_ver_set (SIM_CPU *, UDI);
+UDI sparc64_h_pstate_get (SIM_CPU *);
+void sparc64_h_pstate_set (SIM_CPU *, UDI);
+UDI sparc64_h_tba_get (SIM_CPU *);
+void sparc64_h_tba_set (SIM_CPU *, UDI);
+UDI sparc64_h_tt_get (SIM_CPU *);
+void sparc64_h_tt_set (SIM_CPU *, UDI);
+UDI sparc64_h_tpc_get (SIM_CPU *);
+void sparc64_h_tpc_set (SIM_CPU *, UDI);
+UDI sparc64_h_tnpc_get (SIM_CPU *);
+void sparc64_h_tnpc_set (SIM_CPU *, UDI);
+UDI sparc64_h_tstate_get (SIM_CPU *);
+void sparc64_h_tstate_set (SIM_CPU *, UDI);
+UQI sparc64_h_tl_get (SIM_CPU *);
+void sparc64_h_tl_set (SIM_CPU *, UQI);
+UQI sparc64_h_asi_get (SIM_CPU *);
+void sparc64_h_asi_set (SIM_CPU *, UQI);
+UDI sparc64_h_tick_get (SIM_CPU *);
+void sparc64_h_tick_set (SIM_CPU *, UDI);
+UDI sparc64_h_cansave_get (SIM_CPU *);
+void sparc64_h_cansave_set (SIM_CPU *, UDI);
+UDI sparc64_h_canrestore_get (SIM_CPU *);
+void sparc64_h_canrestore_set (SIM_CPU *, UDI);
+UDI sparc64_h_otherwin_get (SIM_CPU *);
+void sparc64_h_otherwin_set (SIM_CPU *, UDI);
+UDI sparc64_h_cleanwin_get (SIM_CPU *);
+void sparc64_h_cleanwin_set (SIM_CPU *, UDI);
+UDI sparc64_h_wstate_get (SIM_CPU *);
+void sparc64_h_wstate_set (SIM_CPU *, UDI);
+UQI sparc64_h_fcc0_get (SIM_CPU *);
+void sparc64_h_fcc0_set (SIM_CPU *, UQI);
+UQI sparc64_h_fcc1_get (SIM_CPU *);
+void sparc64_h_fcc1_set (SIM_CPU *, UQI);
+UQI sparc64_h_fcc2_get (SIM_CPU *);
+void sparc64_h_fcc2_set (SIM_CPU *, UQI);
+UQI sparc64_h_fcc3_get (SIM_CPU *);
+void sparc64_h_fcc3_set (SIM_CPU *, UQI);
+UQI sparc64_h_fsr_rd_get (SIM_CPU *);
+void sparc64_h_fsr_rd_set (SIM_CPU *, UQI);
+UQI sparc64_h_fsr_tem_get (SIM_CPU *);
+void sparc64_h_fsr_tem_set (SIM_CPU *, UQI);
+BI sparc64_h_fsr_ns_get (SIM_CPU *);
+void sparc64_h_fsr_ns_set (SIM_CPU *, BI);
+UQI sparc64_h_fsr_ver_get (SIM_CPU *);
+void sparc64_h_fsr_ver_set (SIM_CPU *, UQI);
+UQI sparc64_h_fsr_ftt_get (SIM_CPU *);
+void sparc64_h_fsr_ftt_set (SIM_CPU *, UQI);
+BI sparc64_h_fsr_qne_get (SIM_CPU *);
+void sparc64_h_fsr_qne_set (SIM_CPU *, BI);
+UQI sparc64_h_fsr_aexc_get (SIM_CPU *);
+void sparc64_h_fsr_aexc_set (SIM_CPU *, UQI);
+UQI sparc64_h_fsr_cexc_get (SIM_CPU *);
+void sparc64_h_fsr_cexc_set (SIM_CPU *, UQI);
+BI sparc64_h_fpsr_fef_get (SIM_CPU *);
+void sparc64_h_fpsr_fef_set (SIM_CPU *, BI);
+BI sparc64_h_fpsr_du_get (SIM_CPU *);
+void sparc64_h_fpsr_du_set (SIM_CPU *, BI);
+BI sparc64_h_fpsr_dl_get (SIM_CPU *);
+void sparc64_h_fpsr_dl_set (SIM_CPU *, BI);
+UQI sparc64_h_fpsr_get (SIM_CPU *);
+void sparc64_h_fpsr_set (SIM_CPU *, UQI);
+
+/* These must be hand-written.  */
+extern CPUREG_FETCH_FN sparc64_fetch_register;
+extern CPUREG_STORE_FN sparc64_store_register;
+
+typedef struct {
+  int empty;
+} MODEL_SPARC64_DEF_DATA;
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* cpu specific data follows */
+  CGEN_INSN_INT insn;
+  int written;
+};
+
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+  /* Instruction fields.  */ \
+  unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+  length = 0; \
+
+#define EXTRACT_IFMT_BEQZ_VARS \
+  /* Instruction fields.  */ \
+  INT f_disp16; \
+  UINT f_disp16_hi; \
+  UINT f_disp16_lo; \
+  UINT f_rs1; \
+  UINT f_p; \
+  UINT f_op2; \
+  UINT f_fmt2_rcond; \
+  INT f_bpr_res28_1; \
+  UINT f_a; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_BEQZ_CODE \
+  length = 4; \
+  f_disp16_hi = EXTRACT_UINT (insn, 32, 10, 2); \
+  f_disp16_lo = EXTRACT_UINT (insn, 32, 18, 14); \
+do {\
+  f_disp16 = ((((f_disp16_hi) << (14))) | (f_disp16_low));\
+} while (0);\
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_p = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
+  f_fmt2_rcond = EXTRACT_UINT (insn, 32, 27, 3); \
+  f_bpr_res28_1 = EXTRACT_INT (insn, 32, 28, 1); \
+  f_a = EXTRACT_UINT (insn, 32, 29, 1); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_BPCC_BA_VARS \
+  /* Instruction fields.  */ \
+  INT f_disp19; \
+  UINT f_p; \
+  UINT f_fmt2_cc0; \
+  UINT f_fmt2_cc1; \
+  UINT f_op2; \
+  UINT f_fmt2_cond; \
+  UINT f_a; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_BPCC_BA_CODE \
+  length = 4; \
+  f_disp19 = EXTRACT_INT (insn, 32, 13, 19); \
+  f_p = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_fmt2_cc0 = EXTRACT_UINT (insn, 32, 20, 1); \
+  f_fmt2_cc1 = EXTRACT_UINT (insn, 32, 21, 1); \
+  f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
+  f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
+  f_a = EXTRACT_UINT (insn, 32, 29, 1); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_DONE_VARS \
+  /* Instruction fields.  */ \
+  INT f_res_18_19; \
+  UINT f_op3; \
+  UINT f_fcn; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_DONE_CODE \
+  length = 4; \
+  f_res_18_19 = EXTRACT_INT (insn, 32, 18, 19); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_fcn = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_FLUSH_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  INT f_res_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_FLUSH_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_FLUSH_IMM_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm13; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_FLUSH_IMM_CODE \
+  length = 4; \
+  f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_FLUSHW_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm13; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_FLUSHW_CODE \
+  length = 4; \
+  f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_IMPDEP1_VARS \
+  /* Instruction fields.  */ \
+  INT f_impdep19; \
+  UINT f_op3; \
+  INT f_impdep5; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_IMPDEP1_CODE \
+  length = 4; \
+  f_impdep19 = EXTRACT_INT (insn, 32, 18, 19); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_impdep5 = EXTRACT_INT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_MEMBAR_VARS \
+  /* Instruction fields.  */ \
+  UINT f_membarmask; \
+  INT f_membar_res12_6; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_MEMBAR_CODE \
+  length = 4; \
+  f_membarmask = EXTRACT_UINT (insn, 32, 6, 7); \
+  f_membar_res12_6 = EXTRACT_INT (insn, 32, 12, 6); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_MOVA_ICC_ICC_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  INT f_fmt4_res10_6; \
+  UINT f_fmt4_cc1_0; \
+  UINT f_i; \
+  UINT f_fmt4_cc2; \
+  UINT f_op3; \
+  UINT f_fmt2_cond; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_MOVA_ICC_ICC_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_fmt4_res10_6 = EXTRACT_INT (insn, 32, 10, 6); \
+  f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm11; \
+  UINT f_fmt4_cc1_0; \
+  UINT f_i; \
+  UINT f_fmt4_cc2; \
+  UINT f_op3; \
+  UINT f_fmt2_cond; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE \
+  length = 4; \
+  f_simm11 = EXTRACT_INT (insn, 32, 10, 11); \
+  f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_LDSB_REG_REG_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  INT f_res_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDSB_REG_REG_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_LDSB_REG_IMM_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm13; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDSB_REG_IMM_CODE \
+  length = 4; \
+  f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  UINT f_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_LDD_REG_REG_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  INT f_res_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDD_REG_REG_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_LDD_REG_IMM_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm13; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDD_REG_IMM_CODE \
+  length = 4; \
+  f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  UINT f_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  INT f_res_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm13; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \
+  length = 4; \
+  f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  UINT f_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_SETHI_VARS \
+  /* Instruction fields.  */ \
+  INT f_hi22; \
+  UINT f_op2; \
+  UINT f_rd; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_SETHI_CODE \
+  length = 4; \
+  f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \
+  f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
+  f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_UNIMP_VARS \
+  /* Instruction fields.  */ \
+  INT f_imm22; \
+  UINT f_op2; \
+  UINT f_rd_res; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_UNIMP_CODE \
+  length = 4; \
+  f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \
+  f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
+  f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_CALL_VARS \
+  /* Instruction fields.  */ \
+  SI f_disp30; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_CALL_CODE \
+  length = 4; \
+  f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_BA_VARS \
+  /* Instruction fields.  */ \
+  SI f_disp22; \
+  UINT f_op2; \
+  UINT f_fmt2_cond; \
+  UINT f_a; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_BA_CODE \
+  length = 4; \
+  f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \
+  f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
+  f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
+  f_a = EXTRACT_UINT (insn, 32, 29, 1); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_TA_VARS \
+  /* Instruction fields.  */ \
+  UINT f_rs2; \
+  INT f_res_asi; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_fmt2_cond; \
+  UINT f_a; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_TA_CODE \
+  length = 4; \
+  f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
+  f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
+  f_a = EXTRACT_UINT (insn, 32, 29, 1); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+#define EXTRACT_IFMT_TA_IMM_VARS \
+  /* Instruction fields.  */ \
+  INT f_simm13; \
+  UINT f_i; \
+  UINT f_rs1; \
+  UINT f_op3; \
+  UINT f_fmt2_cond; \
+  UINT f_a; \
+  UINT f_op; \
+  unsigned int length;
+#define EXTRACT_IFMT_TA_IMM_CODE \
+  length = 4; \
+  f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
+  f_i = EXTRACT_UINT (insn, 32, 13, 1); \
+  f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
+  f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
+  f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
+  f_a = EXTRACT_UINT (insn, 32, 29, 1); \
+  f_op = EXTRACT_UINT (insn, 32, 31, 2); \
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  IADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_SPARC64_H */

sim/sparc/decode64.h

@@ -0,0 +1,385 @@
+/* Decode header for sparc64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1999 Cygnus Solutions, Inc.
+
+This file is part of the Cygnus Simulators.
+
+
+*/
+
+#ifndef SPARC64_DECODE_H
+#define SPARC64_DECODE_H
+
+extern const IDESC *sparc64_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT, CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void sparc64_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family sparc64.  */
+typedef enum sparc64_insn_type {
+  SPARC64_INSN_X_INVALID, SPARC64_INSN_X_AFTER, SPARC64_INSN_X_BEFORE, SPARC64_INSN_X_CTI_CHAIN
+ , SPARC64_INSN_X_CHAIN, SPARC64_INSN_X_BEGIN, SPARC64_INSN_BEQZ, SPARC64_INSN_BGEZ
+ , SPARC64_INSN_BGTZ, SPARC64_INSN_BLEZ, SPARC64_INSN_BLTZ, SPARC64_INSN_BNEZ
+ , SPARC64_INSN_BPCC_BA, SPARC64_INSN_BPCC_BN, SPARC64_INSN_BPCC_BNE, SPARC64_INSN_BPCC_BE
+ , SPARC64_INSN_BPCC_BG, SPARC64_INSN_BPCC_BLE, SPARC64_INSN_BPCC_BGE, SPARC64_INSN_BPCC_BL
+ , SPARC64_INSN_BPCC_BGU, SPARC64_INSN_BPCC_BLEU, SPARC64_INSN_BPCC_BCC, SPARC64_INSN_BPCC_BCS
+ , SPARC64_INSN_BPCC_BPOS, SPARC64_INSN_BPCC_BNEG, SPARC64_INSN_BPCC_BVC, SPARC64_INSN_BPCC_BVS
+ , SPARC64_INSN_DONE, SPARC64_INSN_RETRY, SPARC64_INSN_FLUSH, SPARC64_INSN_FLUSH_IMM
+ , SPARC64_INSN_FLUSHW, SPARC64_INSN_IMPDEP1, SPARC64_INSN_IMPDEP2, SPARC64_INSN_MEMBAR
+ , SPARC64_INSN_MOVA_ICC_ICC, SPARC64_INSN_MOVA_IMM_ICC_ICC, SPARC64_INSN_MOVA_XCC_XCC, SPARC64_INSN_MOVA_IMM_XCC_XCC
+ , SPARC64_INSN_MOVN_ICC_ICC, SPARC64_INSN_MOVN_IMM_ICC_ICC, SPARC64_INSN_MOVN_XCC_XCC, SPARC64_INSN_MOVN_IMM_XCC_XCC
+ , SPARC64_INSN_MOVNE_ICC_ICC, SPARC64_INSN_MOVNE_IMM_ICC_ICC, SPARC64_INSN_MOVNE_XCC_XCC, SPARC64_INSN_MOVNE_IMM_XCC_XCC
+ , SPARC64_INSN_MOVE_ICC_ICC, SPARC64_INSN_MOVE_IMM_ICC_ICC, SPARC64_INSN_MOVE_XCC_XCC, SPARC64_INSN_MOVE_IMM_XCC_XCC
+ , SPARC64_INSN_MOVG_ICC_ICC, SPARC64_INSN_MOVG_IMM_ICC_ICC, SPARC64_INSN_MOVG_XCC_XCC, SPARC64_INSN_MOVG_IMM_XCC_XCC
+ , SPARC64_INSN_MOVLE_ICC_ICC, SPARC64_INSN_MOVLE_IMM_ICC_ICC, SPARC64_INSN_MOVLE_XCC_XCC, SPARC64_INSN_MOVLE_IMM_XCC_XCC
+ , SPARC64_INSN_MOVGE_ICC_ICC, SPARC64_INSN_MOVGE_IMM_ICC_ICC, SPARC64_INSN_MOVGE_XCC_XCC, SPARC64_INSN_MOVGE_IMM_XCC_XCC
+ , SPARC64_INSN_MOVL_ICC_ICC, SPARC64_INSN_MOVL_IMM_ICC_ICC, SPARC64_INSN_MOVL_XCC_XCC, SPARC64_INSN_MOVL_IMM_XCC_XCC
+ , SPARC64_INSN_MOVGU_ICC_ICC, SPARC64_INSN_MOVGU_IMM_ICC_ICC, SPARC64_INSN_MOVGU_XCC_XCC, SPARC64_INSN_MOVGU_IMM_XCC_XCC
+ , SPARC64_INSN_MOVLEU_ICC_ICC, SPARC64_INSN_MOVLEU_IMM_ICC_ICC, SPARC64_INSN_MOVLEU_XCC_XCC, SPARC64_INSN_MOVLEU_IMM_XCC_XCC
+ , SPARC64_INSN_MOVCC_ICC_ICC, SPARC64_INSN_MOVCC_IMM_ICC_ICC, SPARC64_INSN_MOVCC_XCC_XCC, SPARC64_INSN_MOVCC_IMM_XCC_XCC
+ , SPARC64_INSN_MOVCS_ICC_ICC, SPARC64_INSN_MOVCS_IMM_ICC_ICC, SPARC64_INSN_MOVCS_XCC_XCC, SPARC64_INSN_MOVCS_IMM_XCC_XCC
+ , SPARC64_INSN_MOVPOS_ICC_ICC, SPARC64_INSN_MOVPOS_IMM_ICC_ICC, SPARC64_INSN_MOVPOS_XCC_XCC, SPARC64_INSN_MOVPOS_IMM_XCC_XCC
+ , SPARC64_INSN_MOVNEG_ICC_ICC, SPARC64_INSN_MOVNEG_IMM_ICC_ICC, SPARC64_INSN_MOVNEG_XCC_XCC, SPARC64_INSN_MOVNEG_IMM_XCC_XCC
+ , SPARC64_INSN_MOVVC_ICC_ICC, SPARC64_INSN_MOVVC_IMM_ICC_ICC, SPARC64_INSN_MOVVC_XCC_XCC, SPARC64_INSN_MOVVC_IMM_XCC_XCC
+ , SPARC64_INSN_MOVVS_ICC_ICC, SPARC64_INSN_MOVVS_IMM_ICC_ICC, SPARC64_INSN_MOVVS_XCC_XCC, SPARC64_INSN_MOVVS_IMM_XCC_XCC
+ , SPARC64_INSN_LDSB_REG_REG, SPARC64_INSN_LDSB_REG_IMM, SPARC64_INSN_LDSB_REG_REG_ASI, SPARC64_INSN_LDUB_REG_REG
+ , SPARC64_INSN_LDUB_REG_IMM, SPARC64_INSN_LDUB_REG_REG_ASI, SPARC64_INSN_LDSH_REG_REG, SPARC64_INSN_LDSH_REG_IMM
+ , SPARC64_INSN_LDSH_REG_REG_ASI, SPARC64_INSN_LDUH_REG_REG, SPARC64_INSN_LDUH_REG_IMM, SPARC64_INSN_LDUH_REG_REG_ASI
+ , SPARC64_INSN_LDSW_REG_REG, SPARC64_INSN_LDSW_REG_IMM, SPARC64_INSN_LDSW_REG_REG_ASI, SPARC64_INSN_LDUW_REG_REG
+ , SPARC64_INSN_LDUW_REG_IMM, SPARC64_INSN_LDUW_REG_REG_ASI, SPARC64_INSN_LDX_REG_REG, SPARC64_INSN_LDX_REG_IMM
+ , SPARC64_INSN_LDX_REG_REG_ASI, SPARC64_INSN_LDD_REG_REG, SPARC64_INSN_LDD_REG_IMM, SPARC64_INSN_LDD_REG_REG_ASI
+ , SPARC64_INSN_STB_REG_REG, SPARC64_INSN_STB_REG_IMM, SPARC64_INSN_STB_REG_REG_ASI, SPARC64_INSN_STH_REG_REG
+ , SPARC64_INSN_STH_REG_IMM, SPARC64_INSN_STH_REG_REG_ASI, SPARC64_INSN_ST_REG_REG, SPARC64_INSN_ST_REG_IMM
+ , SPARC64_INSN_ST_REG_REG_ASI, SPARC64_INSN_STX_REG_REG, SPARC64_INSN_STX_REG_IMM, SPARC64_INSN_STX_REG_REG_ASI
+ , SPARC64_INSN_STD_REG_REG, SPARC64_INSN_STD_REG_IMM, SPARC64_INSN_STD_REG_REG_ASI, SPARC64_INSN_FP_LD_REG_REG
+ , SPARC64_INSN_FP_LD_REG_IMM, SPARC64_INSN_FP_LD_REG_REG_ASI, SPARC64_INSN_SETHI, SPARC64_INSN_ADD
+ , SPARC64_INSN_ADD_IMM, SPARC64_INSN_SUB, SPARC64_INSN_SUB_IMM, SPARC64_INSN_ADDCC
+ , SPARC64_INSN_ADDCC_IMM, SPARC64_INSN_SUBCC, SPARC64_INSN_SUBCC_IMM, SPARC64_INSN_ADDC
+ , SPARC64_INSN_ADDC_IMM, SPARC64_INSN_SUBC, SPARC64_INSN_SUBC_IMM, SPARC64_INSN_ADDCCC
+ , SPARC64_INSN_ADDCCC_IMM, SPARC64_INSN_SUBCCC, SPARC64_INSN_SUBCCC_IMM, SPARC64_INSN_AND
+ , SPARC64_INSN_AND_IMM, SPARC64_INSN_ANDCC, SPARC64_INSN_ANDCC_IMM, SPARC64_INSN_OR
+ , SPARC64_INSN_OR_IMM, SPARC64_INSN_ORCC, SPARC64_INSN_ORCC_IMM, SPARC64_INSN_XOR
+ , SPARC64_INSN_XOR_IMM, SPARC64_INSN_XORCC, SPARC64_INSN_XORCC_IMM, SPARC64_INSN_ANDN
+ , SPARC64_INSN_ANDN_IMM, SPARC64_INSN_ANDNCC, SPARC64_INSN_ANDNCC_IMM, SPARC64_INSN_ORN
+ , SPARC64_INSN_ORN_IMM, SPARC64_INSN_ORNCC, SPARC64_INSN_ORNCC_IMM, SPARC64_INSN_XNOR
+ , SPARC64_INSN_XNOR_IMM, SPARC64_INSN_XNORCC, SPARC64_INSN_XNORCC_IMM, SPARC64_INSN_SLL
+ , SPARC64_INSN_SLL_IMM, SPARC64_INSN_SRL, SPARC64_INSN_SRL_IMM, SPARC64_INSN_SRA
+ , SPARC64_INSN_SRA_IMM, SPARC64_INSN_SMUL, SPARC64_INSN_SMUL_IMM, SPARC64_INSN_SMUL_CC
+ , SPARC64_INSN_SMUL_CC_IMM, SPARC64_INSN_UMUL, SPARC64_INSN_UMUL_IMM, SPARC64_INSN_UMUL_CC
+ , SPARC64_INSN_UMUL_CC_IMM, SPARC64_INSN_MULSCC, SPARC64_INSN_SAVE, SPARC64_INSN_SAVE_IMM
+ , SPARC64_INSN_RESTORE, SPARC64_INSN_RESTORE_IMM, SPARC64_INSN_RETT, SPARC64_INSN_RETT_IMM
+ , SPARC64_INSN_UNIMP, SPARC64_INSN_CALL, SPARC64_INSN_JMPL, SPARC64_INSN_JMPL_IMM
+ , SPARC64_INSN_BA, SPARC64_INSN_TA, SPARC64_INSN_TA_IMM, SPARC64_INSN_BN
+ , SPARC64_INSN_TN, SPARC64_INSN_TN_IMM, SPARC64_INSN_BNE, SPARC64_INSN_TNE
+ , SPARC64_INSN_TNE_IMM, SPARC64_INSN_BE, SPARC64_INSN_TE, SPARC64_INSN_TE_IMM
+ , SPARC64_INSN_BG, SPARC64_INSN_TG, SPARC64_INSN_TG_IMM, SPARC64_INSN_BLE
+ , SPARC64_INSN_TLE, SPARC64_INSN_TLE_IMM, SPARC64_INSN_BGE, SPARC64_INSN_TGE
+ , SPARC64_INSN_TGE_IMM, SPARC64_INSN_BL, SPARC64_INSN_TL, SPARC64_INSN_TL_IMM
+ , SPARC64_INSN_BGU, SPARC64_INSN_TGU, SPARC64_INSN_TGU_IMM, SPARC64_INSN_BLEU
+ , SPARC64_INSN_TLEU, SPARC64_INSN_TLEU_IMM, SPARC64_INSN_BCC, SPARC64_INSN_TCC
+ , SPARC64_INSN_TCC_IMM, SPARC64_INSN_BCS, SPARC64_INSN_TCS, SPARC64_INSN_TCS_IMM
+ , SPARC64_INSN_BPOS, SPARC64_INSN_TPOS, SPARC64_INSN_TPOS_IMM, SPARC64_INSN_BNEG
+ , SPARC64_INSN_TNEG, SPARC64_INSN_TNEG_IMM, SPARC64_INSN_BVC, SPARC64_INSN_TVC
+ , SPARC64_INSN_TVC_IMM, SPARC64_INSN_BVS, SPARC64_INSN_TVS, SPARC64_INSN_TVS_IMM
+ , SPARC64_INSN_LDSTUB_REG_REG, SPARC64_INSN_LDSTUB_REG_IMM, SPARC64_INSN_LDSTUB_REG_REG_ASI, SPARC64_INSN_SWAP_REG_REG
+ , SPARC64_INSN_SWAP_REG_IMM, SPARC64_INSN_SWAP_REG_REG_ASI, SPARC64_INSN_MAX
+} SPARC64_INSN_TYPE;
+
+#if ! WITH_SEM_SWITCH_FULL
+#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,fn);
+#else
+#define SEMFULL(fn)
+#endif
+
+#if ! WITH_SEM_SWITCH_FAST
+#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_semf_,fn);
+#else
+#define SEMFAST(fn)
+#endif
+
+#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
+
+/* The function version of the before/after handlers is always needed,
+   so we always want the SEMFULL declaration of them.  */
+extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_before);
+extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_after);
+
+SEM (x_invalid)
+SEM (x_after)
+SEM (x_before)
+SEM (x_cti_chain)
+SEM (x_chain)
+SEM (x_begin)
+SEM (beqz)
+SEM (bgez)
+SEM (bgtz)
+SEM (blez)
+SEM (bltz)
+SEM (bnez)
+SEM (bpcc_ba)
+SEM (bpcc_bn)
+SEM (bpcc_bne)
+SEM (bpcc_be)
+SEM (bpcc_bg)
+SEM (bpcc_ble)
+SEM (bpcc_bge)
+SEM (bpcc_bl)
+SEM (bpcc_bgu)
+SEM (bpcc_bleu)
+SEM (bpcc_bcc)
+SEM (bpcc_bcs)
+SEM (bpcc_bpos)
+SEM (bpcc_bneg)
+SEM (bpcc_bvc)
+SEM (bpcc_bvs)
+SEM (done)
+SEM (retry)
+SEM (flush)
+SEM (flush_imm)
+SEM (flushw)
+SEM (impdep1)
+SEM (impdep2)
+SEM (membar)
+SEM (mova_icc_icc)
+SEM (mova_imm_icc_icc)
+SEM (mova_xcc_xcc)
+SEM (mova_imm_xcc_xcc)
+SEM (movn_icc_icc)
+SEM (movn_imm_icc_icc)
+SEM (movn_xcc_xcc)
+SEM (movn_imm_xcc_xcc)
+SEM (movne_icc_icc)
+SEM (movne_imm_icc_icc)
+SEM (movne_xcc_xcc)
+SEM (movne_imm_xcc_xcc)
+SEM (move_icc_icc)
+SEM (move_imm_icc_icc)
+SEM (move_xcc_xcc)
+SEM (move_imm_xcc_xcc)
+SEM (movg_icc_icc)
+SEM (movg_imm_icc_icc)
+SEM (movg_xcc_xcc)
+SEM (movg_imm_xcc_xcc)
+SEM (movle_icc_icc)
+SEM (movle_imm_icc_icc)
+SEM (movle_xcc_xcc)
+SEM (movle_imm_xcc_xcc)
+SEM (movge_icc_icc)
+SEM (movge_imm_icc_icc)
+SEM (movge_xcc_xcc)
+SEM (movge_imm_xcc_xcc)
+SEM (movl_icc_icc)
+SEM (movl_imm_icc_icc)
+SEM (movl_xcc_xcc)
+SEM (movl_imm_xcc_xcc)
+SEM (movgu_icc_icc)
+SEM (movgu_imm_icc_icc)
+SEM (movgu_xcc_xcc)
+SEM (movgu_imm_xcc_xcc)
+SEM (movleu_icc_icc)
+SEM (movleu_imm_icc_icc)
+SEM (movleu_xcc_xcc)
+SEM (movleu_imm_xcc_xcc)
+SEM (movcc_icc_icc)
+SEM (movcc_imm_icc_icc)
+SEM (movcc_xcc_xcc)
+SEM (movcc_imm_xcc_xcc)
+SEM (movcs_icc_icc)
+SEM (movcs_imm_icc_icc)
+SEM (movcs_xcc_xcc)
+SEM (movcs_imm_xcc_xcc)
+SEM (movpos_icc_icc)
+SEM (movpos_imm_icc_icc)
+SEM (movpos_xcc_xcc)
+SEM (movpos_imm_xcc_xcc)
+SEM (movneg_icc_icc)
+SEM (movneg_imm_icc_icc)
+SEM (movneg_xcc_xcc)
+SEM (movneg_imm_xcc_xcc)
+SEM (movvc_icc_icc)
+SEM (movvc_imm_icc_icc)
+SEM (movvc_xcc_xcc)
+SEM (movvc_imm_xcc_xcc)
+SEM (movvs_icc_icc)
+SEM (movvs_imm_icc_icc)
+SEM (movvs_xcc_xcc)
+SEM (movvs_imm_xcc_xcc)
+SEM (ldsb_reg_reg)
+SEM (ldsb_reg_imm)
+SEM (ldsb_reg_reg_asi)
+SEM (ldub_reg_reg)
+SEM (ldub_reg_imm)
+SEM (ldub_reg_reg_asi)
+SEM (ldsh_reg_reg)
+SEM (ldsh_reg_imm)
+SEM (ldsh_reg_reg_asi)
+SEM (lduh_reg_reg)
+SEM (lduh_reg_imm)
+SEM (lduh_reg_reg_asi)
+SEM (ldsw_reg_reg)
+SEM (ldsw_reg_imm)
+SEM (ldsw_reg_reg_asi)
+SEM (lduw_reg_reg)
+SEM (lduw_reg_imm)
+SEM (lduw_reg_reg_asi)
+SEM (ldx_reg_reg)
+SEM (ldx_reg_imm)
+SEM (ldx_reg_reg_asi)
+SEM (ldd_reg_reg)
+SEM (ldd_reg_imm)
+SEM (ldd_reg_reg_asi)
+SEM (stb_reg_reg)
+SEM (stb_reg_imm)
+SEM (stb_reg_reg_asi)
+SEM (sth_reg_reg)
+SEM (sth_reg_imm)
+SEM (sth_reg_reg_asi)
+SEM (st_reg_reg)
+SEM (st_reg_imm)
+SEM (st_reg_reg_asi)
+SEM (stx_reg_reg)
+SEM (stx_reg_imm)
+SEM (stx_reg_reg_asi)
+SEM (std_reg_reg)
+SEM (std_reg_imm)
+SEM (std_reg_reg_asi)
+SEM (fp_ld_reg_reg)
+SEM (fp_ld_reg_imm)
+SEM (fp_ld_reg_reg_asi)
+SEM (sethi)
+SEM (add)
+SEM (add_imm)
+SEM (sub)
+SEM (sub_imm)
+SEM (addcc)
+SEM (addcc_imm)
+SEM (subcc)
+SEM (subcc_imm)
+SEM (addc)
+SEM (addc_imm)
+SEM (subc)
+SEM (subc_imm)
+SEM (addccc)
+SEM (addccc_imm)
+SEM (subccc)
+SEM (subccc_imm)
+SEM (and)
+SEM (and_imm)
+SEM (andcc)
+SEM (andcc_imm)
+SEM (or)
+SEM (or_imm)
+SEM (orcc)
+SEM (orcc_imm)
+SEM (xor)
+SEM (xor_imm)
+SEM (xorcc)
+SEM (xorcc_imm)
+SEM (andn)
+SEM (andn_imm)
+SEM (andncc)
+SEM (andncc_imm)
+SEM (orn)
+SEM (orn_imm)
+SEM (orncc)
+SEM (orncc_imm)
+SEM (xnor)
+SEM (xnor_imm)
+SEM (xnorcc)
+SEM (xnorcc_imm)
+SEM (sll)
+SEM (sll_imm)
+SEM (srl)
+SEM (srl_imm)
+SEM (sra)
+SEM (sra_imm)
+SEM (smul)
+SEM (smul_imm)
+SEM (smul_cc)
+SEM (smul_cc_imm)
+SEM (umul)
+SEM (umul_imm)
+SEM (umul_cc)
+SEM (umul_cc_imm)
+SEM (mulscc)
+SEM (save)
+SEM (save_imm)
+SEM (restore)
+SEM (restore_imm)
+SEM (rett)
+SEM (rett_imm)
+SEM (unimp)
+SEM (call)
+SEM (jmpl)
+SEM (jmpl_imm)
+SEM (ba)
+SEM (ta)
+SEM (ta_imm)
+SEM (bn)
+SEM (tn)
+SEM (tn_imm)
+SEM (bne)
+SEM (tne)
+SEM (tne_imm)
+SEM (be)
+SEM (te)
+SEM (te_imm)
+SEM (bg)
+SEM (tg)
+SEM (tg_imm)
+SEM (ble)
+SEM (tle)
+SEM (tle_imm)
+SEM (bge)
+SEM (tge)
+SEM (tge_imm)
+SEM (bl)
+SEM (tl)
+SEM (tl_imm)
+SEM (bgu)
+SEM (tgu)
+SEM (tgu_imm)
+SEM (bleu)
+SEM (tleu)
+SEM (tleu_imm)
+SEM (bcc)
+SEM (tcc)
+SEM (tcc_imm)
+SEM (bcs)
+SEM (tcs)
+SEM (tcs_imm)
+SEM (bpos)
+SEM (tpos)
+SEM (tpos_imm)
+SEM (bneg)
+SEM (tneg)
+SEM (tneg_imm)
+SEM (bvc)
+SEM (tvc)
+SEM (tvc_imm)
+SEM (bvs)
+SEM (tvs)
+SEM (tvs_imm)
+SEM (ldstub_reg_reg)
+SEM (ldstub_reg_imm)
+SEM (ldstub_reg_reg_asi)
+SEM (swap_reg_reg)
+SEM (swap_reg_imm)
+SEM (swap_reg_reg_asi)
+
+#undef SEMFULL
+#undef SEMFAST
+#undef SEM
+
+/* Function unit handlers (user written).  */
+
+extern int sparc64_model_sparc64_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void sparc64_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void sparc64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* SPARC64_DECODE_H */

sim/sparc/mloop64.in

@@ -0,0 +1,133 @@
+# Simulator main loop for sparc64. -*- C -*-
+# Copyright (C) 1999 Cygnus Solutions.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE void
+execute (SIM_CPU *current_cpu, SCACHE *sc)
+{
+  ARGBUF *abuf = &sc->argbuf;
+  IADDR pc = GET_H_PC ();
+  USI insn = GETIMEMUSI (current_cpu, pc);
+  int fast_p = STATE_RUN_FAST_P (CPU_STATE (current_cpu));
+
+  if (fast_p)
+    {
+      const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
+
+      @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+      (*id->sem_full) (current_cpu, sc, insn);
+    }
+  else
+    {
+      const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
+      const CGEN_INSN *idata = id->idata;
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+
+      @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+
+      /* FIXME: call x-before */
+      if (ARGBUF_PROFILE_P (abuf))
+        PROFILE_COUNT_INSN (current_cpu, pc, id->num);
+      /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
+      if (PROFILE_MODEL_P (current_cpu)
+          && ARGBUF_PROFILE_P (abuf))
+        @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+      TRACE_INSN_INIT (current_cpu, abuf, 1);
+      TRACE_INSN (current_cpu, idata, abuf, pc);
+
+      (*id->sem_full) (current_cpu, sc, insn);
+
+      /* FIXME: call x-after */
+      if (PROFILE_MODEL_P (current_cpu)
+          && ARGBUF_PROFILE_P (abuf))
+        {
+          int cycles;
+
+          cycles = (*id->timing->model_fn) (current_cpu, sc);
+          @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+        }
+      TRACE_INSN_FINI (current_cpu, abuf, 1);
+    }
+}
+
+static INLINE void
+do_annul (SIM_CPU *current_cpu)
+{
+  IADDR npc = GET_H_NPC ();
+
+  /* ??? log profiling data */
+  /* ??? anything else */
+
+  SET_H_PC (npc);
+  SET_H_NPC (npc + 4);
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xfull-exec-simple)
+
+# Inputs: current_cpu, sc, FAST_P
+# Outputs: none, instruction is fetched and executed
+# Recorded PC is updated after every insn.
+# ??? Use of `sc' is a bit of a hack as we don't use the scache.
+# We do however use ARGBUF so for consistency with the other engine flavours
+# sc is used.
+
+cat <<EOF
+
+{
+  if (GET_H_ANNUL_P ())
+    {
+      do_annul (current_cpu);
+      SET_H_ANNUL_P (0);
+    }
+  else
+    {
+      execute (current_cpu, sc);
+    }
+}
+
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac

sim/sparc/regs64.h

@@ -0,0 +1,74 @@
+/* sparc64 register definitions
+   Copyright (C) 1999 Cygnus Solutions.  */
+
+#ifndef REG64_H
+#define REG64_H
+
+/* The PSR is a hodge-podge of various things.
+   ??? The final organization of this is wip.  */
+
+extern USI sparc32_get_h_psr_handler (SIM_CPU *);
+extern void sparc32_set_h_psr_handler (SIM_CPU *, USI);
+#define GET_H_PSR()    sparc32_get_h_psr_handler (current_cpu)
+#define SET_H_PSR(val) sparc32_set_h_psr_handler (current_cpu, (val))
+
+/* The y reg is a virtual reg as it's actually one of the asr regs.
+   ??? To be replaced in time with get/set specs.  */
+#if 0
+#define sparc32_h_y_get(cpu)     (CPU_CGEN_HW (cpu)->h_asr[0])
+#define sparc32_h_y_set(cpu,val) (CPU_CGEN_HW (cpu)->h_asr[0] = (val))
+#endif
+#define GET_H_Y()       (CPU (h_asr) [0])
+#define SET_H_Y(newval) do { CPU (h_asr) [0] = (newval); } while (0)
+
+/* The Trap Base Register.  */
+#define GET_H_TBR() CPU (h_tbr)
+#define SET_H_TBR(newval) \
+  do { \
+    CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000); \
+  } while (0)
+
+/* sparc32 register window stuff.  */
+
+/* Handle gets/sets of h-cwp.
+   This handles swapping out the current set of window registers
+   and swapping in the new.  How the "swapping" is done depends on the
+   register window implementation of the day.  */
+void sparc32_set_h_cwp_handler (SIM_CPU *, int);
+#define GET_H_CWP() CPU (h_cwp)
+#define SET_H_CWP(newval) sparc32_set_h_cwp_handler (current_cpu, (newval))
+
+/* WIM accessors.  */
+/* ??? Yes, mask computation assumes nwindows < 32.  */
+#define GET_H_WIM()       (CPU (h_wim) & ((1 << GET_NWINDOWS ()) - 1))
+#define SET_H_WIM(newval) (CPU (h_wim) = (newval))
+
+/* Return non-zero if window WIN is valid in WIM.  */
+#define WINDOW_VALID_P(win, wim) (((wim) & (1 << (win))) == 0)
+
+void sparc32_alloc_regwins (SIM_CPU *, int);
+void sparc32_free_regwins (SIM_CPU *);
+void sparc32_swapout_regwin (SIM_CPU *, int);
+void sparc32_swapin_regwin (SIM_CPU *, int);
+
+void sparc32_load_regwin (SIM_CPU *, IADDR pc_, int win_);
+void sparc32_flush_regwin (SIM_CPU *, IADDR pc_, int win_, int no_errors_p_);
+void sparc32_flush_regwins (SIM_CPU *, IADDR pc_, int no_errors_p_);
+
+void sparc32_save_regwin (SIM_CPU *);
+void sparc32_restore_regwin (SIM_CPU *);
+
+/* Integer register access macros.
+   Provides an interface between the cpu description and the register window
+   implementation of the day.  To be solidified in time.  */
+#define GET_H_GR(r) (current_cpu->current_regs[r])
+
+/* ??? The r != 0 test may not be necessary as sufficient numbers of dni
+   entries can prevent this from occuring (I think).  Even then though doing
+   this makes things more robust, and a lot of dni's would be needed.
+   ??? The other way to handle %g0 is to always reset it for each insn
+   [perhaps optimized to only do so when necessary].  */
+#define SET_H_GR(r, val) \
+  ((r) != 0 ? (current_cpu->current_regs[r] = (val)) : 0)
+
+#endif /* REG64_H */

sim/sparc/sparc-opc.h

@@ -0,0 +1,175 @@
+/* Instruction opcode header for sparc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1999 Cygnus Solutions, Inc.
+
+This file is part of the Cygnus Simulators.
+
+
+*/
+
+#ifndef SPARC_OPC_H
+#define SPARC_OPC_H
+
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 256
+#undef CGEN_DIS_HASH
+extern const unsigned int sparc_cgen_opcode_bits[];
+#define CGEN_DIS_HASH(buffer, insn) \
+((((insn) >> 24) & 0xc0) \
+ | (((insn) & sparc_cgen_opcode_bits[((insn) >> 30) & 3]) >> 19))
+
+/* -- */
+/* Enum declaration for sparc instruction types.  */
+typedef enum cgen_insn_type {
+  SPARC_INSN_INVALID, SPARC_INSN_RD_ASR, SPARC_INSN_WR_ASR, SPARC_INSN_WR_ASR_IMM
+ , SPARC_INSN_RD_PSR, SPARC_INSN_WR_PSR, SPARC_INSN_WR_PSR_IMM, SPARC_INSN_RD_WIM
+ , SPARC_INSN_WR_WIM, SPARC_INSN_WR_WIM_IMM, SPARC_INSN_RD_TBR, SPARC_INSN_WR_TBR
+ , SPARC_INSN_WR_TBR_IMM, SPARC_INSN_BEQZ, SPARC_INSN_BGEZ, SPARC_INSN_BGTZ
+ , SPARC_INSN_BLEZ, SPARC_INSN_BLTZ, SPARC_INSN_BNEZ, SPARC_INSN_BPCC_BA
+ , SPARC_INSN_BPCC_BN, SPARC_INSN_BPCC_BNE, SPARC_INSN_BPCC_BE, SPARC_INSN_BPCC_BG
+ , SPARC_INSN_BPCC_BLE, SPARC_INSN_BPCC_BGE, SPARC_INSN_BPCC_BL, SPARC_INSN_BPCC_BGU
+ , SPARC_INSN_BPCC_BLEU, SPARC_INSN_BPCC_BCC, SPARC_INSN_BPCC_BCS, SPARC_INSN_BPCC_BPOS
+ , SPARC_INSN_BPCC_BNEG, SPARC_INSN_BPCC_BVC, SPARC_INSN_BPCC_BVS, SPARC_INSN_DONE
+ , SPARC_INSN_RETRY, SPARC_INSN_FLUSH, SPARC_INSN_FLUSH_IMM, SPARC_INSN_FLUSHW
+ , SPARC_INSN_IMPDEP1, SPARC_INSN_IMPDEP2, SPARC_INSN_MEMBAR, SPARC_INSN_MOVA_ICC_ICC
+ , SPARC_INSN_MOVA_IMM_ICC_ICC, SPARC_INSN_MOVA_XCC_XCC, SPARC_INSN_MOVA_IMM_XCC_XCC, SPARC_INSN_MOVN_ICC_ICC
+ , SPARC_INSN_MOVN_IMM_ICC_ICC, SPARC_INSN_MOVN_XCC_XCC, SPARC_INSN_MOVN_IMM_XCC_XCC, SPARC_INSN_MOVNE_ICC_ICC
+ , SPARC_INSN_MOVNE_IMM_ICC_ICC, SPARC_INSN_MOVNE_XCC_XCC, SPARC_INSN_MOVNE_IMM_XCC_XCC, SPARC_INSN_MOVE_ICC_ICC
+ , SPARC_INSN_MOVE_IMM_ICC_ICC, SPARC_INSN_MOVE_XCC_XCC, SPARC_INSN_MOVE_IMM_XCC_XCC, SPARC_INSN_MOVG_ICC_ICC
+ , SPARC_INSN_MOVG_IMM_ICC_ICC, SPARC_INSN_MOVG_XCC_XCC, SPARC_INSN_MOVG_IMM_XCC_XCC, SPARC_INSN_MOVLE_ICC_ICC
+ , SPARC_INSN_MOVLE_IMM_ICC_ICC, SPARC_INSN_MOVLE_XCC_XCC, SPARC_INSN_MOVLE_IMM_XCC_XCC, SPARC_INSN_MOVGE_ICC_ICC
+ , SPARC_INSN_MOVGE_IMM_ICC_ICC, SPARC_INSN_MOVGE_XCC_XCC, SPARC_INSN_MOVGE_IMM_XCC_XCC, SPARC_INSN_MOVL_ICC_ICC
+ , SPARC_INSN_MOVL_IMM_ICC_ICC, SPARC_INSN_MOVL_XCC_XCC, SPARC_INSN_MOVL_IMM_XCC_XCC, SPARC_INSN_MOVGU_ICC_ICC
+ , SPARC_INSN_MOVGU_IMM_ICC_ICC, SPARC_INSN_MOVGU_XCC_XCC, SPARC_INSN_MOVGU_IMM_XCC_XCC, SPARC_INSN_MOVLEU_ICC_ICC
+ , SPARC_INSN_MOVLEU_IMM_ICC_ICC, SPARC_INSN_MOVLEU_XCC_XCC, SPARC_INSN_MOVLEU_IMM_XCC_XCC, SPARC_INSN_MOVCC_ICC_ICC
+ , SPARC_INSN_MOVCC_IMM_ICC_ICC, SPARC_INSN_MOVCC_XCC_XCC, SPARC_INSN_MOVCC_IMM_XCC_XCC, SPARC_INSN_MOVCS_ICC_ICC
+ , SPARC_INSN_MOVCS_IMM_ICC_ICC, SPARC_INSN_MOVCS_XCC_XCC, SPARC_INSN_MOVCS_IMM_XCC_XCC, SPARC_INSN_MOVPOS_ICC_ICC
+ , SPARC_INSN_MOVPOS_IMM_ICC_ICC, SPARC_INSN_MOVPOS_XCC_XCC, SPARC_INSN_MOVPOS_IMM_XCC_XCC, SPARC_INSN_MOVNEG_ICC_ICC
+ , SPARC_INSN_MOVNEG_IMM_ICC_ICC, SPARC_INSN_MOVNEG_XCC_XCC, SPARC_INSN_MOVNEG_IMM_XCC_XCC, SPARC_INSN_MOVVC_ICC_ICC
+ , SPARC_INSN_MOVVC_IMM_ICC_ICC, SPARC_INSN_MOVVC_XCC_XCC, SPARC_INSN_MOVVC_IMM_XCC_XCC, SPARC_INSN_MOVVS_ICC_ICC
+ , SPARC_INSN_MOVVS_IMM_ICC_ICC, SPARC_INSN_MOVVS_XCC_XCC, SPARC_INSN_MOVVS_IMM_XCC_XCC, SPARC_INSN_LDSB_REG_REG
+ , SPARC_INSN_LDSB_REG_IMM, SPARC_INSN_LDSB_REG_REG_ASI, SPARC_INSN_LDUB_REG_REG, SPARC_INSN_LDUB_REG_IMM
+ , SPARC_INSN_LDUB_REG_REG_ASI, SPARC_INSN_LDSH_REG_REG, SPARC_INSN_LDSH_REG_IMM, SPARC_INSN_LDSH_REG_REG_ASI
+ , SPARC_INSN_LDUH_REG_REG, SPARC_INSN_LDUH_REG_IMM, SPARC_INSN_LDUH_REG_REG_ASI, SPARC_INSN_LDSW_REG_REG
+ , SPARC_INSN_LDSW_REG_IMM, SPARC_INSN_LDSW_REG_REG_ASI, SPARC_INSN_LDUW_REG_REG, SPARC_INSN_LDUW_REG_IMM
+ , SPARC_INSN_LDUW_REG_REG_ASI, SPARC_INSN_LDX_REG_REG, SPARC_INSN_LDX_REG_IMM, SPARC_INSN_LDX_REG_REG_ASI
+ , SPARC_INSN_LD_REG_REG, SPARC_INSN_LD_REG_IMM, SPARC_INSN_LD_REG_REG_ASI, SPARC_INSN_LDD_REG_REG
+ , SPARC_INSN_LDD_REG_IMM, SPARC_INSN_LDD_REG_REG_ASI, SPARC_INSN_STB_REG_REG, SPARC_INSN_STB_REG_IMM
+ , SPARC_INSN_STB_REG_REG_ASI, SPARC_INSN_STH_REG_REG, SPARC_INSN_STH_REG_IMM, SPARC_INSN_STH_REG_REG_ASI
+ , SPARC_INSN_ST_REG_REG, SPARC_INSN_ST_REG_IMM, SPARC_INSN_ST_REG_REG_ASI, SPARC_INSN_STX_REG_REG
+ , SPARC_INSN_STX_REG_IMM, SPARC_INSN_STX_REG_REG_ASI, SPARC_INSN_STD_REG_REG, SPARC_INSN_STD_REG_IMM
+ , SPARC_INSN_STD_REG_REG_ASI, SPARC_INSN_FP_LD_REG_REG, SPARC_INSN_FP_LD_REG_IMM, SPARC_INSN_FP_LD_REG_REG_ASI
+ , SPARC_INSN_SETHI, SPARC_INSN_ADD, SPARC_INSN_ADD_IMM, SPARC_INSN_SUB
+ , SPARC_INSN_SUB_IMM, SPARC_INSN_ADDCC, SPARC_INSN_ADDCC_IMM, SPARC_INSN_SUBCC
+ , SPARC_INSN_SUBCC_IMM, SPARC_INSN_ADDX, SPARC_INSN_ADDX_IMM, SPARC_INSN_SUBX
+ , SPARC_INSN_SUBX_IMM, SPARC_INSN_ADDXCC, SPARC_INSN_ADDXCC_IMM, SPARC_INSN_SUBXCC
+ , SPARC_INSN_SUBXCC_IMM, SPARC_INSN_ADDC, SPARC_INSN_ADDC_IMM, SPARC_INSN_SUBC
+ , SPARC_INSN_SUBC_IMM, SPARC_INSN_ADDCCC, SPARC_INSN_ADDCCC_IMM, SPARC_INSN_SUBCCC
+ , SPARC_INSN_SUBCCC_IMM, SPARC_INSN_AND, SPARC_INSN_AND_IMM, SPARC_INSN_ANDCC
+ , SPARC_INSN_ANDCC_IMM, SPARC_INSN_OR, SPARC_INSN_OR_IMM, SPARC_INSN_ORCC
+ , SPARC_INSN_ORCC_IMM, SPARC_INSN_XOR, SPARC_INSN_XOR_IMM, SPARC_INSN_XORCC
+ , SPARC_INSN_XORCC_IMM, SPARC_INSN_ANDN, SPARC_INSN_ANDN_IMM, SPARC_INSN_ANDNCC
+ , SPARC_INSN_ANDNCC_IMM, SPARC_INSN_ORN, SPARC_INSN_ORN_IMM, SPARC_INSN_ORNCC
+ , SPARC_INSN_ORNCC_IMM, SPARC_INSN_XNOR, SPARC_INSN_XNOR_IMM, SPARC_INSN_XNORCC
+ , SPARC_INSN_XNORCC_IMM, SPARC_INSN_SLL, SPARC_INSN_SLL_IMM, SPARC_INSN_SRL
+ , SPARC_INSN_SRL_IMM, SPARC_INSN_SRA, SPARC_INSN_SRA_IMM, SPARC_INSN_SMUL
+ , SPARC_INSN_SMUL_IMM, SPARC_INSN_SMUL_CC, SPARC_INSN_SMUL_CC_IMM, SPARC_INSN_UMUL
+ , SPARC_INSN_UMUL_IMM, SPARC_INSN_UMUL_CC, SPARC_INSN_UMUL_CC_IMM, SPARC_INSN_SDIV
+ , SPARC_INSN_SDIV_IMM, SPARC_INSN_SDIV_CC, SPARC_INSN_SDIV_CC_IMM, SPARC_INSN_UDIV
+ , SPARC_INSN_UDIV_IMM, SPARC_INSN_UDIV_CC, SPARC_INSN_UDIV_CC_IMM, SPARC_INSN_MULSCC
+ , SPARC_INSN_SAVE, SPARC_INSN_SAVE_IMM, SPARC_INSN_RESTORE, SPARC_INSN_RESTORE_IMM
+ , SPARC_INSN_RETT, SPARC_INSN_RETT_IMM, SPARC_INSN_UNIMP, SPARC_INSN_CALL
+ , SPARC_INSN_JMPL, SPARC_INSN_JMPL_IMM, SPARC_INSN_BA, SPARC_INSN_TA
+ , SPARC_INSN_TA_IMM, SPARC_INSN_BN, SPARC_INSN_TN, SPARC_INSN_TN_IMM
+ , SPARC_INSN_BNE, SPARC_INSN_TNE, SPARC_INSN_TNE_IMM, SPARC_INSN_BE
+ , SPARC_INSN_TE, SPARC_INSN_TE_IMM, SPARC_INSN_BG, SPARC_INSN_TG
+ , SPARC_INSN_TG_IMM, SPARC_INSN_BLE, SPARC_INSN_TLE, SPARC_INSN_TLE_IMM
+ , SPARC_INSN_BGE, SPARC_INSN_TGE, SPARC_INSN_TGE_IMM, SPARC_INSN_BL
+ , SPARC_INSN_TL, SPARC_INSN_TL_IMM, SPARC_INSN_BGU, SPARC_INSN_TGU
+ , SPARC_INSN_TGU_IMM, SPARC_INSN_BLEU, SPARC_INSN_TLEU, SPARC_INSN_TLEU_IMM
+ , SPARC_INSN_BCC, SPARC_INSN_TCC, SPARC_INSN_TCC_IMM, SPARC_INSN_BCS
+ , SPARC_INSN_TCS, SPARC_INSN_TCS_IMM, SPARC_INSN_BPOS, SPARC_INSN_TPOS
+ , SPARC_INSN_TPOS_IMM, SPARC_INSN_BNEG, SPARC_INSN_TNEG, SPARC_INSN_TNEG_IMM
+ , SPARC_INSN_BVC, SPARC_INSN_TVC, SPARC_INSN_TVC_IMM, SPARC_INSN_BVS
+ , SPARC_INSN_TVS, SPARC_INSN_TVS_IMM, SPARC_INSN_LDSTUB_REG_REG, SPARC_INSN_LDSTUB_REG_IMM
+ , SPARC_INSN_LDSTUB_REG_REG_ASI, SPARC_INSN_SWAP_REG_REG, SPARC_INSN_SWAP_REG_IMM, SPARC_INSN_SWAP_REG_REG_ASI
+ , SPARC_INSN_MAX
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder.  */
+#define CGEN_INSN_INVALID SPARC_INSN_INVALID
+
+/* Total number of insns in table.  */
+#define MAX_INSNS ((int) SPARC_INSN_MAX)
+
+/* This struct records data prior to insertion or after extraction.  */
+struct cgen_fields
+{
+  int length;
+  long f_nil;
+  long f_op;
+  long f_op2;
+  long f_op3;
+  long f_rs1;
+  long f_rs2;
+  long f_rd;
+  long f_rd_res;
+  long f_i;
+  long f_simm13;
+  long f_imm22;
+  long f_hi22;
+  long f_a;
+  long f_fmt2_cond;
+  long f_disp22;
+  long f_disp30;
+  long f_opf;
+  long f_res_12_8;
+  long f_simm10;
+  long f_fmt2_cc;
+  long f_fmt3_cc;
+  long f_x;
+  long f_shcnt32;
+  long f_fcn;
+  long f_imm_asi;
+  long f_asi;
+  long f_res_asi;
+  long f_fmt4_cc;
+  long f_soft_trap;
+  long f_opf_low5;
+  long f_opf_low6;
+  long f_opf_cc;
+  long f_fmt2_cc1;
+  long f_fmt2_cc0;
+  long f_p;
+  long f_fmt2_rcond;
+  long f_disp19;
+  long f_fmt3_rcond;
+  long f_shcnt64;
+  long f_fmt4_cond;
+  long f_fmt4_ccx_hi;
+  long f_fmt4_ccx_lo;
+  long f_fmt4_rcond;
+  long f_fmt4_cc2;
+  long f_fmt4_cc1_0;
+  long f_fmt4_res10_6;
+  long f_disp16_hi;
+  long f_disp16_lo;
+  long f_disp16;
+  long f_res_18_19;
+  long f_bpr_res28_1;
+  long f_impdep5;
+  long f_impdep19;
+  long f_membar_res12_6;
+  long f_cmask;
+  long f_mmask;
+  long f_membarmask;
+  long f_simm11;
+};
+
+
+
+#endif /* SPARC_OPC_H */

sim/sparc/trap64.c

@@ -0,0 +1,308 @@
+/* sparc64 trap support
+   Copyright (C) 1999 Cygnus Solutions.  */
+
+#define WANT_CPU sparc64
+#define WANT_CPU_SPARC64
+
+#include "sim-main.h"
+#include "targ-vals.h"
+
+/* Indicate a window overflow has occured.  */
+
+void
+sparc64_window_overflow (SIM_CPU *cpu, IADDR pc)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    sparc64_hw_trap (cpu, pc, TRAP32_WINDOW_OVERFLOW);
+  else
+    sparc64_hw_trap (cpu, pc, TRAP32_SIM_SPILL);
+}
+
+/* Indicate a window underflow has occured.  */
+
+void
+sparc64_window_underflow (SIM_CPU *cpu, IADDR pc)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    sparc64_hw_trap (cpu, pc, TRAP32_WINDOW_UNDERFLOW);
+  else
+    sparc64_hw_trap (cpu, pc, TRAP32_SIM_FILL);
+}
+
+void
+sparc64_invalid_insn (SIM_CPU * cpu, IADDR pc)
+{
+  sparc64_hw_trap (cpu, pc, TRAP32_ILLEGAL_INSN);
+}
+
+void
+sparc64_core_signal (SIM_DESC sd, SIM_CPU *cpu, sim_cia pc,
+		     unsigned int map, int nr_bytes, address_word addr,
+		     transfer_type transfer, sim_core_signals sig)
+{
+  sparc64_hw_trap (cpu, pc,
+		   map == exec_map
+		   ? TRAP32_INSTRUCTION_ACCESS
+		   : TRAP32_DATA_ACCESS);
+}
+
+/* Handle hardware generated traps when --environment=operating.  */
+
+static void
+sparc64_hw_trap_oper (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  IADDR new_pc = (GET_H_TBR () & 0xfffff000) | (trap << 4);
+  USI psr = GET_H_PSR ();
+
+  psr &= ~PSR_ET;
+  psr = (psr & ~PSR_PS) | (psr & PSR_S ? PSR_PS : 0);
+  psr |= PSR_S;
+  psr = (psr & ~PSR_CWP) | NEXT_WIN (psr & PSR_CWP);
+  SET_H_PSR (psr);
+  SET_H_GR (H_GR__L1, GET_H_PC ());
+  SET_H_GR (H_GR__L2, GET_H_NPC ());
+
+  SET_H_ANNUL_P (0);
+
+  /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either
+     (??? doesn't *have* to be this way though).
+     Therefore we can't use SET_H_TBR here.  */
+  CPU (h_tbr) = new_pc;
+  SET_H_PC (new_pc);
+  SET_H_NPC (new_pc + 4);
+
+  sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, new_pc);
+}
+
+/* Handle hardware generated traps when --environment=user.  */
+
+static void
+sparc64_hw_trap_user (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+  switch (trap)
+    {
+    case TRAP32_SIM_SPILL :
+      /* The CWP-1 window is invalid.  */
+      {
+	int win = NEXT_WIN (GET_H_CWP ());
+	int next_win = NEXT_WIN (win);
+	int nwindows = GET_NWINDOWS ();
+	unsigned int mask = (1 << nwindows) - 1;
+	unsigned int wim = GET_H_WIM ();
+
+	/* There's no need to flush `current_regs' here, `next_win' can't
+	   refer to it.  */
+	sparc64_flush_regwin (current_cpu, pc, next_win, 0 /* error ok (?) */);
+	/* Rotate WIM right one.  */
+	wim = ((wim & mask) >> 1) | (wim << (nwindows - 1));
+	SET_H_WIM (wim & mask);
+	return;
+      }
+
+    case TRAP32_SIM_FILL :
+      /* The CWP+1 window is invalid.  */
+      {
+	int win = PREV_WIN (GET_H_CWP ());
+	int nwindows = GET_NWINDOWS ();
+	unsigned int mask = (1 << nwindows) - 1;
+	unsigned int wim = GET_H_WIM ();
+
+	/* Load caller's caller's window.
+	   There's no need to flush `current_regs' as `win' can't
+	   refer to it.  */
+	sparc64_load_regwin (current_cpu, pc, win);
+	/* Rotate WIM left one.  */
+	wim = (wim << 1) | ((wim & mask) >> (nwindows - 1));
+	SET_H_WIM (wim & mask);
+	return;
+      }
+    }
+
+  sim_io_eprintf (sd, "Received trap %d\n", trap);
+  sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGABRT);
+}
+
+/* Handle hardware generated traps.  */
+
+void
+sparc64_hw_trap (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    sparc64_hw_trap_oper (current_cpu, pc, trap);
+  else
+    sparc64_hw_trap_user (current_cpu, pc, trap);
+}
+
+/* Handle the trap insn when --environment=operating.  */
+
+static IADDR
+sparc64_sw_trap_oper (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  int trap = 128 + ((rs1 + rs2_simm13) & 127);
+  IADDR new_pc;
+
+  /* ??? Quick hack to have breakpoints work with gdb+"target sim" until
+     other things are working.  */
+  if (trap == TRAP32_BREAKPOINT)
+    sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+
+  if (! GET_H_ET ())
+    {
+      /* Enter error mode.
+	 ??? wip, need to remain compatible with erc32 for now.  */
+      int i0 = GET_H_GR (H_GR__I0);
+      int i1 = GET_H_GR (H_GR__I1);
+
+      if (i1 == LIBGLOSS_EXIT_MAGIC)
+	sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, i0);
+      else
+	{
+	  sim_io_eprintf (sd, "Unexpected program termination, pc=0x%x\n",
+			  (int) pc);
+	  sim_engine_halt (sd, current_cpu, NULL, pc,
+			   sim_signalled, SIM_SIGABRT);
+	}
+    }
+
+  SET_H_ET (0);
+  SET_H_PSR ((GET_H_PSR () & ~(PSR_CWP | PSR_PS))
+	     | PSR_S
+	     | (GET_H_S () ? PSR_PS : 0)
+	     | (NEXT_WIN (GET_H_CWP ())));
+  SET_H_GR (H_GR__L1, GET_H_PC ());
+  SET_H_GR (H_GR__L2, GET_H_NPC ());
+  /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either
+     (??? doesn't *have* to be this way though).
+     Therefore we can't use SET_H_TBR here.  */
+  CPU (h_tbr) = new_pc = ((GET_H_TBR () & 0xfffff000)
+			  | (trap << 4));
+  return new_pc;
+}
+
+/* Subroutine of sparc64_do_trap to read target memory.  */
+
+static int
+syscall_read_mem (host_callback *cb, CB_SYSCALL *sc,
+		  unsigned long taddr, char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+/* Subroutine of sparc64_do_trap to write target memory.  */
+
+static int
+syscall_write_mem (host_callback *cb, CB_SYSCALL *sc,
+		   unsigned long taddr, const char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+/* Handle the trap insn when --environment=user.  */
+
+static IADDR
+sparc64_sw_trap_user (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  int trap = 128 + ((rs1 + rs2_simm13) & 127);
+  IADDR new_pc = pc + 4;
+
+  switch (trap)
+    {
+    case TRAP32_SYSCALL :
+      /* FIXME: Later make trap number runtime selectable.  */
+      {
+	CB_SYSCALL s;
+
+	CB_SYSCALL_INIT (&s);
+	s.func = a_sparc_h_gr_get (current_cpu, 8);
+	s.arg1 = a_sparc_h_gr_get (current_cpu, 9);
+	s.arg2 = a_sparc_h_gr_get (current_cpu, 10);
+	s.arg3 = a_sparc_h_gr_get (current_cpu, 11);
+	if (s.func == TARGET_SYS_exit)
+	  {
+	    /* Tell sim_resume program called exit().  */
+	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
+	  }
+	s.p1 = (PTR) sd;
+	s.p2 = (PTR) current_cpu;
+	s.read_mem = syscall_read_mem;
+	s.write_mem = syscall_write_mem;
+	cb_syscall (STATE_CALLBACK (CPU_STATE (current_cpu)), &s);
+	a_sparc_h_gr_set (current_cpu, 10, s.errcode);
+	a_sparc_h_gr_set (current_cpu, 8, s.result);
+	a_sparc_h_gr_set (current_cpu, 9, s.result2);
+	break;
+      }
+
+    case TRAP32_BREAKPOINT :
+      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+
+    case TRAP32_DIVIDE_0 :
+      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
+
+    case TRAP32_FLUSH_REGWIN :
+      sparc64_flush_regwins (current_cpu, pc, 0 /* error ok */);
+      break;
+
+    default :
+      sim_io_eprintf (sd, "Unsupported trap %d\n", trap);
+      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL);
+    }
+
+  return new_pc;
+}
+
+/* Called from the semantic code to handle the trap instruction.  */
+
+IADDR
+sparc64_sw_trap (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  IADDR new_pc;
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    new_pc = sparc64_sw_trap_oper (current_cpu, pc, rs1, rs2_simm13);
+  else
+    new_pc = sparc64_sw_trap_user (current_cpu, pc, rs1, rs2_simm13);
+  return new_pc;
+}
+
+/* Handle the rett insn.  */
+
+IADDR
+sparc64_do_rett (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13)
+{
+  int psr = GET_H_PSR ();
+
+  /* FIXME: check for trap conditions.  */
+
+  SET_H_PSR ((psr & ~(PSR_S + PSR_CWP))
+	     | ((psr & PSR_PS) ? PSR_S : 0)
+	     | PSR_ET
+	     | PREV_WIN (psr & PSR_CWP));
+
+  if (TRACE_INSN_P (current_cpu)) /* FIXME */
+    {
+      trace_result (current_cpu, "sp", 'x', GET_H_GR (H_GR__SP));
+      trace_result (current_cpu, "fp", 'x', GET_H_GR (H_GR__FP));
+      trace_result (current_cpu, "cwp", 'x', GET_H_CWP ());
+    }
+
+  return rs1 + rs2_simm13;
+}