* config/tc-arm.c(do_t_ldst): Warn on loading into sp with
writeback for appropriate cores/arch. * testsuite/gas/arm/ld-sp-warn-cortex-m3.d: New test. * testsuite/gas/arm/ld-sp-warn-cortex-m3.l: New test. * testsuite/gas/arm/ld-sp-warn-cortex-m4.d: New test. * testsuite/gas/arm/ld-sp-warn-cortex-m4.l: New test. * testsuite/gas/arm/ld-sp-warn-v7.d: New test. * testsuite/gas/arm/ld-sp-warn-v7.l: New test. * testsuite/gas/arm/ld-sp-warn-v7a.d: New test. * testsuite/gas/arm/ld-sp-warn-v7a.l: New test. * testsuite/gas/arm/ld-sp-warn-v7e-m.l: New test. * testsuite/gas/arm/ld-sp-warn-v7em.d: New test. * testsuite/gas/arm/ld-sp-warn-v7m.d: New test. * testsuite/gas/arm/ld-sp-warn-v7m.l: New test. * testsuite/gas/arm/ld-sp-warn-v7r.d: New test. * testsuite/gas/arm/ld-sp-warn-v7r.l: New test. * testsuite/gas/arm/ld-sp-warn.s: New test.
This commit is contained in:
parent
faf067f1a3
commit
8d67f500e1
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@ -239,6 +239,15 @@ static int mfloat_abi_opt = -1;
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static arm_feature_set selected_cpu = ARM_ARCH_NONE;
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/* Must be long enough to hold any of the names in arm_cpus. */
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static char selected_cpu_name[16];
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/* Return if no cpu was selected on command-line. */
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static bfd_boolean
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no_cpu_selected (void)
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{
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return selected_cpu.core == arm_arch_none.core
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&& selected_cpu.coproc == arm_arch_none.coproc;
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}
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#ifdef OBJ_ELF
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# ifdef EABI_DEFAULT
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static int meabi_flags = EABI_DEFAULT;
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@ -10378,6 +10387,21 @@ do_t_ldst (void)
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}
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/* Definitely a 32-bit variant. */
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/* Warning for Erratum 752419. */
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if (opcode == T_MNEM_ldr
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&& inst.operands[0].reg == REG_SP
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&& inst.operands[1].writeback == 1
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&& !inst.operands[1].immisreg)
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{
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if (no_cpu_selected ()
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|| (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
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as_warn (_("This instruction may be unpredictable "
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"if executed on M-profile cores "
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"with interrupts enabled."));
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}
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/* Do some validations regarding addressing modes. */
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if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
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&& opcode != T_MNEM_str)
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@ -1,3 +1,21 @@
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2011-05-11 Tejas Belagod <tejas.belagod@arm.com>
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* gas/arm/ld-sp-warn-cortex-m3.d: New test.
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* gas/arm/ld-sp-warn-cortex-m3.l: New test.
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* gas/arm/ld-sp-warn-cortex-m4.d: New test.
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* gas/arm/ld-sp-warn-cortex-m4.l: New test.
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* gas/arm/ld-sp-warn-v7.d: New test.
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* gas/arm/ld-sp-warn-v7.l: New test.
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* gas/arm/ld-sp-warn-v7a.d: New test.
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* gas/arm/ld-sp-warn-v7a.l: New test.
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* gas/arm/ld-sp-warn-v7e-m.l: New test.
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* gas/arm/ld-sp-warn-v7em.d: New test.
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* gas/arm/ld-sp-warn-v7m.d: New test.
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* gas/arm/ld-sp-warn-v7m.l: New test.
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* gas/arm/ld-sp-warn-v7r.d: New test.
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* gas/arm/ld-sp-warn-v7r.l: New test.
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* gas/arm/ld-sp-warn.s: New test.
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2010-05-10 Quentin Neill <quentin.neill@amd.com>
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* gas/i386/i386.exp: Add new bdver2 test cases.
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (cortex m3)
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# as: -mcpu=cortex-m3
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-cortex-m3.l
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@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (cortex m4)
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# as: -mcpu=cortex-m4
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-cortex-m4.l
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@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (v7)
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# as: -march=armv7
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-v7.l
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@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (v7a)
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# as: -march=armv7-a
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-v7a.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (v7em)
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# as: -march=armv7e-m
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-v7e-m.l
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (v7m)
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# as: -march=armv7m
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-v7m.l
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@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,4 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP (v7r)
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# as: -march=armv7-r
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn-v7r.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,3 @@
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# name: Erratum 752419: Warn Loads with writebacks to SP
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# source: ld-sp-warn.s
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# error-output: ld-sp-warn.l
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@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
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[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
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[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
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@ -0,0 +1,8 @@
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.syntax unified
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.thumb
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ldr sp, [r0, #16]!
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ldr sp, [r1], #8
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ldr sp, [r0, #16]
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ldr r1, [r0, #16]
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ldr r1, [r0, r1]!
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ldrsb sp, [r2, #16]!
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