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* config/tc-arm.c(do_t_ldst): Warn on loading into sp with 

writeback for appropriate cores/arch.
	* testsuite/gas/arm/ld-sp-warn-cortex-m3.d: New test.
	* testsuite/gas/arm/ld-sp-warn-cortex-m3.l: New test.
	* testsuite/gas/arm/ld-sp-warn-cortex-m4.d: New test.
	* testsuite/gas/arm/ld-sp-warn-cortex-m4.l: New test.
	* testsuite/gas/arm/ld-sp-warn-v7.d: New test.
	* testsuite/gas/arm/ld-sp-warn-v7.l: New test.
	* testsuite/gas/arm/ld-sp-warn-v7a.d: New test.
	* testsuite/gas/arm/ld-sp-warn-v7a.l: New test.
	* testsuite/gas/arm/ld-sp-warn-v7e-m.l: New test.
	* testsuite/gas/arm/ld-sp-warn-v7em.d: New test.
	* testsuite/gas/arm/ld-sp-warn-v7m.d: New test.
	* testsuite/gas/arm/ld-sp-warn-v7m.l: New test.
	* testsuite/gas/arm/ld-sp-warn-v7r.d: New test.
	* testsuite/gas/arm/ld-sp-warn-v7r.l: New test.
	* testsuite/gas/arm/ld-sp-warn.s: New test.
This commit is contained in:
Nick Clifton 2011-05-11 09:25:44 +00:00
parent faf067f1a3
commit 8d67f500e1
19 changed files with 117 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
gas/config/tc-arm.c
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@ -239,6 +239,15 @@ static int mfloat_abi_opt = -1;
static arm_feature_set selected_cpu = ARM_ARCH_NONE;
/* Must be long enough to hold any of the names in arm_cpus. */
static char selected_cpu_name[16];
/* Return if no cpu was selected on command-line. */
static bfd_boolean
no_cpu_selected (void)
{
return selected_cpu.core == arm_arch_none.core
&& selected_cpu.coproc == arm_arch_none.coproc;
}
#ifdef OBJ_ELF
# ifdef EABI_DEFAULT
static int meabi_flags = EABI_DEFAULT;
@ -10378,6 +10387,21 @@ do_t_ldst (void)
}
/* Definitely a 32-bit variant. */
/* Warning for Erratum 752419. */
if (opcode == T_MNEM_ldr
&& inst.operands[0].reg == REG_SP
&& inst.operands[1].writeback == 1
&& !inst.operands[1].immisreg)
{
if (no_cpu_selected ()
|| (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
as_warn (_("This instruction may be unpredictable "
"if executed on M-profile cores "
"with interrupts enabled."));
}
/* Do some validations regarding addressing modes. */
if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
&& opcode != T_MNEM_str)

18
gas/testsuite/ChangeLog
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@ -1,3 +1,21 @@
2011-05-11 Tejas Belagod <tejas.belagod@arm.com>
* gas/arm/ld-sp-warn-cortex-m3.d: New test.
* gas/arm/ld-sp-warn-cortex-m3.l: New test.
* gas/arm/ld-sp-warn-cortex-m4.d: New test.
* gas/arm/ld-sp-warn-cortex-m4.l: New test.
* gas/arm/ld-sp-warn-v7.d: New test.
* gas/arm/ld-sp-warn-v7.l: New test.
* gas/arm/ld-sp-warn-v7a.d: New test.
* gas/arm/ld-sp-warn-v7a.l: New test.
* gas/arm/ld-sp-warn-v7e-m.l: New test.
* gas/arm/ld-sp-warn-v7em.d: New test.
* gas/arm/ld-sp-warn-v7m.d: New test.
* gas/arm/ld-sp-warn-v7m.l: New test.
* gas/arm/ld-sp-warn-v7r.d: New test.
* gas/arm/ld-sp-warn-v7r.l: New test.
* gas/arm/ld-sp-warn.s: New test.
2010-05-10 Quentin Neill <quentin.neill@amd.com>
* gas/i386/i386.exp: Add new bdver2 test cases.

4
gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (cortex m3)
# as: -mcpu=cortex-m3
# source: ld-sp-warn.s
# error-output: ld-sp-warn-cortex-m3.l

5
gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.l Normal file
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@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

4
gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (cortex m4)
# as: -mcpu=cortex-m4
# source: ld-sp-warn.s
# error-output: ld-sp-warn-cortex-m4.l

5
gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.l Normal file
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@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

4
gas/testsuite/gas/arm/ld-sp-warn-v7.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (v7)
# as: -march=armv7
# source: ld-sp-warn.s
# error-output: ld-sp-warn-v7.l

5
gas/testsuite/gas/arm/ld-sp-warn-v7.l Normal file
View File

@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

4
gas/testsuite/gas/arm/ld-sp-warn-v7a.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (v7a)
# as: -march=armv7-a
# source: ld-sp-warn.s
# error-output: ld-sp-warn-v7a.l

3
gas/testsuite/gas/arm/ld-sp-warn-v7a.l Normal file
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@ -0,0 +1,3 @@
[^:]*: Assembler messages:
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

5
gas/testsuite/gas/arm/ld-sp-warn-v7e-m.l Normal file
View File

@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

4
gas/testsuite/gas/arm/ld-sp-warn-v7em.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (v7em)
# as: -march=armv7e-m
# source: ld-sp-warn.s
# error-output: ld-sp-warn-v7e-m.l

4
gas/testsuite/gas/arm/ld-sp-warn-v7m.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (v7m)
# as: -march=armv7m
# source: ld-sp-warn.s
# error-output: ld-sp-warn-v7m.l

5
gas/testsuite/gas/arm/ld-sp-warn-v7m.l Normal file
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@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

4
gas/testsuite/gas/arm/ld-sp-warn-v7r.d Normal file
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@ -0,0 +1,4 @@
# name: Erratum 752419: Warn Loads with writebacks to SP (v7r)
# as: -march=armv7-r
# source: ld-sp-warn.s
# error-output: ld-sp-warn-v7r.l

3
gas/testsuite/gas/arm/ld-sp-warn-v7r.l Normal file
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@ -0,0 +1,3 @@
[^:]*: Assembler messages:
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

3
gas/testsuite/gas/arm/ld-sp-warn.d Normal file
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@ -0,0 +1,3 @@
# name: Erratum 752419: Warn Loads with writebacks to SP
# source: ld-sp-warn.s
# error-output: ld-sp-warn.l

5
gas/testsuite/gas/arm/ld-sp-warn.l Normal file
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@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'

8
gas/testsuite/gas/arm/ld-sp-warn.s Normal file
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@ -0,0 +1,8 @@
.syntax unified
.thumb
ldr sp, [r0, #16]!
ldr sp, [r1], #8
ldr sp, [r0, #16]
ldr r1, [r0, #16]
ldr r1, [r0, r1]!
ldrsb sp, [r2, #16]!