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opcodes/ 

* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
	This has been reported as being accepted by the Sun assmebler.

gas/testsuite/

	* gas/sparc/save-args.[sd]: New test.
	* gas/sparc/sparc.exp: Run new test.
This commit is contained in:
David S. Miller 2011-09-08 19:03:17 +00:00
parent 9bf29d72d4
commit 8dbb9eb3c6
6 changed files with 26 additions and 0 deletions
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3
gas/testsuite/ChangeLog
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@ -7,6 +7,9 @@
* gas/sparc/v8-movwr-imm.[sd]: New test.
* gas/sparc/sparc.exp: Run new tests.
* gas/sparc/save-args.[sd]: New test.
* gas/sparc/sparc.exp: Run new test.
2011-09-08 David S. Miller <davem@davemloft.net>
* gas/sparc/hpcvis3.s: Correct pdistn test.

12
gas/testsuite/gas/sparc/save-args.d Normal file
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@ -0,0 +1,12 @@
#as: -Av8
#objdump: -dr
#name: software traps
.*: +file format .*
Disassembly of section .text:
00000000 <foo>:
0: 81 e0 00 00 save
4: 9d e3 bf a0 save %sp, -96, %sp
8: 9d e3 bf a0 save %sp, -96, %sp

6
gas/testsuite/gas/sparc/save-args.s Normal file
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@ -0,0 +1,6 @@
! Test several forms of save argument
.text
foo:
save
save %sp, -96, %sp
save -96, %sp, %sp

1
gas/testsuite/gas/sparc/sparc.exp
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@ -53,6 +53,7 @@ if [istarget sparc*-*-*] {
run_dump_test "imm-plus-rreg"
run_dump_test "ticc-imm-reg"
run_dump_test "v8-movwr-imm"
run_dump_test "save-args"
run_dump_test "v9branch1"
run_dump_test "v9branch2"
run_dump_test "v9branch3"

3
opcodes/ChangeLog
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@ -12,6 +12,9 @@
* sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
mov aliases.
* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
This has been reported as being accepted by the Sun assmebler.
2011-09-08 David S. Miller <davem@davemloft.net>
* sparc-opc.c (pdistn): Destination is integer not float register.

1
opcodes/sparc-opc.c
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@ -684,6 +684,7 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 },
{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, v6 }, /* Sun assembler compatibility */
{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 },
{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */