* mn10300_sim.h: Fix ordering of bits in the PSW.
This commit is contained in:
parent
1ec53ef597
commit
8def922034
|
@ -1,5 +1,7 @@
|
||||||
Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
|
Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
|
||||||
|
|
||||||
|
* mn10300_sim.h: Fix ordering of bits in the PSW.
|
||||||
|
|
||||||
* interp.c: Improve hashing routine to avoid long list
|
* interp.c: Improve hashing routine to avoid long list
|
||||||
traversals for common instructions. Add HASH_STAT support.
|
traversals for common instructions. Add HASH_STAT support.
|
||||||
Rewrite opcode dispatch code using a big switch instead of
|
Rewrite opcode dispatch code using a big switch instead of
|
||||||
|
|
|
@ -72,10 +72,10 @@ extern struct simops Simops[];
|
||||||
#define PC (State.regs[9])
|
#define PC (State.regs[9])
|
||||||
|
|
||||||
#define PSW (State.regs[11])
|
#define PSW (State.regs[11])
|
||||||
#define PSW_V 0x1
|
#define PSW_Z 0x1
|
||||||
#define PSW_C 0x2
|
#define PSW_N 0x2
|
||||||
#define PSW_N 0x4
|
#define PSW_C 0x4
|
||||||
#define PSW_Z 0x8
|
#define PSW_V 0x8
|
||||||
|
|
||||||
#define REG_D0 0
|
#define REG_D0 0
|
||||||
#define REG_A0 4
|
#define REG_A0 4
|
||||||
|
|
Loading…
Reference in New Issue