* mn10300_sim.h: Fix ordering of bits in the PSW.
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Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
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* mn10300_sim.h: Fix ordering of bits in the PSW.
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* interp.c: Improve hashing routine to avoid long list
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traversals for common instructions. Add HASH_STAT support.
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Rewrite opcode dispatch code using a big switch instead of
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@ -72,10 +72,10 @@ extern struct simops Simops[];
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#define PC (State.regs[9])
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#define PSW (State.regs[11])
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#define PSW_V 0x1
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#define PSW_C 0x2
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#define PSW_N 0x4
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#define PSW_Z 0x8
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#define PSW_Z 0x1
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#define PSW_N 0x2
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#define PSW_C 0x4
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#define PSW_V 0x8
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#define REG_D0 0
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#define REG_A0 4
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