OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. 

PR 22179
opcodes	* riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
	names for the fmv.x.s and fmv.s.x instructions respectively.

gas	* testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
	renamed fmv.x.s and fmv.s.x instructions.
	* testsuite/gas/riscv/fmv.x.d: New file: Test driver.
This commit is contained in:
Nick Clifton 2017-09-27 16:21:36 +01:00
parent f21b4d5c59
commit 8e43602e34
6 changed files with 36 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2017-09-27 Nick Clifton <nickc@redhat.com>
PR 22179
* testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
renamed fmv.x.s and fmv.s.x instructions.
* testsuite/gas/riscv/fmv.x.d: New file: Test driver.
2017-09-21 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/elf_mach_5900.d: New test.

13
gas/testsuite/gas/riscv/fmv.x.d Normal file
View File

@ -0,0 +1,13 @@
#as:
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+0:[ ]+e00b8653[ ]+fmv.x.w[ ]+a2,fs7
[ ]+4:[ ]+e00b8653[ ]+fmv.x.w[ ]+a2,fs7
[ ]+8:[ ]+f00800d3[ ]+fmv.w.x[ ]+ft1,a6
[ ]+c:[ ]+f00800d3[ ]+fmv.w.x[ ]+ft1,a6

4
gas/testsuite/gas/riscv/fmv.x.s Normal file
View File

@ -0,0 +1,4 @@
fmv.x.w a2, fs7
fmv.x.s a2, fs7
fmv.w.x ft1, a6
fmv.s.x ft1, a6

1
gas/testsuite/gas/riscv/riscv.exp
View File

@ -20,4 +20,5 @@
if [istarget riscv*-*-*] {
run_dump_test "t_insns"
run_dump_test "fmv.x"
}

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2017-09-27 Nick Clifton <nickc@redhat.com>
PR 22179
* riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
names for the fmv.x.s and fmv.s.x instructions respectively.
2017-09-26 do <do@nerilex.org>
PR 22123

5
opcodes/riscv-opc.c
View File

@ -435,8 +435,13 @@ const struct riscv_opcode riscv_opcodes[] =
{"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS },
{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 },
{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
{"fmv.x.w", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.w.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },