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Reverted writes_to_pc() back to old version of code until PC operands are 

supported by cgen.
This commit is contained in:
Nick Clifton 1998-02-13 21:52:13 +00:00
parent ba4da4fe4e
commit 8e7a5a048a
3 changed files with 16 additions and 27 deletions
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5
gas/ChangeLog
View File

@ -5,14 +5,15 @@ Fri Feb 13 16:41:42 1998 Ian Lance Taylor <ian@cygnus.com>
* doc/Makefile.am (AUTOMAKE_OPTIONS): Define.
* doc/Makefile.in: Rebuild.
start-sanitize-m32rx
Fri Feb 13 09:57:11 1998 Nick Clifton <nickc@cygnus.com>
* config/tc-m32r.c (first_writes_to_seconds_operands): New
function. Replaces get_src_reg(), check_for_side_effects(),
reads_from_src_reg(). Uses new insn operand features of cgen.
(writes_to_pc): New function.
(writes_to_pc): New function., but with new code suppressed for now.
(md_assemble): Call first_writes_to_seconds_operands().
end-sanitize-m32rx
Fri Feb 13 00:47:44 1998 Ian Lance Taylor <ian@cygnus.com>
* config/tc-mips.c (macro_build): Handle operand type 'C'.

9
gas/config/tc-m32r.c
View File

@ -432,8 +432,9 @@ static int
writes_to_pc (a)
m32r_insn * a;
{
#if 0
const CGEN_OPERAND_INSTANCE * a_operands;
for (a_operands = CGEN_INSN_OPERANDS (a->insn);
CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
a_operands ++)
@ -442,7 +443,11 @@ writes_to_pc (a)
&& CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
return 1;
}
#else
if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
|| CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
return 1;
#endif
return 0;
}

29
gas/doc/c-m32r.texi
View File

@ -70,7 +70,7 @@ There are several warning and error messages that can be produced by
@table @code
@item output of first instruction is the same as the input of second instruction - is this intentional ?
@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
This message is only produced if warnings for explicit parallel
conflicts have been enabled. It indicates that the assembler has
encountered a parallel instruction in which the destination register of
@ -79,7 +79,7 @@ instruction. For example in this code fragment
@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
move instruction and the input to the neg instruction.
@item output of second instruction is the same as the input of first instruction - is this intentional ?
@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
This message is only produced if warnings for explicit parallel
conflicts have been enabled. It indicates that the assembler has
encountered a parallel instruction in which the destination register of
@ -109,31 +109,14 @@ executed in parallel.
This message is produced when the assembler encounters a parallel
instruction whoes components both use the same execution pipeline.
@item Both instructions write to the link register
This message is produced when the assembler encounters a parallel
instruction whoes components both write to the link register, one of
them as a side effect. For example this code fragment will produce this
message: @samp{jl r0 || mv r14, r1}
@item Destination of first instruction written to by side effect of second instruction.
This message is produced when the assembler encounters a parallel
instruction whoes right hand component has a side effect which modifes a
register used as the destination by the left hand component. For
example this code fragment will produce this message:
@samp{mv r1, r2 || ld r0, @@r1+}
@item Destination of second instruction written to by side effect of first instruction.
This message is produced when the assembler encounters a parallel
instruction whoes left hand component has a side effect which modifes a
register used as the destination by the right hand component. For
example this code fragment will produce this message:
@samp{st r2, @@-r1 || mv r1, r3}
@item Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel
instruction where both components attempt to modify the same register.
For example this code fragment will produce this message:
For example these code fragments will produce this message:
@samp{mv r1, r2 || neg r1, r3}
@samp{jl r0 || mv r14, r1}
@samp{st r2, @@-r1 || mv r1, r3}
@samp{mv r1, r2 || ld r0, @@r1+}
@end table
@c end-sanitize-m32rx