Fix disassembling of TIC6X parallel instructions where the previous fetch packet ended with a 32-bit insn.
PR 21056 opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel instructions when the previous fetch packet ends with a 32-bit instruction. gas * testsuite/gas/tic6x/insns16-parallel.s: New test case. * testsuite/gas/tic6x/insns16-parallel.d: New test driver.
This commit is contained in:
Alexis Deruell
Nick Clifton
parent
0348d4be16
commit
8ec5cf65a8
@ -1,3 +1,9 @@
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2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
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PR 21056
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* testsuite/gas/tic6x/insns16-parallel.s: New test case.
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* testsuite/gas/tic6x/insns16-parallel.d: New test driver.
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2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* configure.tgt (aarch64*-*-rtems*): Remove.
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43
gas/testsuite/gas/tic6x/insns16-parallel.d
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43
gas/testsuite/gas/tic6x/insns16-parallel.d
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name:
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#as: -march=c64x+ -mlittle-endian
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.*: *file format elf32-tic6x-le
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Disassembly of section .text:
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[ \t]*\.\.\.
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008001[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+\|\|[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 8c6e[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 8c6e[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> e8002000[ \t]+<fetch packet header 0xe8002000>
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+\|\|[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008001[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> e0000000[ \t]+<fetch packet header 0xe0000000>
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+\|\|[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[0-9a-f]+[02468ace] <[^>]*> 00008000[ \t]+nop 5
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[ \t]*\.\.\.
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42
gas/testsuite/gas/tic6x/insns16-parallel.s
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42
gas/testsuite/gas/tic6x/insns16-parallel.s
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.text
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nop
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.align 16
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nop
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.align 16
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FP0:
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008001
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FP1:
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.short 0x8c6e
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.short 0x8c6e
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.word 0xe8002000
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FP2:
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008001
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.word 0xe0000000
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FP3:
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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.word 0x00008000
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@ -1,3 +1,10 @@
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2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
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PR 21056
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* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
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instructions when the previous fetch packet ends with a 32-bit
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instruction.
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2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
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* pru-opc.c: Remove vague reference to a future GDB port.
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@ -510,8 +510,17 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info)
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prev_header_based
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= tic6x_check_fetch_packet_header (fp_prev, &prev_header, info);
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if (prev_header_based && prev_header.word_compact[6])
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p_bit = prev_header.p_bits[13];
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if (prev_header_based)
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{
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if (prev_header.word_compact[6])
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p_bit = prev_header.p_bits[13];
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else
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{
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unsigned int prev_opcode = tic6x_extract_32 (fp_prev + 24,
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info);
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p_bit = (prev_opcode & 0x1) ? TRUE : FALSE;
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}
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}
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else
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{
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unsigned int prev_opcode = tic6x_extract_32 (fp_prev + 28,
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