Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.
sim/aarch64/ * simulator.c (mul64hi): Shift carry left by 32. (smulh): Change signum to negate. If negate, invert result, and add carry bit if low part of multiply result is zero. sim/testsuite/sim/aarch64/ * sumov.s: Correct compare test values. * sumulh.s: New.
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@ -1,3 +1,9 @@
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2017-03-03 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (mul64hi): Shift carry left by 32.
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(smulh): Change signum to negate. If negate, invert result, and add
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carry bit if low part of multiply result is zero.
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2017-02-25 Jim Wilson <jim.wilson@linaro.org>
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2017-02-25 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_SMOV_into_scalar): New.
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* simulator.c (do_vec_SMOV_into_scalar): New.
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@ -13020,6 +13020,8 @@ mul64hi (uint64_t value1, uint64_t value2)
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/* Drop lowest 32 bits of middle cross-product. */
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/* Drop lowest 32 bits of middle cross-product. */
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result = resultmid1 >> 32;
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result = resultmid1 >> 32;
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/* Move carry bit to just above middle cross-product highest bit. */
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carry = carry << 32;
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/* Add top cross-product plus and any carry. */
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/* Add top cross-product plus and any carry. */
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result += xproducthi + carry;
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result += xproducthi + carry;
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@ -13042,7 +13044,7 @@ smulh (sim_cpu *cpu)
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int64_t value2 = aarch64_get_reg_u64 (cpu, rm, NO_SP);
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int64_t value2 = aarch64_get_reg_u64 (cpu, rm, NO_SP);
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uint64_t uvalue1;
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uint64_t uvalue1;
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uint64_t uvalue2;
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uint64_t uvalue2;
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int64_t signum = 1;
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int negate = 0;
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if (ra != R31)
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if (ra != R31)
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HALT_UNALLOC;
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HALT_UNALLOC;
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@ -13051,7 +13053,7 @@ smulh (sim_cpu *cpu)
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the fix the sign up afterwards. */
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the fix the sign up afterwards. */
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if (value1 < 0)
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if (value1 < 0)
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{
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{
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signum *= -1L;
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negate = !negate;
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uvalue1 = -value1;
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uvalue1 = -value1;
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}
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}
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else
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else
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@ -13061,7 +13063,7 @@ smulh (sim_cpu *cpu)
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if (value2 < 0)
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if (value2 < 0)
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{
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{
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signum *= -1L;
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negate = !negate;
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uvalue2 = -value2;
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uvalue2 = -value2;
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}
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}
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else
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else
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@ -13070,9 +13072,18 @@ smulh (sim_cpu *cpu)
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}
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}
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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uresult = mul64hi (uvalue1, uvalue2);
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uresult = mul64hi (uvalue1, uvalue2);
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result = uresult;
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result = uresult;
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result *= signum;
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if (negate)
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{
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/* Multiply 128-bit result by -1, which means highpart gets inverted,
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and has carry in added only if low part is 0. */
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result = ~result;
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if ((uvalue1 * uvalue2) == 0)
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result += 1;
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}
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aarch64_set_reg_s64 (cpu, rd, NO_SP, result);
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aarch64_set_reg_s64 (cpu, rd, NO_SP, result);
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}
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}
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@ -1,3 +1,8 @@
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2017-03-03 Jim Wilson <jim.wilson@linaro.org>
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* sumov.s: Correct compare test values.
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* sumulh.s: New.
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2017-02-25 Jim Wilson <jim.wilson@linaro.org>
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2017-02-25 Jim Wilson <jim.wilson@linaro.org>
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* sumov.s: New.
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* sumov.s: New.
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@ -34,7 +34,7 @@ input:
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smov w1, v0.h[4]
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smov w1, v0.h[4]
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cmp w0, #0x0201
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cmp w0, #0x0201
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bne .Lfailure
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bne .Lfailure
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cmp w1, #-2315
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cmp w1, #-3343
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bne .Lfailure
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bne .Lfailure
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smov x0, v0.h[1]
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smov x0, v0.h[1]
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@ -50,8 +50,9 @@ input:
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movk x2, #0x0807, lsl #16
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movk x2, #0x0807, lsl #16
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cmp x0, x2
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cmp x0, x2
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bne .Lfailure
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bne .Lfailure
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mov x3, #0xf6f5
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mov w3, #0xf6f5
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movk x3, #0xf8f7, lsl #16
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movk w3, #0xf8f7, lsl #16
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sxtw x3, w3
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cmp x1, x3
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cmp x1, x3
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bne .Lfailure
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bne .Lfailure
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@ -64,9 +65,10 @@ input:
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umov w0, v0.h[0]
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umov w0, v0.h[0]
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umov w1, v0.h[4]
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umov w1, v0.h[4]
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cmp w0, #0201
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cmp w0, #0x0201
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bne .Lfailure
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bne .Lfailure
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cmp w1, #0xf2f1
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mov w2, #0xf2f1
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cmp w1, w2
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bne .Lfailure
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bne .Lfailure
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umov w0, v0.s[0]
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umov w0, v0.s[0]
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@ -0,0 +1,56 @@
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# mach: aarch64
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# Check the multiply highpart instructions: smulh, umulh.
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# Test -2*2, -1<<32*-1<<32, -2*-2, and 2*2.
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.include "testutils.inc"
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.data
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.align 4
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start
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mov x0, #-2
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mov x1, #2
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smulh x2, x0, x1
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cmp x2, #-1
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bne .Lfailure
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umulh x3, x0, x1
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cmp x3, #1
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bne .Lfailure
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mov w0, #-1
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lsl x0, x0, #32 // 0xffffffff00000000
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mov x1, x0
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smulh x2, x0, x1
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cmp x2, #1
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bne .Lfailure
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umulh x3, x0, x1
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mov w4, #-2
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lsl x4, x4, #32
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add x4, x4, #1 // 0xfffffffe00000001
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cmp x3, x4
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bne .Lfailure
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mov x0, #-2
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mov x1, #-2
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smulh x2, x0, x1
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cmp x2, #0
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bne .Lfailure
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umulh x3, x0, x1
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cmp x3, #-4
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bne .Lfailure
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mov x0, #2
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mov x1, #2
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smulh x2, x0, x1
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cmp x2, #0
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bne .Lfailure
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umulh x3, x0, x1
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cmp x3, #0
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bne .Lfailure
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pass
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.Lfailure:
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fail
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