* gas/mips/sync.d: Pass -mips2 to the assembler.
* gas/mips/elf_e_flags.s: Tweak code so that the tests pass for mips-elf target as well as mips64-elf target. * gas/mips/elf_e_flags1.d: Corresponding changes. * gas/mips/elf_e_flags2.d: Likewise. * gas/mips/elf_e_flags3.d: Likewise. * gas/mips/elf_e_flags4.d: Likewise. * gas/elf/elf.exp: Add setup_xfail for mips*-*-*. * gas/all/itbl-test.c (main): Update itbl_get_reg_val call for new parameter.
This commit is contained in:
Ian Lance Taylor
parent
a22b281cd7
commit
8ee99f93eb
|
|
@ -1,3 +1,19 @@
|
|||
1999-06-10 Ian Lance Taylor <ian@zembu.com>
|
||||
|
||||
* gas/mips/sync.d: Pass -mips2 to the assembler.
|
||||
|
||||
* gas/mips/elf_e_flags.s: Tweak code so that the tests pass for
|
||||
mips-elf target as well as mips64-elf target.
|
||||
* gas/mips/elf_e_flags1.d: Corresponding changes.
|
||||
* gas/mips/elf_e_flags2.d: Likewise.
|
||||
* gas/mips/elf_e_flags3.d: Likewise.
|
||||
* gas/mips/elf_e_flags4.d: Likewise.
|
||||
|
||||
* gas/elf/elf.exp: Add setup_xfail for mips*-*-*.
|
||||
|
||||
* gas/all/itbl-test.c (main): Update itbl_get_reg_val call for new
|
||||
parameter.
|
||||
|
||||
1999-06-10 Jakub Jelinek <jj@ultra.linux.cz>
|
||||
|
||||
* gas/sparc/synth64.s: Add checks for single register signx/clruw.
|
||||
|
|
|
|||
|
|
@ -118,8 +118,8 @@ test_reg (e_processor processor, e_type type, char *name,
|
|||
n, processor, type, val);
|
||||
|
||||
/* We require that names be unique amoung processors and types. */
|
||||
v = itbl_get_reg_val (name);
|
||||
if (!v || v != val)
|
||||
if (! itbl_get_reg_val (name, &v)
|
||||
|| v != val)
|
||||
printf ("Error - reg val not found for processor=%d, type=%d, name=%s\n",
|
||||
processor, type, name);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -8,7 +8,11 @@ if { [istarget "*-elf*"]
|
|||
|| [istarget "sparc*-*-solaris*"]
|
||||
|| [istarget "mips*-*-irix6*"] } then {
|
||||
|
||||
# FIXME: This doesn't work for MIPS targets because of the .reginfo
|
||||
# and .mdebug sections.
|
||||
setup_xfail mips*-*-*
|
||||
run_dump_test "section0"
|
||||
run_dump_test "section1"
|
||||
|
||||
setup_xfail mips*-*-*
|
||||
run_dump_test "section1"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,11 @@
|
|||
We use the -m4650 flag to get the 4650-specific 'mul' instruction
|
||||
in there; the test suite wants to be sure that GAS's -m4650 flag
|
||||
will indeed cause it to generate the 4650 mul instruction, and not
|
||||
expand it as a macro. */
|
||||
expand it as a macro.
|
||||
|
||||
Ian 10 June 1999: I tweaked the resulting assembler file so that it
|
||||
would generate the same code when gas was configured for mips-elf
|
||||
and for mips64-elf. */
|
||||
|
||||
int
|
||||
foo (int a, int b)
|
||||
|
|
|
|||
|
|
@ -28,11 +28,11 @@ main:
|
|||
.mask 0x80000000,-8
|
||||
.fmask 0x00000000,0
|
||||
subu $sp,$sp,40
|
||||
sd $31,32($sp)
|
||||
sw $31,32($sp)
|
||||
jal __gccmain
|
||||
move $2,$0
|
||||
ld $31,32($sp)
|
||||
#nop
|
||||
lw $31,32($sp)
|
||||
nop
|
||||
.set noreorder
|
||||
.set nomacro
|
||||
j $31
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
# objdump: -fd
|
||||
|
||||
.*:.*file format.*mips.*
|
||||
architecture: mips:4000, flags 0x00000011:
|
||||
architecture: mips:[34]000, flags 0x00000011:
|
||||
HAS_RELOC, HAS_SYMS
|
||||
start address 0x0000000000000000
|
||||
|
||||
|
|
@ -17,10 +17,11 @@ Disassembly of section .text:
|
|||
|
||||
0000000000000010 <main>:
|
||||
10: 27bdffd8 addiu \$sp,\$sp,-40
|
||||
14: ffbf0020 sd \$ra,32\(\$sp\)
|
||||
14: afbf0020 sw \$ra,32\(\$sp\)
|
||||
18: 0c000000 jal 0 <foo>
|
||||
1c: 00000000 nop
|
||||
20: 0000102d move \$v0,\$zero
|
||||
24: dfbf0020 ld \$ra,32\(\$sp\)
|
||||
28: 03e00008 jr \$ra
|
||||
2c: 27bd0028 addiu \$sp,\$sp,40
|
||||
20: 0000102[1d] move \$v0,\$zero
|
||||
24: 8fbf0020 lw \$ra,32\(\$sp\)
|
||||
28: 00000000 nop
|
||||
2c: 03e00008 jr \$ra
|
||||
30: 27bd0028 addiu \$sp,\$sp,40
|
||||
|
|
|
|||
|
|
@ -17,10 +17,11 @@ Disassembly of section .text:
|
|||
|
||||
000000000000000c <main>:
|
||||
c: 27bdffd8 addiu \$sp,\$sp,-40
|
||||
10: ffbf0020 sd \$ra,32\(\$sp\)
|
||||
10: afbf0020 sw \$ra,32\(\$sp\)
|
||||
14: 0c000000 jal 0 <foo>
|
||||
18: 00000000 nop
|
||||
1c: 0000102d move \$v0,\$zero
|
||||
20: dfbf0020 ld \$ra,32\(\$sp\)
|
||||
24: 03e00008 jr \$ra
|
||||
28: 27bd0028 addiu \$sp,\$sp,40
|
||||
20: 8fbf0020 lw \$ra,32\(\$sp\)
|
||||
24: 00000000 nop
|
||||
28: 03e00008 jr \$ra
|
||||
2c: 27bd0028 addiu \$sp,\$sp,40
|
||||
|
|
|
|||
|
|
@ -17,10 +17,11 @@ Disassembly of section .text:
|
|||
|
||||
000000000000000c <main>:
|
||||
c: 27bdffd8 addiu \$sp,\$sp,-40
|
||||
10: ffbf0020 sd \$ra,32\(\$sp\)
|
||||
10: afbf0020 sw \$ra,32\(\$sp\)
|
||||
14: 0c000000 jal 0 <foo>
|
||||
18: 00000000 nop
|
||||
1c: 0000102d move \$v0,\$zero
|
||||
20: dfbf0020 ld \$ra,32\(\$sp\)
|
||||
24: 03e00008 jr \$ra
|
||||
28: 27bd0028 addiu \$sp,\$sp,40
|
||||
20: 8fbf0020 lw \$ra,32\(\$sp\)
|
||||
24: 00000000 nop
|
||||
28: 03e00008 jr \$ra
|
||||
2c: 27bd0028 addiu \$sp,\$sp,40
|
||||
|
|
|
|||
|
|
@ -17,10 +17,11 @@ Disassembly of section .text:
|
|||
|
||||
000000000000000c <main>:
|
||||
c: 27bdffd8 addiu \$sp,\$sp,-40
|
||||
10: ffbf0020 sd \$ra,32\(\$sp\)
|
||||
10: afbf0020 sw \$ra,32\(\$sp\)
|
||||
14: 0c000000 jal 0 <foo>
|
||||
18: 00000000 nop
|
||||
1c: 0000102d move \$v0,\$zero
|
||||
20: dfbf0020 ld \$ra,32\(\$sp\)
|
||||
24: 03e00008 jr \$ra
|
||||
28: 27bd0028 addiu \$sp,\$sp,40
|
||||
20: 8fbf0020 lw \$ra,32\(\$sp\)
|
||||
24: 00000000 nop
|
||||
28: 03e00008 jr \$ra
|
||||
2c: 27bd0028 addiu \$sp,\$sp,40
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: sync instructions
|
||||
#as:
|
||||
#as: -mips2
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue