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[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 

1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
This commit is contained in:
Nelson Chu 2020-05-20 17:22:48 +01:00 committed by Nick Clifton
parent 41977d16e4
commit 8f595e9b4f
71 changed files with 7149 additions and 4478 deletions
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21
bfd/ChangeLog
View File

@ -1,3 +1,24 @@
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
2020-05-20 Alan Modra <amodra@gmail.com>
PR 25993

6
bfd/elfnn-riscv.c
View File

@ -2810,7 +2810,7 @@ riscv_merge_std_ext (bfd *ibfd,
if (!riscv_i_or_e_p (ibfd, out_arch, out))
return FALSE;
if (in->name[0] != out->name[0])
if (strcasecmp (in->name, out->name) != 0)
{
/* TODO: We might allow merge 'i' with 'e'. */
_bfd_error_handler
@ -2983,13 +2983,17 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
riscv_parse_subset_t rpe_in;
riscv_parse_subset_t rpe_out;
/* Only assembler needs to check the default version of ISA, so just set
the rpe_in.get_default_version and rpe_out.get_default_version to NULL. */
rpe_in.subset_list = &in_subsets;
rpe_in.error_handler = _bfd_error_handler;
rpe_in.xlen = &xlen_in;
rpe_in.get_default_version = NULL;
rpe_out.subset_list = &out_subsets;
rpe_out.error_handler = _bfd_error_handler;
rpe_out.xlen = &xlen_out;
rpe_out.get_default_version = NULL;
if (in_arch == NULL && out_arch == NULL)
return NULL;

281
bfd/elfxx-riscv.c
View File

@ -1025,9 +1025,8 @@ riscv_elf_add_sub_reloc (bfd *abfd,
`minor_version`: Parsing result of minor version, set to 0 if version is
not present in arch string, but set to `default_minor_version` if
`major_version` using default_major_version.
`default_major_version`: Default major version.
`default_minor_version`: Default minor version.
`std_ext_p`: True if parsing std extension. */
`std_ext_p`: True if parsing std extension.
`use_default_version`: Set it to True if we need the default version. */
static const char *
riscv_parsing_subset_version (riscv_parse_subset_t *rps,
@ -1035,17 +1034,16 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
const char *p,
unsigned *major_version,
unsigned *minor_version,
unsigned default_major_version,
unsigned default_minor_version,
bfd_boolean std_ext_p)
bfd_boolean std_ext_p,
bfd_boolean *use_default_version)
{
bfd_boolean major_p = TRUE;
unsigned version = 0;
unsigned major = 0;
unsigned minor = 0;
char np;
for (;*p; ++p)
*major_version = 0;
*minor_version = 0;
for (; *p; ++p)
{
if (*p == 'p')
{
@ -1062,13 +1060,14 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
}
else
{
rps->error_handler ("-march=%s: Expect number after `%dp'.",
march, version);
rps->error_handler
(_("-march=%s: Expect number after `%dp'."),
march, version);
return NULL;
}
}
major = version;
*major_version = version;
major_p = FALSE;
version = 0;
}
@ -1079,21 +1078,15 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
}
if (major_p)
major = version;
*major_version = version;
else
minor = version;
*minor_version = version;
if (major == 0 && minor == 0)
{
/* We don't found any version string, use default version. */
*major_version = default_major_version;
*minor_version = default_minor_version;
}
else
{
*major_version = major;
*minor_version = minor;
}
/* We can not find any version in string, need to parse default version. */
if (use_default_version != NULL
&& *major_version == 0
&& *minor_version == 0)
*use_default_version = TRUE;
return p;
}
@ -1118,78 +1111,114 @@ riscv_supported_std_ext (void)
static const char *
riscv_parse_std_ext (riscv_parse_subset_t *rps,
const char *march, const char *p)
const char *march,
const char *p)
{
const char *all_std_exts = riscv_supported_std_ext ();
const char *std_exts = all_std_exts;
unsigned major_version = 0;
unsigned minor_version = 0;
char std_ext = '\0';
bfd_boolean use_default_version = FALSE;
/* First letter must start with i, e or g. */
switch (*p)
{
case 'i':
p++;
p = riscv_parsing_subset_version (
rps,
march,
p, &major_version, &minor_version,
/* default_major_version= */ 2,
/* default_minor_version= */ 0,
/* std_ext_p= */TRUE);
riscv_add_subset (rps->subset_list, "i", major_version, minor_version);
p = riscv_parsing_subset_version (rps,
march,
++p,
&major_version,
&minor_version,
/* std_ext_p= */TRUE,
&use_default_version);
/* Find the default version if needed. */
if (use_default_version
&& rps->get_default_version != NULL)
rps->get_default_version ("i",
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, "i",
major_version, minor_version);
break;
case 'e':
p++;
p = riscv_parsing_subset_version (
rps,
march,
p, &major_version, &minor_version,
/* default_major_version= */ 1,
/* default_minor_version= */ 9,
/* std_ext_p= */TRUE);
p = riscv_parsing_subset_version (rps,
march,
++p,
&major_version,
&minor_version,
/* std_ext_p= */TRUE,
&use_default_version);
riscv_add_subset (rps->subset_list, "e", major_version, minor_version);
riscv_add_subset (rps->subset_list, "i", 2, 0);
/* Find the default version if needed. */
if (use_default_version
&& rps->get_default_version != NULL)
rps->get_default_version ("e",
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, "e",
major_version, minor_version);
/* i-ext must be enabled. */
if (rps->get_default_version != NULL)
rps->get_default_version ("i",
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, "i",
major_version, minor_version);
if (*rps->xlen > 32)
{
rps->error_handler ("-march=%s: rv%de is not a valid base ISA",
march, *rps->xlen);
rps->error_handler
(_("-march=%s: rv%de is not a valid base ISA"),
march, *rps->xlen);
return NULL;
}
break;
case 'g':
p++;
p = riscv_parsing_subset_version (
rps,
march,
p, &major_version, &minor_version,
/* default_major_version= */ 2,
/* default_minor_version= */ 0,
/* std_ext_p= */TRUE);
riscv_add_subset (rps->subset_list, "i", major_version, minor_version);
/* The g-ext shouldn't has the version, so we just
skip the setting if user set a version to it. */
p = riscv_parsing_subset_version (rps,
march,
++p,
&major_version,
&minor_version,
TRUE,
&use_default_version);
/* i-ext must be enabled. */
if (rps->get_default_version != NULL)
rps->get_default_version ("i",
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, "i",
major_version, minor_version);
for ( ; *std_exts != 'q'; std_exts++)
{
const char subset[] = {*std_exts, '\0'};
riscv_add_subset (
rps->subset_list, subset, major_version, minor_version);
if (rps->get_default_version != NULL)
rps->get_default_version (subset,
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, subset,
major_version, minor_version);
}
break;
default:
rps->error_handler (
"-march=%s: first ISA subset must be `e', `i' or `g'", march);
rps->error_handler
(_("-march=%s: first ISA subset must be `e', `i' or `g'"), march);
return NULL;
}
while (*p)
/* The riscv_parsing_subset_version may set `p` to NULL, so I think we should
skip parsing the string if `p` is NULL or value of `p` is `\0`. */
while (p != NULL && *p != '\0')
{
char subset[2] = {0, 0};
@ -1210,29 +1239,35 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
if (std_ext != *std_exts)
{
if (strchr (all_std_exts, std_ext) == NULL)
rps->error_handler (
"-march=%s: unsupported ISA subset `%c'", march, *p);
rps->error_handler
(_("-march=%s: unsupported ISA subset `%c'"), march, *p);
else
rps->error_handler (
"-march=%s: ISA string is not in canonical order. `%c'",
march, *p);
rps->error_handler
(_("-march=%s: ISA string is not in canonical order. `%c'"),
march, *p);
return NULL;
}
std_exts++;
p++;
p = riscv_parsing_subset_version (
rps,
march,
p, &major_version, &minor_version,
/* default_major_version= */ 2,
/* default_minor_version= */ 0,
/* std_ext_p= */TRUE);
use_default_version = FALSE;
subset[0] = std_ext;
p = riscv_parsing_subset_version (rps,
march,
++p,
&major_version,
&minor_version,
TRUE,
&use_default_version);
riscv_add_subset (rps->subset_list, subset, major_version, minor_version);
/* Find the default version if needed. */
if (use_default_version
&& rps->get_default_version != NULL)
rps->get_default_version (subset,
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, subset,
major_version, minor_version);
}
return p;
}
@ -1272,9 +1307,10 @@ typedef struct riscv_parse_config
} riscv_parse_config_t;
/* Parse a generic prefixed extension.
march: The full architecture string as passed in by "-march=...".
p: Point from which to start parsing the -march string.
config: What class of extensions to parse, predicate funcs,
`rps`: Hooks and status for parsing subset.
`march`: The full architecture string as passed in by "-march=...".
`p`: Point from which to start parsing the -march string.
`config`: What class of extensions to parse, predicate funcs,
and strings to use in error reporting. */
static const char *
@ -1287,6 +1323,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
unsigned minor_version = 0;
const char *last_name;
riscv_isa_ext_class_t class;
bfd_boolean use_default_version;
while (*p)
{
@ -1309,15 +1346,11 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
while (*++q != '\0' && *q != '_' && !ISDIGIT (*q))
;
use_default_version = FALSE;
end_of_version =
riscv_parsing_subset_version (
rps,
march,
q, &major_version, &minor_version,
/* default_major_version= */ 2,
/* default_minor_version= */ 0,
/* std_ext_p= */FALSE);
riscv_parsing_subset_version (rps, march, q, &major_version,
&minor_version, FALSE,
&use_default_version);
*q = '\0';
/* Check that the name is valid.
@ -1329,7 +1362,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
if (!config->ext_valid_p (subset))
{
rps->error_handler
("-march=%s: Invalid or unknown %s ISA extension: '%s'",
(_("-march=%s: Invalid or unknown %s ISA extension: '%s'"),
march, config->prefix, subset);
free (subset);
return NULL;
@ -1337,11 +1370,11 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
/* Check that the last item is not the same as this. */
last_name = rps->subset_list->tail->name;
if (!strcasecmp (last_name, subset))
{
rps->error_handler ("-march=%s: Duplicate %s ISA extension: \'%s\'",
march, config->prefix, subset);
rps->error_handler
(_("-march=%s: Duplicate %s ISA extension: \'%s\'"),
march, config->prefix, subset);
free (subset);
return NULL;
}
@ -1350,20 +1383,29 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
if (!strncasecmp (last_name, config->prefix, 1)
&& strcasecmp (last_name, subset) > 0)
{
rps->error_handler ("-march=%s: %s ISA extension not in alphabetical "
"order: \'%s\' must come before \'%s\'.",
march, config->prefix, subset, last_name);
rps->error_handler
(_("\
-march=%s: %s ISA extension not in alphabetical order: \'%s\' must come before \'%s\'."),
march, config->prefix, subset, last_name);
free (subset);
return NULL;
}
riscv_add_subset (rps->subset_list, subset, major_version, minor_version);
/* Find the default version if needed. */
if (use_default_version
&& rps->get_default_version != NULL)
rps->get_default_version (subset,
&major_version,
&minor_version);
riscv_add_subset (rps->subset_list, subset,
major_version, minor_version);
free (subset);
p += end_of_version - subset;
if (*p != '\0' && *p != '_')
{
rps->error_handler ("-march=%s: %s must separate with _",
rps->error_handler (_("-march=%s: %s must separate with _"),
march, config->prefix);
return NULL;
}
@ -1384,7 +1426,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
static const char * const riscv_std_z_ext_strtab[] =
{
NULL
"zicsr", NULL
};
/* Same as `riscv_std_z_ext_strtab', but for S-class extensions. */
@ -1478,8 +1520,9 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
}
else
{
rps->error_handler ("-march=%s: ISA string must begin with rv32 or rv64",
arch);
rps->error_handler
(_("-march=%s: ISA string must begin with rv32 or rv64"),
arch);
return FALSE;
}
@ -1490,7 +1533,6 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
return FALSE;
/* Parse the different classes of extensions in the specified order. */
for (i = 0; i < ARRAY_SIZE (parse_config); ++i) {
p = riscv_parse_prefixed_ext (rps, arch, p, &parse_config[i]);
@ -1500,7 +1542,7 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
if (*p != '\0')
{
rps->error_handler ("-march=%s: unexpected ISA string at end: %s",
rps->error_handler (_("-march=%s: unexpected ISA string at end: %s"),
arch, p);
return FALSE;
}
@ -1508,31 +1550,35 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
if (riscv_lookup_subset (rps->subset_list, "e")
&& riscv_lookup_subset (rps->subset_list, "f"))
{
rps->error_handler ("-march=%s: rv32e does not support the `f' extension",
arch);
rps->error_handler
(_("-march=%s: rv32e does not support the `f' extension"),
arch);
return FALSE;
}
if (riscv_lookup_subset (rps->subset_list, "d")
&& !riscv_lookup_subset (rps->subset_list, "f"))
{
rps->error_handler ("-march=%s: `d' extension requires `f' extension",
arch);
rps->error_handler
(_("-march=%s: `d' extension requires `f' extension"),
arch);
return FALSE;
}
if (riscv_lookup_subset (rps->subset_list, "q")
&& !riscv_lookup_subset (rps->subset_list, "d"))
{
rps->error_handler ("-march=%s: `q' extension requires `d' extension",
arch);
rps->error_handler
(_("-march=%s: `q' extension requires `d' extension"),
arch);
return FALSE;
}
if (riscv_lookup_subset (rps->subset_list, "q") && *rps->xlen < 64)
{
rps->error_handler ("-march=%s: rv32 does not support the `q' extension",
arch);
rps->error_handler
(_("-march=%s: rv32 does not support the `q' extension"),
arch);
return FALSE;
}
return TRUE;
@ -1543,7 +1589,8 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
void
riscv_add_subset (riscv_subset_list_t *subset_list,
const char *subset,
int major, int minor)
int major,
int minor)
{
riscv_subset_t *s = xmalloc (sizeof *s);
@ -1567,10 +1614,10 @@ riscv_subset_t *
riscv_lookup_subset (const riscv_subset_list_t *subset_list,
const char *subset)
{
return riscv_lookup_subset_version (
subset_list, subset,
RISCV_DONT_CARE_VERSION,
RISCV_DONT_CARE_VERSION);
return riscv_lookup_subset_version
(subset_list, subset,
RISCV_DONT_CARE_VERSION,
RISCV_DONT_CARE_VERSION);
}
/* Find subset in list with version checking, return NULL if not found. */
@ -1617,7 +1664,7 @@ riscv_release_subset_list (riscv_subset_list_t *subset_list)
/* Return the number of digits for the input. */
static size_t
size_t
riscv_estimate_digit (unsigned num)
{
size_t digit = 0;

6
bfd/elfxx-riscv.h
View File

@ -72,6 +72,9 @@ typedef struct {
void (*error_handler) (const char *,
...) ATTRIBUTE_PRINTF_1;
unsigned *xlen;
void (*get_default_version) (const char *,
unsigned int *,
unsigned int *);
} riscv_parse_subset_t;
extern bfd_boolean
@ -87,6 +90,9 @@ riscv_release_subset_list (riscv_subset_list_t *);
extern char *
riscv_arch_str (unsigned, const riscv_subset_list_t *);
extern size_t
riscv_estimate_digit (unsigned);
/* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z,
"xargs" corresponds to RV_ISA_CLASS_X, etc. Order is important
here. */

3189
bfd/po/bfd.pot
View File

File diff suppressed because it is too large Load Diff

4
binutils/ChangeLog
View File

@ -1,3 +1,7 @@
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* dwarf.c: Updated since DECLARE_CSR is changed.
2020-05-19 H.J. Lu <hjl.tools@gmail.com>
PR binutils/25809

3
binutils/dwarf.c
View File

@ -7409,7 +7409,8 @@ regname_internal_riscv (unsigned int regno)
document. */
switch (regno)
{
#define DECLARE_CSR(NAME,VALUE,CLASS) case VALUE + 4096: name = #NAME; break;
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
case VALUE + 4096: name = #NAME; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR

163
gas/ChangeLog
View File

@ -1,3 +1,166 @@
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
2020-05-19 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.

9
gas/config.in
View File

@ -53,9 +53,18 @@
/* Define to 1 if you want to fix Loongson3 LLSC Errata by default. */
#undef DEFAULT_MIPS_FIX_LOONGSON3_LLSC
/* Define default value for RISC-V -march. */
#undef DEFAULT_RISCV_ARCH_WITH_EXT
/* Define to 1 if you want to generate RISC-V arch attribute by default. */
#undef DEFAULT_RISCV_ATTR
/* Define default value for RISC-V -misa-spec. */
#undef DEFAULT_RISCV_ISA_SPEC
/* Define default value for RISC-V -mpriv-spec */
#undef DEFAULT_RISCV_PRIV_SPEC
/* Define to 1 if you want to generate GNU x86 used ISA and feature properties
by default. */
#undef DEFAULT_X86_USED_NOTE

514
gas/config/tc-riscv.c
View File

@ -63,7 +63,30 @@ struct riscv_cl_insn
#define DEFAULT_RISCV_ATTR 0
#endif
/* Let riscv_after_parse_args set the default value according to xlen. */
#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
#endif
/* The default ISA spec is set to 2.2 rather than the lastest version.
The reason is that compiler generates the ISA string with fixed 2p0
verisons only for the RISCV ELF architecture attributes, but not for
the -march option. Therefore, we should update the compiler or linker
to resolve this problem. */
#ifndef DEFAULT_RISCV_ISA_SPEC
#define DEFAULT_RISCV_ISA_SPEC "2.2"
#endif
#ifndef DEFAULT_RISCV_PRIV_SPEC
#define DEFAULT_RISCV_PRIV_SPEC "1.11"
#endif
static const char default_arch[] = DEFAULT_ARCH;
static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* width of an x-register */
static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
@ -74,6 +97,95 @@ static bfd_boolean rve_abi = FALSE;
static unsigned elf_flags = 0;
/* Set the default_isa_spec. Return 0 if the input spec string isn't
supported. Otherwise, return 1. */
static int
riscv_set_default_isa_spec (const char *s)
{
enum riscv_isa_spec_class class;
if (!riscv_get_isa_spec_class (s, &class))
{
as_bad ("Unknown default ISA spec `%s' set by "
"-misa-spec or --with-isa-spec", s);
return 0;
}
else
default_isa_spec = class;
return 1;
}
/* Set the default_priv_spec, assembler will find the suitable CSR address
according to default_priv_spec. We will try to check priv attributes if
the input string is NULL. Return 0 if the input priv spec string isn't
supported. Otherwise, return 1. */
static int
riscv_set_default_priv_spec (const char *s)
{
enum riscv_priv_spec_class class;
unsigned major, minor, revision;
obj_attribute *attr;
size_t buf_size;
char *buf;
/* Find the corresponding priv spec class. */
if (riscv_get_priv_spec_class (s, &class))
{
default_priv_spec = class;
return 1;
}
if (s != NULL)
{
as_bad (_("Unknown default privilege spec `%s' set by "
"-mpriv-spec or --with-priv-spec"), s);
return 0;
}
/* Try to set the default_priv_spec according to the priv attributes. */
attr = elf_known_obj_attributes_proc (stdoutput);
major = (unsigned) attr[Tag_RISCV_priv_spec].i;
minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
/* The priv attributes setting 0.0.0 is meaningless. We should have set
the default_priv_spec by md_parse_option and riscv_after_parse_args,
so just skip the following setting. */
if (major == 0 && minor == 0 && revision == 0)
return 1;
buf_size = riscv_estimate_digit (major)
+ 1 /* '.' */
+ riscv_estimate_digit (minor)
+ 1; /* string terminator */
if (revision != 0)
{
buf_size += 1 /* '.' */
+ riscv_estimate_digit (revision);
buf = xmalloc (buf_size);
snprintf (buf, buf_size, "%d.%d.%d", major, minor, revision);
}
else
{
buf = xmalloc (buf_size);
snprintf (buf, buf_size, "%d.%d", major, minor);
}
if (riscv_get_priv_spec_class (buf, &class))
{
default_priv_spec = class;
free (buf);
return 1;
}
/* Still can not find the priv spec class. */
as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
"privilege attributes"), major, minor, revision);
free (buf);
return 0;
}
/* This is the set of options which the .option pseudo-op may modify. */
struct riscv_set_options
@ -147,6 +259,67 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
}
}
/* Handle of the extension with version hash table. */
static struct hash_control *ext_version_hash = NULL;
static struct hash_control *
init_ext_version_hash (const struct riscv_ext_version *table)
{
int i = 0;
struct hash_control *hash = hash_new ();
while (table[i].name)
{
const char *name = table[i].name;
const char *hash_error =
hash_insert (hash, name, (void *) &table[i]);
if (hash_error != NULL)
{
fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
table[i].name, hash_error);
/* Probably a memory allocation problem? Give up now. */
as_fatal (_("Broken assembler. No assembly attempted."));
return NULL;
}
i++;
while (table[i].name
&& strcmp (table[i].name, name) == 0)
i++;
}
return hash;
}
static void
riscv_get_default_ext_version (const char *name,
unsigned int *major_version,
unsigned int *minor_version)
{
struct riscv_ext_version *ext;
*major_version = 0;
*minor_version = 0;
if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
return;
ext = (struct riscv_ext_version *) hash_find (ext_version_hash, name);
while (ext
&& ext->name
&& strcmp (ext->name, name) == 0)
{
if (ext->isa_spec_class == default_isa_spec)
{
*major_version = ext->major_version;
*minor_version = ext->minor_version;
return;
}
ext++;
}
}
/* Set which ISA and extensions are available. */
static void
@ -156,6 +329,10 @@ riscv_set_arch (const char *s)
rps.subset_list = &riscv_subsets;
rps.error_handler = as_fatal;
rps.xlen = &xlen;
rps.get_default_version = riscv_get_default_ext_version;
if (s == NULL)
return;
riscv_release_subset_list (&riscv_subsets);
riscv_parse_subset (&rps, s);
@ -194,8 +371,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Indicate we are already assemble any instructions or not. */
static bfd_boolean start_assemble = FALSE;
/* Indicate arch attribute is explictly set. */
static bfd_boolean explicit_arch_attr = FALSE;
/* Indicate ELF attributes are explictly set. */
static bfd_boolean explicit_attr = FALSE;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
@ -452,8 +629,9 @@ enum reg_class
{
RCLASS_GPR,
RCLASS_FPR,
RCLASS_CSR,
RCLASS_MAX
RCLASS_MAX,
RCLASS_CSR
};
static struct hash_control *reg_names_hash = NULL;
@ -483,102 +661,165 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
hash_reg_name (class, names[i], i);
}
/* All RISC-V CSRs belong to one of these classes. */
enum riscv_csr_class
{
CSR_CLASS_NONE,
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
};
/* This structure holds all restricted conditions for a CSR. */
struct riscv_csr_extra
{
/* Class to which this CSR belongs. Used to decide whether or
not this CSR is legal in the current -march context. */
enum riscv_csr_class csr_class;
};
/* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */
/* Init hash table csr_extra_hash to handle CSR. */
static void
riscv_init_csr_hashes (const char *name,
unsigned address,
enum riscv_csr_class class)
riscv_init_csr_hash (const char *name,
unsigned address,
enum riscv_csr_class class,
enum riscv_priv_spec_class define_version,
enum riscv_priv_spec_class abort_version)
{
struct riscv_csr_extra *entry = XNEW (struct riscv_csr_extra);
entry->csr_class = class;
struct riscv_csr_extra *entry, *pre_entry;
const char *hash_error = NULL;
bfd_boolean need_enrty = TRUE;
const char *hash_error =
hash_insert (csr_extra_hash, name, (void *) entry);
if (hash_error != NULL)
pre_entry = NULL;
entry = (struct riscv_csr_extra *) hash_find (csr_extra_hash, name);
while (need_enrty && entry != NULL)
{
fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
name, hash_error);
/* Probably a memory allocation problem? Give up now. */
as_fatal (_("Broken assembler. No assembly attempted."));
if (entry->csr_class == class
&& entry->address == address
&& entry->define_version == define_version
&& entry->abort_version == abort_version)
need_enrty = FALSE;
pre_entry = entry;
entry = entry->next;
}
/* Duplicate setting for the CSR, just return and do nothing. */
if (!need_enrty)
return;
hash_reg_name (RCLASS_CSR, name, address);
entry = XNEW (struct riscv_csr_extra);
entry->csr_class = class;
entry->address = address;
entry->define_version = define_version;
entry->abort_version = abort_version;
/* If the CSR hasn't been inserted in the hash table, then insert it.
Otherwise, attach the extra information to the entry which is already
in the hash table. */
if (pre_entry == NULL)
{
hash_error = hash_insert (csr_extra_hash, name, (void *) entry);
if (hash_error != NULL)
{
fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
name, hash_error);
/* Probably a memory allocation problem? Give up now. */
as_fatal (_("Broken assembler. No assembly attempted."));
}
}
else
pre_entry->next = entry;
}
/* Check wether the CSR is valid according to the ISA. */
static bfd_boolean
riscv_csr_class_check (enum riscv_csr_class csr_class)
static void
riscv_csr_class_check (const char *s,
enum riscv_csr_class csr_class)
{
bfd_boolean result = TRUE;
/* Don't check the ISA dependency when -mcsr-check isn't set. */
if (!riscv_opts.csr_check)
return;
switch (csr_class)
{
case CSR_CLASS_I: return riscv_subset_supports ("i");
case CSR_CLASS_F: return riscv_subset_supports ("f");
case CSR_CLASS_I:
result = riscv_subset_supports ("i");
break;
case CSR_CLASS_F:
result = riscv_subset_supports ("f");
break;
case CSR_CLASS_I_32:
return (xlen == 32 && riscv_subset_supports ("i"));
result = (xlen == 32 && riscv_subset_supports ("i"));
break;
default:
return FALSE;
as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
}
if (!result)
as_warn (_("Invalid CSR `%s' for the current ISA"), s);
}
/* Check and find the CSR address according to the privilege spec version. */
static void
riscv_csr_version_check (const char *csr_name,
struct riscv_csr_extra **entryP)
{
struct riscv_csr_extra *entry = *entryP;
while (entry != NULL)
{
if (default_priv_spec >= entry->define_version
&& default_priv_spec < entry->abort_version)
{
/* Find the suitable CSR according to the specific version. */
*entryP = entry;
return;
}
entry = entry->next;
}
/* We can not find the suitable CSR address according to the privilege
version. Therefore, we use the last defined value. Report the warning
only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
otherwise, you may get the unexpected CSR address. */
if (riscv_opts.csr_check)
{
const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
if (priv_name != NULL)
as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
csr_name, priv_name);
}
}
/* If the CSR is defined, then we call `riscv_csr_class_check` to do the
further checking. Return FALSE if the CSR is not defined. Otherwise,
return TRUE. */
/* Once the CSR is defined, including the old privilege spec, then we call
riscv_csr_class_check and riscv_csr_version_check to do the further checking
and get the corresponding address. Return -1 if the CSR is never been
defined. Otherwise, return the address. */
static bfd_boolean
static unsigned int
reg_csr_lookup_internal (const char *s)
{
struct riscv_csr_extra *r =
(struct riscv_csr_extra *) hash_find (csr_extra_hash, s);
if (r == NULL)
return FALSE;
return -1U;
/* We just report the warning when the CSR is invalid. */
if (!riscv_csr_class_check (r->csr_class))
as_warn (_("Invalid CSR `%s' for the current ISA"), s);
/* We just report the warning when the CSR is invalid. "Invalid CSR" means
the CSR was defined, but isn't allowed for the current ISA setting or
the privilege spec. If the CSR is never been defined, then assembler
will regard it as a "Unknown CSR" and report error. If user use number
to set the CSR, but over the range (> 0xfff), then assembler will report
"Improper CSR" error for it. */
riscv_csr_class_check (s, r->csr_class);
riscv_csr_version_check (s, &r);
return TRUE;
return r->address;
}
static unsigned int
reg_lookup_internal (const char *s, enum reg_class class)
{
void *r = hash_find (reg_names_hash, s);
void *r;
if (class == RCLASS_CSR)
return reg_csr_lookup_internal (s);
r = hash_find (reg_names_hash, s);
if (r == NULL || DECODE_REG_CLASS (r) != class)
return -1;
if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
return -1;
if (class == RCLASS_CSR
&& riscv_opts.csr_check
&& !reg_csr_lookup_internal (s))
return -1;
return DECODE_REG_NUM (r);
}
@ -862,8 +1103,10 @@ md_begin (void)
/* Create and insert CSR hash tables. */
csr_extra_hash = hash_new ();
#define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
#define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
#define DECLARE_CSR(name, num, class, define_version, abort_version) \
riscv_init_csr_hash (#name, num, class, define_version, abort_version);
#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
DECLARE_CSR(name, num, class, define_version, abort_version);
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
@ -2306,9 +2549,17 @@ md_assemble (char *str)
expressionS imm_expr;
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
/* The arch and priv attributes should be set before assembling. */
if (!start_assemble)
{
start_assemble = TRUE;
start_assemble = TRUE;
/* Set the default_priv_spec according to the priv attributes. */
if (!riscv_set_default_priv_spec (NULL))
return;
}
const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
if (error)
{
@ -2348,6 +2599,8 @@ enum options
OPTION_NO_ARCH_ATTR,
OPTION_CSR_CHECK,
OPTION_NO_CSR_CHECK,
OPTION_MISA_SPEC,
OPTION_MPRIV_SPEC,
OPTION_END_OF_ENUM
};
@ -2364,6 +2617,8 @@ struct option md_longopts[] =
{"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
{"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
{"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
{"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
{"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
{NULL, no_argument, NULL, 0}
};
@ -2392,7 +2647,9 @@ md_parse_option (int c, const char *arg)
switch (c)
{
case OPTION_MARCH:
riscv_set_arch (arg);
/* riscv_after_parse_args will call riscv_set_arch to parse
the architecture. */
default_arch_with_ext = arg;
break;
case OPTION_NO_PIC:
@ -2450,6 +2707,12 @@ md_parse_option (int c, const char *arg)
riscv_opts.csr_check = FALSE;
break;
case OPTION_MISA_SPEC:
return riscv_set_default_isa_spec (arg);
case OPTION_MPRIV_SPEC:
return riscv_set_default_priv_spec (arg);
default:
return 0;
}
@ -2460,6 +2723,10 @@ md_parse_option (int c, const char *arg)
void
riscv_after_parse_args (void)
{
/* The --with-arch is optional for now, so we have to set the xlen
according to the default_arch, which is set by the --targte, first.
Then, we use the xlen to set the default_arch_with_ext if the
-march and --with-arch are not set. */
if (xlen == 0)
{
if (strcmp (default_arch, "riscv32") == 0)
@ -2469,9 +2736,19 @@ riscv_after_parse_args (void)
else
as_bad ("unknown default architecture `%s'", default_arch);
}
if (default_arch_with_ext == NULL)
default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
if (riscv_subsets.head == NULL)
riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
/* Initialize the hash table for extensions with default version. */
ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
/* If the -misa-spec isn't set, then we set the default ISA spec according
to DEFAULT_RISCV_ISA_SPEC. */
if (default_isa_spec == ISA_SPEC_CLASS_NONE)
riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
/* Set the architecture according to -march or or --with-arch. */
riscv_set_arch (default_arch_with_ext);
/* Add the RVC extension, regardless of -march, to support .option rvc. */
riscv_set_rvc (FALSE);
@ -2483,6 +2760,11 @@ riscv_after_parse_args (void)
if (riscv_subset_supports ("e"))
riscv_set_rve (TRUE);
/* If the -mpriv-spec isn't set, then we set the default privilege spec
according to DEFAULT_PRIV_SPEC. */
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
/* Infer ABI from ISA if not specified on command line. */
if (abi_xlen == 0)
abi_xlen = xlen;
@ -3189,14 +3471,16 @@ md_show_usage (FILE *stream)
{
fprintf (stream, _("\
RISC-V options:\n\
-fpic generate position-independent code\n\
-fno-pic don't generate position-independent code (default)\n\
-march=ISA set the RISC-V architecture\n\
-mabi=ABI set the RISC-V ABI\n\
-mrelax enable relax (default)\n\
-mno-relax disable relax\n\
-march-attr generate RISC-V arch attribute\n\
-mno-arch-attr don't generate RISC-V arch attribute\n\
-fpic generate position-independent code\n\
-fno-pic don't generate position-independent code (default)\n\
-march=ISA set the RISC-V architecture\n\
-misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
-mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
-mabi=ABI set the RISC-V ABI\n\
-mrelax enable relax (default)\n\
-mno-relax disable relax\n\
-march-attr generate RISC-V arch attribute\n\
-mno-arch-attr don't generate RISC-V arch attribute\n\
"));
}
@ -3284,26 +3568,66 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
demand_empty_rest_of_line ();
}
/* Update arch attributes. */
/* Update arch and priv attributes. If we don't set the corresponding ELF
attributes, then try to output the default ones. */
static void
riscv_write_out_arch_attr (void)
riscv_write_out_attrs (void)
{
const char *arch_str = riscv_arch_str (xlen, &riscv_subsets);
const char *arch_str, *priv_str, *p;
/* versions[0] is major, versions[1] is minor,
and versions[3] is revision. */
unsigned versions[3] = {0}, number = 0;
unsigned int i;
/* Re-write arch attribute to normalize the arch string. */
arch_str = riscv_arch_str (xlen, &riscv_subsets);
bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
xfree ((void *)arch_str);
/* For the file without any instruction, we don't set the default_priv_spec
according to the priv attributes since the md_assemble isn't called.
Call riscv_set_default_priv_spec here for the above case, although
it seems strange. */
if (!start_assemble
&& !riscv_set_default_priv_spec (NULL))
return;
/* Re-write priv attributes by default_priv_spec. */
priv_str = riscv_get_priv_spec_name (default_priv_spec);
p = priv_str;
for (i = 0; *p; ++p)
{
if (*p == '.' && i < 3)
{
versions[i++] = number;
number = 0;
}
else if (ISDIGIT (*p))
number = (number * 10) + (*p - '0');
else
{
as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
return;
}
}
versions[i] = number;
/* Set the priv attributes. */
bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
}
/* Add the default contents for the .riscv.attributes section. */
/* Add the default contents for the .riscv.attributes section. If any
ELF attribute or -march-attr options is set, call riscv_write_out_attrs
to update the arch and priv attributes. */
static void
riscv_set_public_attributes (void)
{
if (riscv_opts.arch_attr || explicit_arch_attr)
/* Re-write arch attribute to normalize the arch string. */
riscv_write_out_arch_attr ();
if (riscv_opts.arch_attr || explicit_attr)
riscv_write_out_attrs ();
}
/* Called after all assembly has been done. */
@ -3357,13 +3681,14 @@ static void
s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
{
int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
unsigned old_xlen;
obj_attribute *attr;
if (tag == Tag_RISCV_arch)
explicit_attr = TRUE;
switch (tag)
{
unsigned old_xlen = xlen;
explicit_arch_attr = TRUE;
obj_attribute *attr;
case Tag_RISCV_arch:
old_xlen = xlen;
attr = elf_known_obj_attributes_proc (stdoutput);
if (!start_assemble)
riscv_set_arch (attr[Tag_RISCV_arch].s);
@ -3379,6 +3704,17 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
as_warn (_("Could not set architecture and machine"));
}
break;
case Tag_RISCV_priv_spec:
case Tag_RISCV_priv_spec_minor:
case Tag_RISCV_priv_spec_revision:
if (start_assemble)
as_fatal (_(".attribute priv spec must set before any instructions"));
break;
default:
break;
}
}

52
gas/configure vendored
View File

@ -13009,7 +13009,7 @@ $as_echo "#define NDS32_DEFAULT_ZOL_EXT 1" >>confdefs.h
$as_echo "$enable_zol_ext" >&6; }
;;
aarch64 | i386 | riscv | s390 | sparc)
aarch64 | i386 | s390 | sparc)
if test $this_target = $target ; then
cat >>confdefs.h <<_ACEOF
@ -13019,6 +13019,56 @@ _ACEOF
fi
;;
riscv)
# --target=riscv[32|64]-*-*. */
if test $this_target = $target ; then
cat >>confdefs.h <<_ACEOF
#define DEFAULT_ARCH "${arch}"
_ACEOF
fi
# --with-arch=<value>. The syntax of <value> is same as Gas option -march.
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-arch" >&5
$as_echo_n "checking for default configuration of --with-arch... " >&6; }
if test "x${with_arch}" != x; then
cat >>confdefs.h <<_ACEOF
#define DEFAULT_RISCV_ARCH_WITH_EXT "$with_arch"
_ACEOF
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_arch" >&5
$as_echo "$with_arch" >&6; }
# --with-isa-spec=[2.2|20190608|20191213].
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-isa-spec" >&5
$as_echo_n "checking for default configuration of --with-isa-spec... " >&6; }
if test "x${with_isa_spec}" != x; then
cat >>confdefs.h <<_ACEOF
#define DEFAULT_RISCV_ISA_SPEC "$with_isa_spec"
_ACEOF
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_isa_spec" >&5
$as_echo "$with_isa_spec" >&6; }
# --with-priv-spec=[1.9|1.9.1|1.10|1.11].
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-priv-spec" >&5
$as_echo_n "checking for default configuration of --with-priv-spec... " >&6; }
if test "x${with_priv_spec}" != x; then
cat >>confdefs.h <<_ACEOF
#define DEFAULT_RISCV_PRIV_SPEC "$with_priv_spec"
_ACEOF
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_priv_spec" >&5
$as_echo "$with_priv_spec" >&6; }
;;
rl78)
f=rl78-parse.o
case " $extra_objects " in

33
gas/configure.ac
View File

@ -569,12 +569,43 @@ changequote([,])dnl
AC_MSG_RESULT($enable_zol_ext)
;;
aarch64 | i386 | riscv | s390 | sparc)
aarch64 | i386 | s390 | sparc)
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
;;
riscv)
# --target=riscv[32|64]-*-*. */
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
# --with-arch=<value>. The syntax of <value> is same as Gas option -march.
AC_MSG_CHECKING(for default configuration of --with-arch)
if test "x${with_arch}" != x; then
AC_DEFINE_UNQUOTED(DEFAULT_RISCV_ARCH_WITH_EXT, "$with_arch",
[Define default value for RISC-V -march.])
fi
AC_MSG_RESULT($with_arch)
# --with-isa-spec=[2.2|20190608|20191213].
AC_MSG_CHECKING(for default configuration of --with-isa-spec)
if test "x${with_isa_spec}" != x; then
AC_DEFINE_UNQUOTED(DEFAULT_RISCV_ISA_SPEC, "$with_isa_spec",
[Define default value for RISC-V -misa-spec.])
fi
AC_MSG_RESULT($with_isa_spec)
# --with-priv-spec=[1.9|1.9.1|1.10|1.11].
AC_MSG_CHECKING(for default configuration of --with-priv-spec)
if test "x${with_priv_spec}" != x; then
AC_DEFINE_UNQUOTED(DEFAULT_RISCV_PRIV_SPEC, "$with_priv_spec",
[Define default value for RISC-V -mpriv-spec])
fi
AC_MSG_RESULT($with_priv_spec)
;;
rl78)
f=rl78-parse.o
case " $extra_objects " in

16
gas/doc/c-riscv.texi
View File

@ -42,6 +42,22 @@ Don't generate position-independent code (default)
@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima.
If this option and the architecture attributes aren’t set, then assembler
will check the default configure setting --with-arch=ISA.
@cindex @samp{-misa-spec=ISAspec} option, RISC-V
@item -misa-spec=ISAspec
Select the default isa spec version. If the version of ISA isn't set
by -march, then assembler helps to set the version according to
the default chosen spec. If this option isn't set, then assembler will
check the default configure setting --with-isa-spec=ISAspec.
@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
@item -mpriv-spec=PRIVspec
Select the privileged spec version. We can decide whether the CSR is valid or
not according to the chosen spec. If this option and the privilege attributes
aren't set, then assembler will check the default configure setting
--with-priv-spec=PRIVspec.
@cindex @samp{-mabi=ABI} option, RISC-V
@item -mabi=ABI

4558
gas/po/gas.pot
View File

File diff suppressed because it is too large Load Diff

5
gas/testsuite/gas/riscv/attribute-01.d
View File

@ -1,6 +1,9 @@
#as: -march=rv32g -march-attr
#as: -march=rv32g -march-attr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

7
gas/testsuite/gas/riscv/attribute-02.d
View File

@ -1,6 +1,9 @@
#as: -march=rv32gxargle -march-attr
#as: -march=rv32gxargle -march-attr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0"
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

7
gas/testsuite/gas/riscv/attribute-03.d
View File

@ -1,6 +1,9 @@
#as: -march=rv32gxargle_xfoo -march-attr
#as: -march=rv32gxargle_xfoo -march-attr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0_xfoo2p0"
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

5
gas/testsuite/gas/riscv/attribute-04.d
View File

@ -1,6 +1,9 @@
#as: -march-attr
#as: -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-04.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

6
gas/testsuite/gas/riscv/attribute-05.d
View File

@ -1,4 +1,4 @@
#as: -march-attr
#as: -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-05.s
Attribute Section: riscv
@ -7,5 +7,5 @@ File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 2
Tag_RISCV_priv_spec_revision: 3
Tag_RISCV_priv_spec_minor: 9
Tag_RISCV_priv_spec_revision: 1

4
gas/testsuite/gas/riscv/attribute-05.s
View File

@ -1,6 +1,6 @@
.attribute arch, "rv32g"
.attribute priv_spec, 1
.attribute priv_spec_minor, 2
.attribute priv_spec_revision, 3
.attribute priv_spec_minor, 9
.attribute priv_spec_revision, 1
.attribute unaligned_access, 1
.attribute stack_align, 16

5
gas/testsuite/gas/riscv/attribute-06.d
View File

@ -1,6 +1,9 @@
#as: -march=rv32g2p0 -march-attr
#as: -march=rv32g2p0 -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-06.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

5
gas/testsuite/gas/riscv/attribute-07.d
View File

@ -1,6 +1,9 @@
#as: -march=rv64g2p0 -march-attr
#as: -march=rv64g2p0 -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-07.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-08.d
View File

@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32e1p9"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

9
gas/testsuite/gas/riscv/attribute-09.d Normal file
View File

@ -0,0 +1,9 @@
#as: -march-attr -march=rv32i2p1m_zicsr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

9
gas/testsuite/gas/riscv/attribute-10.d Normal file
View File

@ -0,0 +1,9 @@
#as: -march-attr -march=rv32gc_zicsr -misa-spec=20191213
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-unknown.d
View File

@ -4,5 +4,8 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...
Tag_unknown_255: "test"
Tag_unknown_256: 123 \(0x7b\)

2
gas/testsuite/gas/riscv/csr-dw-regnums.d
View File

@ -1,4 +1,4 @@
#as: -march=rv32if
#as: -march=rv32if -mpriv-spec=1.11
#objdump: --dwarf=frames

2
gas/testsuite/gas/riscv/march-fail-s-with-version
View File

@ -1,2 +0,0 @@
Assembler messages:
.*: Invalid or unknown s ISA extension: 'sfoo'

2
gas/testsuite/gas/riscv/priv-reg-fail-fext.d
View File

@ -1,3 +1,3 @@
#as: -march=rv32i -mcsr-check
#as: -march=rv32i -mcsr-check -mpriv-spec=1.11
#source: priv-reg.s
#warning_output: priv-reg-fail-fext.l

25
gas/testsuite/gas/riscv/priv-reg-fail-fext.l
View File

@ -2,3 +2,28 @@
.*Warning: Invalid CSR `fflags' for the current ISA
.*Warning: Invalid CSR `frm' for the current ISA
.*Warning: Invalid CSR `fcsr' for the current ISA
.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'

2
gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
View File

@ -1,3 +1,3 @@
#as: -march=rv32if -mcsr-check
#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
#source: priv-reg-fail-read-only-01.s
#warning_output: priv-reg-fail-read-only-01.l

25
gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
View File

@ -67,3 +67,28 @@
.*Warning: Read-only CSR is written `csrw marchid,a1'
.*Warning: Read-only CSR is written `csrw mimpid,a1'
.*Warning: Read-only CSR is written `csrw mhartid,a1'
.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'

114
gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
View File

@ -1,7 +1,8 @@
.macro csr val
csrw \val, a1
.endm
# 1.9.1 registers
# Supported the current priv spec 1.11.
csr ustatus
csr uie
csr utvec
@ -9,7 +10,7 @@
csr uscratch
csr uepc
csr ucause
csr ubadaddr
csr utval # Added in 1.10
csr uip
csr fflags
@ -86,26 +87,15 @@
csr sideleg
csr sie
csr stvec
csr scounteren # Added in 1.10
csr sscratch
csr sepc
csr scause
csr sbadaddr
csr stval # Added in 1.10
csr sip
csr sptbr
csr hstatus
csr hedeleg
csr hideleg
csr hie
csr htvec
csr hscratch
csr hepc
csr hcause
csr hbadaddr
csr hip
csr satp # Added in 1.10
csr mvendorid
csr marchid
@ -113,24 +103,39 @@
csr mhartid
csr mstatus
csr misa
csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
csr medeleg
csr mideleg
csr mie
csr mtvec
csr mcounteren # Added in 1.10
csr mscratch
csr mepc
csr mcause
csr mbadaddr
csr mtval # Added in 1.10
csr mip
csr mbase
csr mbound
csr mibase
csr mibound
csr mdbase
csr mdbound
csr pmpcfg0 # Added in 1.10
csr pmpcfg1 # Added in 1.10
csr pmpcfg2 # Added in 1.10
csr pmpcfg3 # Added in 1.10
csr pmpaddr0 # Added in 1.10
csr pmpaddr1 # Added in 1.10
csr pmpaddr2 # Added in 1.10
csr pmpaddr3 # Added in 1.10
csr pmpaddr4 # Added in 1.10
csr pmpaddr5 # Added in 1.10
csr pmpaddr6 # Added in 1.10
csr pmpaddr7 # Added in 1.10
csr pmpaddr8 # Added in 1.10
csr pmpaddr9 # Added in 1.10
csr pmpaddr10 # Added in 1.10
csr pmpaddr11 # Added in 1.10
csr pmpaddr12 # Added in 1.10
csr pmpaddr13 # Added in 1.10
csr pmpaddr14 # Added in 1.10
csr pmpaddr15 # Added in 1.10
csr mcycle
csr minstret
@ -195,10 +200,7 @@
csr mhpmcounter30h
csr mhpmcounter31h
csr mucounteren
csr mscounteren
csr mhcounteren
csr mcountinhibit # Added in 1.11
csr mhpmevent3
csr mhpmevent4
csr mhpmevent5
@ -236,34 +238,32 @@
csr dcsr
csr dpc
csr dscratch
# 1.10 registers
csr utval
csr dscratch0 # Added in 1.11
csr dscratch1 # Added in 1.11
csr scounteren
csr stval
csr satp
# Supported in previous priv spec, but dropped now.
csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
csr mcounteren
csr mtval
csr pmpcfg0
csr pmpcfg1
csr pmpcfg2
csr pmpcfg3
csr pmpaddr0
csr pmpaddr1
csr pmpaddr2
csr pmpaddr3
csr pmpaddr4
csr pmpaddr5
csr pmpaddr6
csr pmpaddr7
csr pmpaddr8
csr pmpaddr9
csr pmpaddr10
csr pmpaddr11
csr pmpaddr12
csr pmpaddr13
csr pmpaddr14
csr pmpaddr15
csr hstatus # 0x200, dropped in 1.10
csr hedeleg # 0x202, dropped in 1.10
csr hideleg # 0x203, dropped in 1.10
csr hie # 0x204, dropped in 1.10
csr htvec # 0x205, dropped in 1.10
csr hscratch # 0x240, dropped in 1.10
csr hepc # 0x241, dropped in 1.10
csr hcause # 0x242, dropped in 1.10
csr hbadaddr # 0x243, dropped in 1.10
csr hip # 0x244, dropped in 1.10
csr mbase # 0x380, dropped in 1.10
csr mbound # 0x381, dropped in 1.10
csr mibase # 0x382, dropped in 1.10
csr mibound # 0x383, dropped in 1.10
csr mdbase # 0x384, dropped in 1.10
csr mdbound # 0x385, dropped in 1.10
csr mscounteren # 0x321, dropped in 1.10
csr mhcounteren # 0x322, dropped in 1.10

2
gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
View File

@ -1,3 +1,3 @@
#as: -march=rv32if -mcsr-check
#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
#source: priv-reg-fail-read-only-02.s
#warning_output: priv-reg-fail-read-only-02.l

2
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
View File

@ -1,3 +1,3 @@
#as: -march=rv64if -mcsr-check
#as: -march=rv64if -mcsr-check -mpriv-spec=1.11
#source: priv-reg.s
#warning_output: priv-reg-fail-rv32-only.l

25
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
View File

@ -64,3 +64,28 @@
.*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'

11
gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d Normal file
View File

@ -0,0 +1,11 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p10.l
#readelf: -A
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 10
#...

27
gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l Normal file
View File

@ -0,0 +1,27 @@
.*Assembler messages:
.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.10'
.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.10'
.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.10'
.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.10'
.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.10'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.10'
.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.10'
.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.10'
.*Warning: Invalid CSR `hstatus' for the privilege spec `1.10'
.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.10'
.*Warning: Invalid CSR `hideleg' for the privilege spec `1.10'
.*Warning: Invalid CSR `hie' for the privilege spec `1.10'
.*Warning: Invalid CSR `htvec' for the privilege spec `1.10'
.*Warning: Invalid CSR `hscratch' for the privilege spec `1.10'
.*Warning: Invalid CSR `hepc' for the privilege spec `1.10'
.*Warning: Invalid CSR `hcause' for the privilege spec `1.10'
.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.10'
.*Warning: Invalid CSR `hip' for the privilege spec `1.10'
.*Warning: Invalid CSR `mbase' for the privilege spec `1.10'
.*Warning: Invalid CSR `mbound' for the privilege spec `1.10'
.*Warning: Invalid CSR `mibase' for the privilege spec `1.10'
.*Warning: Invalid CSR `mibound' for the privilege spec `1.10'
.*Warning: Invalid CSR `mdbase' for the privilege spec `1.10'
.*Warning: Invalid CSR `mdbound' for the privilege spec `1.10'
.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.10'
.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.10'

11
gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d Normal file
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@ -0,0 +1,11 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p11.l
#readelf: -A
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 11
#...

25
gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l Normal file
View File

@ -0,0 +1,25 @@
.*Assembler messages:
.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'

11
gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d Normal file
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@ -0,0 +1,11 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.9 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9.l
#readelf: -A
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 9
#...

30
gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l Normal file
View File

@ -0,0 +1,30 @@
.*Assembler messages:
.*Warning: Invalid CSR `utval' for the privilege spec `1.9'
.*Warning: Invalid CSR `scounteren' for the privilege spec `1.9'
.*Warning: Invalid CSR `stval' for the privilege spec `1.9'
.*Warning: Invalid CSR `satp' for the privilege spec `1.9'
.*Warning: Invalid CSR `mcounteren' for the privilege spec `1.9'
.*Warning: Invalid CSR `mtval' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpcfg0' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpcfg1' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpcfg2' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpcfg3' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr0' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr1' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr2' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr3' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr4' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr5' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr6' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr7' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr8' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr9' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr10' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr11' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr12' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr13' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9'
.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9'
.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9'
.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9'
.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9'

12
gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9p1.l
#readelf: -A
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 9
Tag_RISCV_priv_spec_revision: 1
#...

30
gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l Normal file
View File

@ -0,0 +1,30 @@
.*Assembler messages:
.*Warning: Invalid CSR `utval' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `scounteren' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `stval' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `satp' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `mcounteren' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `mtval' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpcfg0' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpcfg1' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpcfg2' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpcfg3' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr0' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr1' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr2' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr3' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr4' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr5' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr6' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr7' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr8' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr9' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr10' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr11' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr12' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr13' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9.1'

257
gas/testsuite/gas/riscv/priv-reg-version-1p10.d Normal file
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@ -0,0 +1,257 @@
#as: -march=rv32if -mpriv-spec=1.10
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.10
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320
[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,0x7b3
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203
[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204
[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205
[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240
[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241
[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242
[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243
[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244
[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380
[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381
[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382
[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,0x383
[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,0x384
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,0x321
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,0x322

257
gas/testsuite/gas/riscv/priv-reg-version-1p11.d Normal file
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@ -0,0 +1,257 @@
#as: -march=rv32if -mpriv-spec=1.11
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.11
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203
[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204
[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205
[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240
[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241
[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242
[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243
[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244
[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380
[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381
[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382
[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,0x383
[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,0x384
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,0x321
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,0x322

257
gas/testsuite/gas/riscv/priv-reg-version-1p9.d Normal file
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@ -0,0 +1,257 @@
#as: -march=rv32if -mpriv-spec=1.9
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.9
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,0x106
[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr
[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
[ ]+[0-9a-f]+:[ ]+f1002573[ ]+csrr[ ]+a0,misa
[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,0x306
[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,0x3a0
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,0x3a1
[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,0x3a2
[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,0x3a3
[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,0x3b0
[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,0x3b1
[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,0x3b2
[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,0x3b3
[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,0x3b4
[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,0x3b5
[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,0x3b6
[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,0x3b7
[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,0x3b8
[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,0x3b9
[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,0x3ba
[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,0x3bb
[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,0x3bc
[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,0x3bd
[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,0x3be
[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,0x3bf
[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,0x7b3
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren

257
gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d Normal file
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@ -0,0 +1,257 @@
#as: -march=rv32if -mpriv-spec=1.9.1
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.9.1
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,0x106
[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr
[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,0x306
[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,0x3a0
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,0x3a1
[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,0x3a2
[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,0x3a3
[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,0x3b0
[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,0x3b1
[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,0x3b2
[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,0x3b3
[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,0x3b4
[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,0x3b5
[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,0x3b6
[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,0x3b7
[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,0x3b8
[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,0x3b9
[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,0x3ba
[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,0x3bb
[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,0x3bc
[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,0x3bd
[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,0x3be
[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,0x3bf
[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,0x7b3
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren

256
gas/testsuite/gas/riscv/priv-reg.d
View File

@ -1,256 +0,0 @@
#as: -march=rv32if
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren

6
gdb/riscv-tdep.c
View File

@ -240,7 +240,7 @@ static struct riscv_register_feature riscv_csr_feature =
{
"org.gnu.gdb.riscv.csr",
{
#define DECLARE_CSR(NAME,VALUE,CLASS) \
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
{ RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
@ -498,7 +498,7 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
{
#define DECLARE_CSR(NAME,VALUE,CLASS) \
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
case RISCV_ ## VALUE ## _REGNUM: return # NAME;
switch (regnum)
@ -828,7 +828,7 @@ riscv_is_regnum_a_named_csr (int regnum)
switch (regnum)
{
#define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM:
#define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
return true;

2
gdb/riscv-tdep.h
View File

@ -44,7 +44,7 @@ enum
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
#define DECLARE_CSR(name, num, class) \
#define DECLARE_CSR(name, num, class, define_version, abort_version) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR

20
include/ChangeLog
View File

@ -1,3 +1,23 @@
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
2020-05-19 Alexander Fedotov <alfedotov@gmail.com>
PR 25992

509
include/opcode/riscv-opc.h
View File

@ -656,7 +656,6 @@
#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
/* scounteren is present int priv spec 1.10. */
#define CSR_SCOUNTEREN 0x106
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
@ -669,20 +668,17 @@
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_MSTATUS 0x300
/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
/* mcounteren is present in priv spec 1.10. */
#define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
@ -765,7 +761,6 @@
#define CSR_MHPMCOUNTER29H 0xb9d
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
/* mcountinhibit is present in priv spec 1.11. */
#define CSR_MCOUNTINHIBIT 0x320
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
@ -802,10 +797,8 @@
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
/* dscratch0 and dscratch1 are present in priv spec 1.11. */
#define CSR_DSCRATCH0 0x7b2
#define CSR_DSCRATCH1 0x7b3
/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
#define CSR_HSTATUS 0x200
#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
@ -1124,262 +1117,256 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
#endif
#ifdef DECLARE_CSR
DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I)
DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I)
DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I)
DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I)
DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I)
DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I)
DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I)
DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I)
DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F)
DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F)
DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F)
DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I)
DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I)
DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I)
DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I)
DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I)
DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I)
DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I)
DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I)
DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I)
DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I)
DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I)
DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I)
DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I)
DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I)
DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I)
DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I)
DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I)
DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I)
DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I)
DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I)
DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I)
DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I)
DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I)
DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I)
DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I)
DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I)
DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I)
DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I)
DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I)
DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I)
DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I)
DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I)
DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32)
DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32)
DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32)
DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32)
DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I)
DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I)
DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I)
DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I)
DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I)
DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I)
DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I)
DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I)
DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I)
DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I)
DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I)
DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I)
DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I)
DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I)
DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I)
DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I)
DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I)
DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I)
DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I)
DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I)
DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I)
DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I)
DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I)
DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I)
DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I)
DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I)
DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I)
DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32)
DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I)
DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32)
DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I)
DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I)
DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I)
DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I)
DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I)
DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I)
DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I)
DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I)
DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I)
DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I)
DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I)
DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I)
DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I)
DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I)
DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I)
DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I)
DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I)
DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I)
DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I)
DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32)
DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I)
DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I)
DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I)
DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I)
DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I)
DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I)
DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I)
DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I)
DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I)
DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I)
DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I)
DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I)
DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I)
DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I)
DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I)
DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I)
DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I)
DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I)
DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I)
DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I)
DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I)
DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I)
DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I)
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I)
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I)
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I)
DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I)
DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I)
DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I)
DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I)
DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I)
DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I)
DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I)
DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I)
DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I)
DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I)
DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I)
DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I)
DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
#endif
#ifdef DECLARE_CSR_ALIAS
/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I)
/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1)
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)

76
include/opcode/riscv.h
View File

@ -24,6 +24,7 @@
#include "riscv-opc.h"
#include <stdlib.h>
#include <stdint.h>
#include "bfd.h"
typedef uint64_t insn_t;
@ -343,6 +344,73 @@ struct riscv_opcode
unsigned long pinfo;
};
/* The current supported ISA spec versions. */
enum riscv_isa_spec_class
{
ISA_SPEC_CLASS_NONE,
ISA_SPEC_CLASS_2P2,
ISA_SPEC_CLASS_20190608,
ISA_SPEC_CLASS_20191213
};
/* This structure holds version information for specific ISA. */
struct riscv_ext_version
{
const char *name;
enum riscv_isa_spec_class isa_spec_class;
unsigned int major_version;
unsigned int minor_version;
};
/* All RISC-V CSR belong to one of these classes. */
enum riscv_csr_class
{
CSR_CLASS_NONE,
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
};
/* The current supported privilege spec versions. */
enum riscv_priv_spec_class
{
PRIV_SPEC_CLASS_NONE,
PRIV_SPEC_CLASS_1P9,
PRIV_SPEC_CLASS_1P9P1,
PRIV_SPEC_CLASS_1P10,
PRIV_SPEC_CLASS_1P11,
PRIV_SPEC_CLASS_DRAFT
};
/* This structure holds all restricted conditions for a CSR. */
struct riscv_csr_extra
{
/* Class to which this CSR belongs. Used to decide whether or
not this CSR is legal in the current -march context. */
enum riscv_csr_class csr_class;
/* CSR may have differnet numbers in the previous priv spec. */
unsigned address;
/* Record the CSR is defined/valid in which versions. */
enum riscv_priv_spec_class define_version;
/* Record the CSR is aborted/invalid from which versions. If it isn't
aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
enum riscv_priv_spec_class abort_version;
/* The CSR may have more than one setting. */
struct riscv_csr_extra *next;
};
/* Instruction is a simple alias (e.g. "mv" for "addi"). */
#define INSN_ALIAS 0x00000001
@ -420,5 +488,13 @@ extern const char * const riscv_fpr_names_abi[NFPR];
extern const struct riscv_opcode riscv_opcodes[];
extern const struct riscv_opcode riscv_insn_types[];
extern const struct riscv_ext_version riscv_ext_version_table[];
extern bfd_boolean
riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
extern bfd_boolean
riscv_get_priv_spec_class (const char *, enum riscv_priv_spec_class *);
extern const char *
riscv_get_priv_spec_name (enum riscv_priv_spec_class);
#endif /* _RISCV_H_ */

16
ld/ChangeLog
View File

@ -1,3 +1,19 @@
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
2020-05-20 Alan Modra <amodra@gmail.com>
PR 25993

3
ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
View File

@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
View File

@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
View File

@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

4
ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
View File

@ -1,3 +1,3 @@
.attribute priv_spec, 1
.attribute priv_spec_minor, 2
.attribute priv_spec_revision, 3
.attribute priv_spec_minor, 9
.attribute priv_spec_revision, 1

4
ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
View File

@ -1,3 +1,3 @@
.attribute priv_spec, 1
.attribute priv_spec_minor, 2
.attribute priv_spec_revision, 3
.attribute priv_spec_minor, 9
.attribute priv_spec_revision, 1

4
ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
View File

@ -8,5 +8,5 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 2
Tag_RISCV_priv_spec_revision: 3
Tag_RISCV_priv_spec_minor: 9
Tag_RISCV_priv_spec_revision: 1

3
ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
View File

@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
View File

@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
View File

@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
View File

@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
View File

@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
View File

@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

31
opcodes/ChangeLog
View File

@ -1,3 +1,34 @@
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
2020-05-19 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new

139
opcodes/po/opcodes.pot
View File

@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
"POT-Creation-Date: 2020-04-30 13:57+0100\n"
"POT-Creation-Date: 2020-05-20 15:53+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@ -75,7 +75,7 @@ msgid ""
msgstr ""
#: aarch64-dis.c:3552 mips-dis.c:2778 mips-dis.c:2788 mips-dis.c:2791
#: nfp-dis.c:2981 riscv-dis.c:556
#: nfp-dis.c:2981 riscv-dis.c:616
#, c-format
msgid "\n"
msgstr ""
@ -663,7 +663,7 @@ msgstr ""
#: bpf-asm.c:181 epiphany-asm.c:456 fr30-asm.c:311 frv-asm.c:1264
#: ip2k-asm.c:512 iq2000-asm.c:460 lm32-asm.c:350 m32c-asm.c:1585
#: m32r-asm.c:329 mep-asm.c:1288 mt-asm.c:596 or1k-asm.c:580 xc16x-asm.c:377
#: m32r-asm.c:329 mep-asm.c:1288 mt-asm.c:596 or1k-asm.c:571 xc16x-asm.c:377
#: xstormy16-asm.c:277
#, c-format
msgid "internal error: unrecognized field %d while parsing"
@ -671,7 +671,7 @@ msgstr ""
#: bpf-asm.c:233 epiphany-asm.c:508 fr30-asm.c:363 frv-asm.c:1316
#: ip2k-asm.c:564 iq2000-asm.c:512 lm32-asm.c:402 m32c-asm.c:1637
#: m32r-asm.c:381 mep-asm.c:1340 mt-asm.c:648 or1k-asm.c:632 xc16x-asm.c:429
#: m32r-asm.c:381 mep-asm.c:1340 mt-asm.c:648 or1k-asm.c:623 xc16x-asm.c:429
#: xstormy16-asm.c:329
msgid "missing mnemonic in syntax string"
msgstr ""
@ -686,8 +686,8 @@ msgstr ""
#: m32c-asm.c:1772 m32c-asm.c:1776 m32c-asm.c:1865 m32c-asm.c:1972
#: m32r-asm.c:516 m32r-asm.c:520 m32r-asm.c:609 m32r-asm.c:716 mep-asm.c:1475
#: mep-asm.c:1479 mep-asm.c:1568 mep-asm.c:1675 mt-asm.c:783 mt-asm.c:787
#: mt-asm.c:876 mt-asm.c:983 or1k-asm.c:767 or1k-asm.c:771 or1k-asm.c:860
#: or1k-asm.c:967 xc16x-asm.c:564 xc16x-asm.c:568 xc16x-asm.c:657
#: mt-asm.c:876 mt-asm.c:983 or1k-asm.c:758 or1k-asm.c:762 or1k-asm.c:851
#: or1k-asm.c:958 xc16x-asm.c:564 xc16x-asm.c:568 xc16x-asm.c:657
#: xc16x-asm.c:764 xstormy16-asm.c:464 xstormy16-asm.c:468 xstormy16-asm.c:557
#: xstormy16-asm.c:664
msgid "unrecognized instruction"
@ -695,7 +695,7 @@ msgstr ""
#: bpf-asm.c:415 epiphany-asm.c:690 fr30-asm.c:545 frv-asm.c:1498
#: ip2k-asm.c:746 iq2000-asm.c:694 lm32-asm.c:584 m32c-asm.c:1819
#: m32r-asm.c:563 mep-asm.c:1522 mt-asm.c:830 or1k-asm.c:814 xc16x-asm.c:611
#: m32r-asm.c:563 mep-asm.c:1522 mt-asm.c:830 or1k-asm.c:805 xc16x-asm.c:611
#: xstormy16-asm.c:511
#, c-format
msgid "syntax error (expected char `%c', found `%c')"
@ -703,7 +703,7 @@ msgstr ""
#: bpf-asm.c:425 epiphany-asm.c:700 fr30-asm.c:555 frv-asm.c:1508
#: ip2k-asm.c:756 iq2000-asm.c:704 lm32-asm.c:594 m32c-asm.c:1829
#: m32r-asm.c:573 mep-asm.c:1532 mt-asm.c:840 or1k-asm.c:824 xc16x-asm.c:621
#: m32r-asm.c:573 mep-asm.c:1532 mt-asm.c:840 or1k-asm.c:815 xc16x-asm.c:621
#: xstormy16-asm.c:521
#, c-format
msgid "syntax error (expected char `%c', found end of instruction)"
@ -711,21 +711,21 @@ msgstr ""
#: bpf-asm.c:455 epiphany-asm.c:730 fr30-asm.c:585 frv-asm.c:1538
#: ip2k-asm.c:786 iq2000-asm.c:734 lm32-asm.c:624 m32c-asm.c:1859
#: m32r-asm.c:603 mep-asm.c:1562 mt-asm.c:870 or1k-asm.c:854 xc16x-asm.c:651
#: m32r-asm.c:603 mep-asm.c:1562 mt-asm.c:870 or1k-asm.c:845 xc16x-asm.c:651
#: xstormy16-asm.c:551
msgid "junk at end of line"
msgstr ""
#: bpf-asm.c:567 epiphany-asm.c:842 fr30-asm.c:697 frv-asm.c:1650
#: ip2k-asm.c:898 iq2000-asm.c:846 lm32-asm.c:736 m32c-asm.c:1971
#: m32r-asm.c:715 mep-asm.c:1674 mt-asm.c:982 or1k-asm.c:966 xc16x-asm.c:763
#: m32r-asm.c:715 mep-asm.c:1674 mt-asm.c:982 or1k-asm.c:957 xc16x-asm.c:763
#: xstormy16-asm.c:663
msgid "unrecognized form of instruction"
msgstr ""
#: bpf-asm.c:581 epiphany-asm.c:856 fr30-asm.c:711 frv-asm.c:1664
#: ip2k-asm.c:912 iq2000-asm.c:860 lm32-asm.c:750 m32c-asm.c:1985
#: m32r-asm.c:729 mep-asm.c:1688 mt-asm.c:996 or1k-asm.c:980 xc16x-asm.c:777
#: m32r-asm.c:729 mep-asm.c:1688 mt-asm.c:996 or1k-asm.c:971 xc16x-asm.c:777
#: xstormy16-asm.c:677
#, c-format
msgid "bad instruction `%.50s...'"
@ -733,7 +733,7 @@ msgstr ""
#: bpf-asm.c:584 epiphany-asm.c:859 fr30-asm.c:714 frv-asm.c:1667
#: ip2k-asm.c:915 iq2000-asm.c:863 lm32-asm.c:753 m32c-asm.c:1988
#: m32r-asm.c:732 mep-asm.c:1691 mt-asm.c:999 or1k-asm.c:983 xc16x-asm.c:780
#: m32r-asm.c:732 mep-asm.c:1691 mt-asm.c:999 or1k-asm.c:974 xc16x-asm.c:780
#: xstormy16-asm.c:680
#, c-format
msgid "bad instruction `%.50s'"
@ -766,7 +766,7 @@ msgstr ""
#: bpf-dis.c:203 epiphany-dis.c:279 fr30-dis.c:300 frv-dis.c:397 ip2k-dis.c:289
#: iq2000-dis.c:190 lm32-dis.c:148 m32c-dis.c:892 m32r-dis.c:280 mep-dis.c:1188
#: mt-dis.c:291 or1k-dis.c:184 xc16x-dis.c:421 xstormy16-dis.c:169
#: mt-dis.c:291 or1k-dis.c:175 xc16x-dis.c:421 xstormy16-dis.c:169
#, c-format
msgid "internal error: unrecognized field %d while printing insn"
msgstr ""
@ -797,7 +797,7 @@ msgstr ""
#: bpf-ibld.c:628 epiphany-ibld.c:883 fr30-ibld.c:738 frv-ibld.c:864
#: ip2k-ibld.c:615 iq2000-ibld.c:721 lm32-ibld.c:642 m32c-ibld.c:1739
#: m32r-ibld.c:673 mep-ibld.c:1216 mt-ibld.c:757 or1k-ibld.c:745
#: m32r-ibld.c:673 mep-ibld.c:1216 mt-ibld.c:757 or1k-ibld.c:736
#: xc16x-ibld.c:760 xstormy16-ibld.c:686
#, c-format
msgid "internal error: unrecognized field %d while building insn"
@ -805,7 +805,7 @@ msgstr ""
#: bpf-ibld.c:712 epiphany-ibld.c:1178 fr30-ibld.c:944 frv-ibld.c:1182
#: ip2k-ibld.c:691 iq2000-ibld.c:897 lm32-ibld.c:747 m32c-ibld.c:2901
#: m32r-ibld.c:811 mep-ibld.c:1816 mt-ibld.c:978 or1k-ibld.c:913
#: m32r-ibld.c:811 mep-ibld.c:1816 mt-ibld.c:978 or1k-ibld.c:895
#: xc16x-ibld.c:981 xstormy16-ibld.c:833
#, c-format
msgid "internal error: unrecognized field %d while decoding insn"
@ -813,7 +813,7 @@ msgstr ""
#: bpf-ibld.c:781 epiphany-ibld.c:1322 fr30-ibld.c:1091 frv-ibld.c:1461
#: ip2k-ibld.c:766 iq2000-ibld.c:1029 lm32-ibld.c:837 m32c-ibld.c:3519
#: m32r-ibld.c:925 mep-ibld.c:2287 mt-ibld.c:1179 or1k-ibld.c:1018
#: m32r-ibld.c:925 mep-ibld.c:2287 mt-ibld.c:1179 or1k-ibld.c:991
#: xc16x-ibld.c:1203 xstormy16-ibld.c:944
#, c-format
msgid "internal error: unrecognized field %d while getting int operand"
@ -821,7 +821,7 @@ msgstr ""
#: bpf-ibld.c:832 epiphany-ibld.c:1448 fr30-ibld.c:1220 frv-ibld.c:1722
#: ip2k-ibld.c:823 iq2000-ibld.c:1143 lm32-ibld.c:909 m32c-ibld.c:4119
#: m32r-ibld.c:1021 mep-ibld.c:2740 mt-ibld.c:1362 or1k-ibld.c:1105
#: m32r-ibld.c:1021 mep-ibld.c:2740 mt-ibld.c:1362 or1k-ibld.c:1069
#: xc16x-ibld.c:1407 xstormy16-ibld.c:1037
#, c-format
msgid "internal error: unrecognized field %d while getting vma operand"
@ -829,7 +829,7 @@ msgstr ""
#: bpf-ibld.c:890 epiphany-ibld.c:1581 fr30-ibld.c:1352 frv-ibld.c:1990
#: ip2k-ibld.c:883 iq2000-ibld.c:1264 lm32-ibld.c:988 m32c-ibld.c:4707
#: m32r-ibld.c:1123 mep-ibld.c:3154 mt-ibld.c:1552 or1k-ibld.c:1199
#: m32r-ibld.c:1123 mep-ibld.c:3154 mt-ibld.c:1552 or1k-ibld.c:1154
#: xc16x-ibld.c:1612 xstormy16-ibld.c:1137
#, c-format
msgid "internal error: unrecognized field %d while setting int operand"
@ -837,7 +837,7 @@ msgstr ""
#: bpf-ibld.c:938 epiphany-ibld.c:1704 fr30-ibld.c:1474 frv-ibld.c:2248
#: ip2k-ibld.c:933 iq2000-ibld.c:1375 lm32-ibld.c:1057 m32c-ibld.c:5285
#: m32r-ibld.c:1215 mep-ibld.c:3558 mt-ibld.c:1732 or1k-ibld.c:1283
#: m32r-ibld.c:1215 mep-ibld.c:3558 mt-ibld.c:1732 or1k-ibld.c:1229
#: xc16x-ibld.c:1807 xstormy16-ibld.c:1227
#, c-format
msgid "internal error: unrecognized field %d while setting vma operand"
@ -1881,29 +1881,29 @@ msgstr ""
msgid "internal relocation type invalid"
msgstr ""
#: or1k-desc.c:2213
#: or1k-desc.c:2040
#, c-format
msgid ""
"internal error: or1k_cgen_rebuild_tables: conflicting insn-chunk-bitsize "
"values: `%d' vs. `%d'"
msgstr ""
#: or1k-desc.c:2296
#: or1k-desc.c:2123
#, c-format
msgid "internal error: or1k_cgen_cpu_open: unsupported argument `%d'"
msgstr ""
#: or1k-desc.c:2315
#: or1k-desc.c:2142
#, c-format
msgid "internal error: or1k_cgen_cpu_open: no endianness specified"
msgstr ""
#: ppc-dis.c:376
#: ppc-dis.c:381
#, c-format
msgid "warning: ignoring unknown -M%s option"
msgstr ""
#: ppc-dis.c:965
#: ppc-dis.c:972
#, c-format
msgid ""
"\n"
@ -1935,101 +1935,126 @@ msgstr ""
msgid "attempt to set 'at' bits when using + or - modifier"
msgstr ""
#: ppc-opc.c:658
#: ppc-opc.c:677
msgid "invalid R operand"
msgstr ""
#: ppc-opc.c:713
#: ppc-opc.c:732
msgid "invalid mask field"
msgstr ""
#: ppc-opc.c:736
#: ppc-opc.c:755
msgid "invalid mfcr mask"
msgstr ""
#: ppc-opc.c:812
#: ppc-opc.c:873 ppc-opc.c:891
msgid "illegal L operand value"
msgstr ""
#: ppc-opc.c:851
#: ppc-opc.c:914
msgid "illegal WC operand value"
msgstr ""
#: ppc-opc.c:1011
msgid "incompatible L operand value"
msgstr ""
#: ppc-opc.c:891 ppc-opc.c:926
#: ppc-opc.c:1051 ppc-opc.c:1086
msgid "illegal bitmask"
msgstr ""
#: ppc-opc.c:1013
#: ppc-opc.c:1173
msgid "address register in load range"
msgstr ""
#: ppc-opc.c:1079
#: ppc-opc.c:1213
msgid "illegal PL operand value"
msgstr ""
#: ppc-opc.c:1274
msgid "index register in load range"
msgstr ""
#: ppc-opc.c:1108 ppc-opc.c:1194
#: ppc-opc.c:1303 ppc-opc.c:1389
msgid "source and target register operands must be different"
msgstr ""
#: ppc-opc.c:1139
#: ppc-opc.c:1334
msgid "invalid register operand when updating"
msgstr ""
#: ppc-opc.c:1257
#: ppc-opc.c:1452
msgid "illegal immediate value"
msgstr ""
#: ppc-opc.c:1362
#: ppc-opc.c:1557
msgid "invalid bat number"
msgstr ""
#: ppc-opc.c:1397
#: ppc-opc.c:1592
msgid "invalid sprg number"
msgstr ""
#: ppc-opc.c:1434
#: ppc-opc.c:1629
msgid "invalid tbr number"
msgstr ""
#: ppc-opc.c:1581
#: ppc-opc.c:1715 ppc-opc.c:1761
msgid "VSR overlaps ACC operand"
msgstr ""
#: ppc-opc.c:1868
msgid "invalid constant"
msgstr ""
#: ppc-opc.c:1683 ppc-opc.c:1706 ppc-opc.c:1729 ppc-opc.c:1752
#: ppc-opc.c:1970 ppc-opc.c:1993 ppc-opc.c:2016 ppc-opc.c:2039
msgid "UIMM = 00000 is illegal"
msgstr ""
#: ppc-opc.c:1775
#: ppc-opc.c:2062
msgid "UIMM values >7 are illegal"
msgstr ""
#: ppc-opc.c:1798
#: ppc-opc.c:2085
msgid "UIMM values >15 are illegal"
msgstr ""
#: ppc-opc.c:1821
#: ppc-opc.c:2108
msgid "GPR odd is illegal"
msgstr ""
#: ppc-opc.c:1844 ppc-opc.c:1867
#: ppc-opc.c:2131 ppc-opc.c:2154
msgid "invalid offset"
msgstr ""
#: ppc-opc.c:1890
#: ppc-opc.c:2177
msgid "invalid Ddd value"
msgstr ""
#: riscv-dis.c:68
#. The option without '=' should be defined above.
#: riscv-dis.c:84 riscv-dis.c:108
#, c-format
msgid "unrecognized disassembler option: %s"
msgstr ""
#: riscv-dis.c:346
#. Invalid options with '=', no option name before '=',
#. and no value after '='.
#: riscv-dis.c:92
#, c-format
msgid "unrecognized disassembler option with '=': %s"
msgstr ""
#: riscv-dis.c:102
#, c-format
msgid "unknown privilege spec set by %s=%s"
msgstr ""
#: riscv-dis.c:402
#, c-format
msgid "# internal error, undefined modifier (%c)"
msgstr ""
#: riscv-dis.c:545
#: riscv-dis.c:601
#, c-format
msgid ""
"\n"
@ -2037,19 +2062,27 @@ msgid ""
"with the -M switch (multiple options should be separated by commas):\n"
msgstr ""
#: riscv-dis.c:549
#: riscv-dis.c:605
#, c-format
msgid ""
"\n"
" numeric Print numeric register names, rather than ABI names.\n"
" numeric Print numeric register names, rather than ABI names.\n"
msgstr ""
#: riscv-dis.c:552
#: riscv-dis.c:608
#, c-format
msgid ""
"\n"
" no-aliases Disassemble only into canonical instructions, rather\n"
" than into pseudoinstructions.\n"
" no-aliases Disassemble only into canonical instructions, rather\n"
" than into pseudoinstructions.\n"
msgstr ""
#: riscv-dis.c:612
#, c-format
msgid ""
"\n"
" priv-spec=PRIV Print the CSR according to the chosen privilege spec\n"
" (1.9, 1.9.1, 1.10, 1.11).\n"
msgstr ""
#: rx-dis.c:139 rx-dis.c:163 rx-dis.c:171 rx-dis.c:179 rx-dis.c:187

80
opcodes/riscv-dis.c
View File

@ -31,6 +31,8 @@
#include "bfd_stdint.h"
#include <ctype.h>
static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
struct riscv_private_data
{
bfd_vma gp;
@ -52,8 +54,8 @@ set_default_riscv_dis_options (void)
no_aliases = 0;
}
static void
parse_riscv_dis_option (const char *option)
static bfd_boolean
parse_riscv_dis_option_without_args (const char *option)
{
if (strcmp (option, "no-aliases") == 0)
no_aliases = 1;
@ -62,6 +64,44 @@ parse_riscv_dis_option (const char *option)
riscv_gpr_names = riscv_gpr_names_numeric;
riscv_fpr_names = riscv_fpr_names_numeric;
}
else
return FALSE;
return TRUE;
}
static void
parse_riscv_dis_option (const char *option)
{
char *equal, *value;
if (parse_riscv_dis_option_without_args (option))
return;
equal = strchr (option, '=');
if (equal == NULL)
{
/* The option without '=' should be defined above. */
opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
return;
}
if (equal == option
|| *(equal + 1) == '\0')
{
/* Invalid options with '=', no option name before '=',
and no value after '='. */
opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
option);
return;
}
*equal = '\0';
value = equal + 1;
if (strcmp (option, "priv-spec") == 0)
{
if (!riscv_get_priv_spec_class (value, &default_priv_spec))
opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
option, value);
}
else
{
/* xgettext:c-format */
@ -322,16 +362,32 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'E':
{
const char* csr_name = NULL;
static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR. */
static bfd_boolean init_csr = FALSE;
unsigned int csr = EXTRACT_OPERAND (CSR, l);
switch (csr)
if (!init_csr)
{
#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
unsigned int i;
for (i = 0; i < 4096; i++)
riscv_csr_hash[i] = NULL;
/* Set to the newest privilege version. */
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
#define DECLARE_CSR(name, num, class, define_version, abort_version) \
if (default_priv_spec >= define_version \
&& default_priv_spec < abort_version) \
riscv_csr_hash[num] = #name;
#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
DECLARE_CSR (name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
if (csr_name)
print (info->stream, "%s", csr_name);
if (riscv_csr_hash[csr] != NULL)
print (info->stream, "%s", riscv_csr_hash[csr]);
else
print (info->stream, "0x%x", csr);
break;
@ -547,11 +603,15 @@ The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
numeric Print numeric register names, rather than ABI names.\n"));
numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n\
no-aliases Disassemble only into canonical instructions, rather\n\
than into pseudoinstructions.\n"));
no-aliases Disassemble only into canonical instructions, rather\n\
than into pseudoinstructions.\n"));
fprintf (stream, _("\n\
priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
(1.9, 1.9.1, 1.10, 1.11).\n"));
fprintf (stream, _("\n"));
}

144
opcodes/riscv-opc.c
View File

@ -884,3 +884,147 @@ const struct riscv_opcode riscv_insn_types[] =
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
/* All standard extensions defined in all supported ISA spec. */
const struct riscv_ext_version riscv_ext_version_table[] =
{
/* name, ISA spec, major version, minor_version. */
{"e", ISA_SPEC_CLASS_20191213, 1, 9},
{"e", ISA_SPEC_CLASS_20190608, 1, 9},
{"e", ISA_SPEC_CLASS_2P2, 1, 9},
{"i", ISA_SPEC_CLASS_20191213, 2, 1},
{"i", ISA_SPEC_CLASS_20190608, 2, 1},
{"i", ISA_SPEC_CLASS_2P2, 2, 0},
{"m", ISA_SPEC_CLASS_20191213, 2, 0},
{"m", ISA_SPEC_CLASS_20190608, 2, 0},
{"m", ISA_SPEC_CLASS_2P2, 2, 0},
{"a", ISA_SPEC_CLASS_20191213, 2, 1},
{"a", ISA_SPEC_CLASS_20190608, 2, 0},
{"a", ISA_SPEC_CLASS_2P2, 2, 0},
{"f", ISA_SPEC_CLASS_20191213, 2, 2},
{"f", ISA_SPEC_CLASS_20190608, 2, 2},
{"f", ISA_SPEC_CLASS_2P2, 2, 0},
{"d", ISA_SPEC_CLASS_20191213, 2, 2},
{"d", ISA_SPEC_CLASS_20190608, 2, 2},
{"d", ISA_SPEC_CLASS_2P2, 2, 0},
{"q", ISA_SPEC_CLASS_20191213, 2, 2},
{"q", ISA_SPEC_CLASS_20190608, 2, 2},
{"q", ISA_SPEC_CLASS_2P2, 2, 0},
{"c", ISA_SPEC_CLASS_20191213, 2, 0},
{"c", ISA_SPEC_CLASS_20190608, 2, 0},
{"c", ISA_SPEC_CLASS_2P2, 2, 0},
{"p", ISA_SPEC_CLASS_20191213, 0, 2},
{"p", ISA_SPEC_CLASS_20190608, 0, 2},
{"p", ISA_SPEC_CLASS_2P2, 0, 1},
{"v", ISA_SPEC_CLASS_20191213, 0, 7},
{"v", ISA_SPEC_CLASS_20190608, 0, 7},
{"v", ISA_SPEC_CLASS_2P2, 0, 7},
{"n", ISA_SPEC_CLASS_20190608, 1, 1},
{"n", ISA_SPEC_CLASS_2P2, 1, 1},
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
/* Terminate the list. */
{NULL, 0, 0, 0}
};
struct isa_spec_t
{
const char *name;
enum riscv_isa_spec_class class;
};
/* List for all supported ISA spec versions. */
static const struct isa_spec_t isa_specs[] =
{
{"2.2", ISA_SPEC_CLASS_2P2},
{"20190608", ISA_SPEC_CLASS_20190608},
{"20191213", ISA_SPEC_CLASS_20191213},
/* Terminate the list. */
{NULL, 0}
};
/* Get the corresponding ISA spec class by giving a ISA spec string. */
bfd_boolean
riscv_get_isa_spec_class (const char *s,
enum riscv_isa_spec_class *class)
{
const struct isa_spec_t *version;
if (s == NULL)
return FALSE;
for (version = &isa_specs[0]; version->name != NULL; ++version)
if (strcmp (version->name, s) == 0)
{
*class = version->class;
return TRUE;
}
/* Can not find the supported ISA spec. */
return FALSE;
}
struct priv_spec_t
{
const char *name;
enum riscv_priv_spec_class class;
};
/* List for all supported privilege versions. */
static const struct priv_spec_t priv_specs[] =
{
{"1.9", PRIV_SPEC_CLASS_1P9},
{"1.9.1", PRIV_SPEC_CLASS_1P9P1},
{"1.10", PRIV_SPEC_CLASS_1P10},
{"1.11", PRIV_SPEC_CLASS_1P11},
/* Terminate the list. */
{NULL, 0}
};
/* Get the corresponding CSR version class by giving a privilege
version string. */
bfd_boolean
riscv_get_priv_spec_class (const char *s,
enum riscv_priv_spec_class *class)
{
const struct priv_spec_t *version;
if (s == NULL)
return FALSE;
for (version = &priv_specs[0]; version->name != NULL; ++version)
if (strcmp (version->name, s) == 0)
{
*class = version->class;
return TRUE;
}
/* Can not find the supported privilege version. */
return FALSE;
}
/* Get the corresponding privilege version string by giving a CSR
version class. */
const char *
riscv_get_priv_spec_name (enum riscv_priv_spec_class class)
{
/* The first enum is PRIV_SPEC_CLASS_NONE. */
return priv_specs[class - 1].name;
}