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[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M Baseline 

gas/ChangeLog:
2019-05-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 24559
	* config/tc-arm.c (move_or_literal_pool): Set size_req to 0
	for MOVW replacement.
	* testsuite/gas/arm/load-pseudo.s: New test input.
	* testsuite/gas/arm/m0-load-pseudo.d: New test.
	* testsuite/gas/arm/m23-load-pseudo.d: New test.
	* testsuite/gas/arm/m33-load-pseudo.d: New test.
This commit is contained in:
Andre Vieira 2019-05-21 14:51:43 +01:00
parent e6f65e7573
commit 8fe9a076ad
6 changed files with 53 additions and 0 deletions
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10
gas/ChangeLog
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@ -1,3 +1,13 @@
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW
replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming

5
gas/config/tc-arm.c
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@ -8696,6 +8696,11 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
inst.instruction |= (imm & 0x0800) << 15;
inst.instruction |= (imm & 0x0700) << 4;
inst.instruction |= (imm & 0x00ff);
/* In case this replacement is being done on Armv8-M
Baseline we need to make sure to disable the
instruction size check, as otherwise GAS will reject
the use of this T32 instruction. */
inst.size_req = 0;
return TRUE;
}
}

3
gas/testsuite/gas/arm/load-pseudo.s Normal file
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@ -0,0 +1,3 @@
.syntax unified
ldr r0, =(0x30)
ldr r0, =(0x70000000)

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gas/testsuite/gas/arm/m0-load-pseudo.d Normal file
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@ -0,0 +1,12 @@
# name: Load pseudo-operation for Cortex-M0
# as: -mcpu=cortex-m0
# objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
# source: load-pseudo.s
.*: +file format .*arm.*
Disassembly of section .text:
[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000004 [^>]*>\)
[^>]*> 4801 ldr r0, \[pc, #4\] ; \(00000008 [^>]*>\)
#...

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gas/testsuite/gas/arm/m23-load-pseudo.d Normal file
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@ -0,0 +1,12 @@
# name: Load pseudo-operation for Cortex-M23
# as: -mcpu=cortex-m23
# objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
# source: load-pseudo.s
.*: +file format .*arm.*
Disassembly of section .text:
[^>]*> f240 0030 movw r0, #48 ; 0x30
[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000008 [^>]*>\)
#...

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gas/testsuite/gas/arm/m33-load-pseudo.d Normal file
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@ -0,0 +1,11 @@
# name: Load pseudo-operation for Cortex-M33
# as: -mcpu=cortex-m33
# objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
# source: load-pseudo.s
.*: +file format .*arm.*
Disassembly of section .text:
[^>]*> f04f 0030 mov.w r0, #48 ; 0x30
[^>]*> f04f 40e0 mov.w r0, #1879048192 ; 0x70000000