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2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>

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* opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	Remove redundant instruction types.
	(struct argument): X_op - new field.
	(struct cst4_entry): Remove.
	(no_op_insn): Declare.
This commit is contained in:
Tomer Levi 2004-11-29 16:36:50 +00:00
parent 89a649f7ae
commit 9019af69c4
2 changed files with 47 additions and 49 deletions
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8
include/ChangeLog
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@ -1,3 +1,11 @@
2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
* opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
Remove redundant instruction types.
(struct argument): X_op - new field.
(struct cst4_entry): Remove.
(no_op_insn): Declare.
2004-11-04 Paul Brook <paul@codesourcery.com>
* bfdlink.h (bfd_link_info): Add default_imported_symver.

88
include/opcode/crx.h
View File

@ -130,7 +130,7 @@ typedef enum
/* N-bit absolute address. */
abs16, abs32,
/* Register relative. */
rbase, rbase_cst4,
rbase, rbase_dispu4,
rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
/* Register index. */
rindex_disps6, rindex_disps22,
@ -162,19 +162,13 @@ operand_type;
#define LD_STOR_INS_INC 8
#define STOR_IMM_INS 9
#define CSTBIT_INS 10
#define SYS_INS 11
#define JMP_INS 12
#define MUL_INS 13
#define DIV_INS 14
#define COP_BRANCH_INS 15
#define COP_REG_INS 16
#define COPS_REG_INS 17
#define DCR_BRANCH_INS 18
#define MMC_INS 19
#define MMU_INS 20
#define COP_BRANCH_INS 11
#define COP_REG_INS 12
#define COPS_REG_INS 13
#define DCR_BRANCH_INS 14
/* Maximum value supported for instruction types. */
#define CRX_INS_MAX (1 << 5)
#define CRX_INS_MAX (1 << 4)
/* Mask to record an instruction type. */
#define CRX_INS_MASK (CRX_INS_MAX - 1)
/* Return instruction type, given instruction's attributes. */
@ -184,42 +178,40 @@ operand_type;
#define REG_LIST CRX_INS_MAX
/* The operands in binary and assembly are placed in reverse order.
load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
#define REVERSE_MATCH (1 << 6)
#define REVERSE_MATCH (1 << 5)
/* Kind of displacement map used DISPU[BWD]4. */
#define DISPUB4 (1 << 7)
#define DISPUW4 (1 << 8)
#define DISPUD4 (1 << 9)
#define DISPUB4 (1 << 6)
#define DISPUW4 (1 << 7)
#define DISPUD4 (1 << 8)
#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4)
/* Printing formats, where the instruction prefix isn't consecutive. */
#define FMT_1 (1 << 10) /* 0xF0F00000 */
#define FMT_2 (1 << 11) /* 0xFFF0FF00 */
#define FMT_3 (1 << 12) /* 0xFFF00F00 */
#define FMT_4 (1 << 13) /* 0xFFF0F000 */
#define FMT_5 (1 << 14) /* 0xFFF0FFF0 */
#define FMT_1 (1 << 9) /* 0xF0F00000 */
#define FMT_2 (1 << 10) /* 0xFFF0FF00 */
#define FMT_3 (1 << 11) /* 0xFFF00F00 */
#define FMT_4 (1 << 12) /* 0xFFF0F000 */
#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */
#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
/* Indicates whether this instruction can be relaxed. */
#define RELAXABLE (1 << 15)
#define RELAXABLE (1 << 14)
/* Indicates that instruction uses user registers (and not
general-purpose registers) as operands. */
#define USER_REG (1 << 16)
#define USER_REG (1 << 15)
/* Indicates that instruction can perfom a cst4 mapping. */
#define CST4MAP (1 << 17)
#define CST4MAP (1 << 16)
/* Instruction shouldn't allow 'sp' usage. */
#define NO_SP (1 << 18)
#define NO_SP (1 << 17)
/* Instruction shouldn't allow to push a register which is used as a rptr. */
#define NO_RPTR (1 << 19)
#define NO_RPTR (1 << 18)
/* Maximum operands per instruction. */
#define MAX_OPERANDS 5
/* Maximum words per instruction. */
#define MAX_WORDS 3
/* Maximum register name length. */
#define MAX_REGNAME_LEN 10
/* Maximum instruction length. */
@ -229,19 +221,23 @@ operand_type;
/* Values defined for the flags field of a struct operand_entry. */
/* Operand must be an unsigned number. */
#define OPERAND_UNSIGNED (1 << 0)
#define OP_UNSIGNED (1 << 0)
/* Operand must be a signed number. */
#define OPERAND_SIGNED (1 << 1)
/* A cst4 operand. */
#define OPERAND_CST4 (1 << 2)
#define OP_SIGNED (1 << 1)
/* A special arithmetic 4-bit constant operand. */
#define OP_CST4 (1 << 2)
/* A special load/stor 4-bit unsigned displacement operand. */
#define OP_DISPU4 (1 << 3)
/* Operand must be an even number. */
#define OPERAND_EVEN (1 << 3)
#define OP_EVEN (1 << 4)
/* Operand is shifted right. */
#define OPERAND_SHIFT (1 << 4)
#define OP_SHIFT (1 << 5)
/* Operand is shifted right and decremented. */
#define OPERAND_SHIFT_DEC (1 << 5)
#define OP_SHIFT_DEC (1 << 6)
/* Operand has reserved escape sequences. */
#define OPERAND_ESC (1 << 6)
#define OP_ESC (1 << 7)
/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */
#define OP_UPPER_64KB (1 << 8)
/* Single operand description. */
@ -284,15 +280,15 @@ typedef struct
/* Coprocessor register. */
copreg cr;
/* Constant/immediate/absolute value. */
unsigned long int constant;
long constant;
/* Scaled index mode. */
unsigned int scale;
/* Argument type. */
argtype type;
/* Size of the argument (in bits) required to represent. */
int size;
/* Indicates whether a constant is positive or negative. */
int signflag;
/* The type of the expression. */
unsigned char X_op;
}
argument;
@ -363,15 +359,6 @@ reg_entry;
/* Structure to hold a cst4 operand mapping. */
typedef struct
{
/* The binary value which is written to the object file. */
int binary;
/* The value which is mapped. */
int value;
}
cst4_entry;
/* CRX opcode table. */
extern const inst crx_instruction[];
extern const int crx_num_opcodes;
@ -396,9 +383,12 @@ extern const int crx_num_traps;
#define NUMTRAPS crx_num_traps
/* cst4 operand mapping. */
extern const cst4_entry cst4_map[];
extern const long cst4_map[];
extern const int cst4_maps;
/* Table of instructions with no operands. */
extern const char* no_op_insn[];
/* Current instruction we're assembling. */
extern const inst *instruction;