[MIPS] Add Loongson 2K1000 proccessor support.
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs264e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS264E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs264e to bfd_mach_mips_gs464e extension. binutils/ * NEWS: Mention Loongson 2K1000 proccessor support. * readelf.c (get_machine_flags): Handle gs264e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. (mips_cpu_info_table): Add gs264e descriptors. * doc/as.texi (march table): Add gs264e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. * opcode/mips.h (CPU_XXX): New CPU_GS264E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs264e and gs464e. opcodes/ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
This commit is contained in:
Chenghua Xu
parent
bd782c07b9
commit
9108bc33b1
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@ -1,3 +1,16 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* archures.c (bfd_architecture): New machine
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bfd_mach_mips_gs264e.
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* bfd-in2.h (bfd_architecture): Likewise.
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* cpu-mips.c (enum I_xxx): Likewise.
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(arch_info_struct): Likewise.
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* elfxx-mips.c (_bfd_elf_mips_mach): Handle
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E_MIPS_MACH_GS264E.
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(mips_set_isa_flags): Likewise.
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(mips_mach_extensions): Map bfd_mach_mips_gs264e to
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bfd_mach_mips_gs464e extension.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* archures.c (bfd_architecture): New machine
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@ -177,6 +177,7 @@ DESCRIPTION
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.#define bfd_mach_mips_loongson_2f 3002
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.#define bfd_mach_mips_gs464 3003
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.#define bfd_mach_mips_gs464e 3004
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.#define bfd_mach_mips_gs264e 3005
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.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01. *}
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.#define bfd_mach_mips_octeon 6501
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.#define bfd_mach_mips_octeonp 6601
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@ -2071,6 +2071,7 @@ enum bfd_architecture
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#define bfd_mach_mips_loongson_2f 3002
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#define bfd_mach_mips_gs464 3003
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#define bfd_mach_mips_gs464e 3004
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#define bfd_mach_mips_gs264e 3005
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#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01. */
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#define bfd_mach_mips_octeon 6501
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#define bfd_mach_mips_octeonp 6601
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@ -100,6 +100,7 @@ enum
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I_loongson_2f,
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I_gs464,
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I_gs464e,
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I_gs264e,
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I_mipsocteon,
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I_mipsocteonp,
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I_mipsocteon2,
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@ -153,6 +154,7 @@ static const bfd_arch_info_type arch_info_struct[] =
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N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
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N (64, 64, bfd_mach_mips_gs464, "mips:gs464", FALSE, NN(I_gs464)),
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N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", FALSE, NN(I_gs464e)),
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N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e", FALSE, NN(I_gs264e)),
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N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
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N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
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N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
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@ -6793,6 +6793,9 @@ _bfd_elf_mips_mach (flagword flags)
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case E_MIPS_MACH_GS464E:
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return bfd_mach_mips_gs464e;
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case E_MIPS_MACH_GS264E:
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return bfd_mach_mips_gs264e;
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case E_MIPS_MACH_OCTEON3:
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return bfd_mach_mips_octeon3;
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@ -11995,6 +11998,10 @@ mips_set_isa_flags (bfd *abfd)
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val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
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break;
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case bfd_mach_mips_gs264e:
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val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
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break;
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case bfd_mach_mips_octeon:
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case bfd_mach_mips_octeonp:
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val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
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@ -14000,6 +14007,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
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{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
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{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
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{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
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{ bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
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{ bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
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{ bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
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@ -1,3 +1,8 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* NEWS: Mention Loongson 2K1000 proccessor support.
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* readelf.c (get_machine_flags): Handle gs264e.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
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@ -1,5 +1,10 @@
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-*- text -*-
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* The MIPS port now supports the Loongson 2K1000 processor which implements
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the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE, Loongson-ext ASE,
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Loongson-ext2 ASE and MSA ASE instructions. Add -march=gs264e option for
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Loongson 2K1000 processor.
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* The MIPS port now supports the Loongson 3A2000/3A3000 processor which
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implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
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Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
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@ -3406,6 +3406,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
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case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
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case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
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case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
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case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break;
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case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
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case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
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case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
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@ -1,3 +1,7 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
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@ -237,6 +237,7 @@ enum
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E_MIPS_MACH_LS2F = 0x00A10000,
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E_MIPS_MACH_GS464 = 0x00A20000,
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E_MIPS_MACH_GS464E = 0x00A30000,
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E_MIPS_MACH_GS264E = 0x00A40000,
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};
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// MIPS architecture
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@ -1,3 +1,9 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
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(mips_cpu_info_table): Add gs264e descriptors.
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* doc/as.texi (march table): Add gs264e.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
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@ -423,7 +423,8 @@ static int mips_32bitmode = 0;
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|| (ISA) == ISA_MIPS64R6 \
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|| (CPU) == CPU_R5900) \
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&& ((CPU) != CPU_GS464 \
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|| (CPU) != CPU_GS464E))
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|| (CPU) != CPU_GS464E \
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|| (CPU) != CPU_GS264E))
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/* Return true if ISA supports move to/from high part of a 64-bit
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floating-point register. */
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@ -19817,6 +19818,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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ISA_MIPS64R2, CPU_GS464 },
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{ "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
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| ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E },
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{ "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
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| ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E },
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/* Cavium Networks Octeon CPU core */
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{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
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@ -439,6 +439,7 @@ loongson2e,
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loongson2f,
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gs464,
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gs464e,
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gs264e,
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octeon,
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octeon+,
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octeon2,
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@ -3984,6 +3984,7 @@ class Target_mips : public Sized_target<size, big_endian>
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mach_mips_loongson_2f = 3002,
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mach_mips_gs464 = 3003,
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mach_mips_gs464e = 3004,
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mach_mips_gs264e = 3005,
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mach_mips_sb1 = 12310201, // octal 'SB', 01
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mach_mips_octeon = 6501,
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mach_mips_octeonp = 6601,
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@ -4149,6 +4150,7 @@ class Target_mips : public Sized_target<size, big_endian>
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this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
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this->add_extension(mach_mips_octeonp, mach_mips_octeon);
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this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
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this->add_extension(mach_mips_gs264e, mach_mips_gs464e);
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this->add_extension(mach_mips_gs464e, mach_mips_gs464);
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this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
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@ -8866,6 +8868,9 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags)
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case elfcpp::E_MIPS_MACH_GS464E:
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return mach_mips_gs464e;
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case elfcpp::E_MIPS_MACH_GS264E:
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return mach_mips_gs264e;
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case elfcpp::E_MIPS_MACH_OCTEON3:
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return mach_mips_octeon3;
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@ -12533,6 +12538,8 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags)
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return "mips:gs464";
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case elfcpp::E_MIPS_MACH_GS464E:
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return "mips:gs464e";
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case elfcpp::E_MIPS_MACH_GS264E:
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return "mips:gs264e";
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case elfcpp::E_MIPS_MACH_OCTEON:
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return "mips:octeon";
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case elfcpp::E_MIPS_MACH_OCTEON2:
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@ -1,5 +1,9 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
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* opcode/mips.h (CPU_XXX): New CPU_GS264E.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
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* opcode/mips.h (CPU_XXX): New CPU_GS464E.
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@ -301,6 +301,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
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#define E_MIPS_MACH_LS2F 0x00A10000
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#define E_MIPS_MACH_GS464 0x00A20000
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#define E_MIPS_MACH_GS464E 0x00A30000
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#define E_MIPS_MACH_GS264E 0x00A40000
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/* Processor specific section indices. These sections do not actually
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exist. Symbols with a st_shndx field corresponding to one of these
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@ -1374,6 +1374,7 @@ static const unsigned int mips_isa_table[] = {
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#define CPU_LOONGSON_2F 3002
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#define CPU_GS464 3003
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#define CPU_GS464E 3004
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#define CPU_GS264E 3005
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#define CPU_OCTEON 6501
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#define CPU_OCTEONP 6601
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#define CPU_OCTEON2 6502
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@ -1,3 +1,8 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
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gs264e and gs464e.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
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@ -320,3 +320,7 @@ good_combination { "-march=gs464 -32" "-march=gs464e -32" } \
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{ gs464e o32 } \
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MIPS64r2 "None" \
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{ "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
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good_combination { "-march=gs264e -32" "-march=gs464e -32" } \
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{ gs264e o32 } \
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MIPS64r2 "None" \
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{ "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
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@ -1,3 +1,7 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
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@ -645,6 +645,11 @@ const struct mips_arch_choice mips_arch_choices[] =
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| ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
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mips_hwr_names_numeric },
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{ "g264e", 1, bfd_mach_mips_gs464e, CPU_GS264E,
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ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
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| ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL,
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0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
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{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
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ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
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mips_cp1_names_mips3264, mips_hwr_names_numeric },
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