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Fix the disassembly of the AArch64 SIMD EXT instruction.

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PR 18800
	* aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
	instruction.
This commit is contained in:
Nick Clifton 2015-08-11 18:00:36 +01:00
parent dbac553d28
commit 922c5db5e7
2 changed files with 7 additions and 1 deletions
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6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2015-08-11 Nick Clifton <nickc@redhat.com>
PR 18800
* aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
instruction.
2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
* mips-opc.c (mips_builtin_opcodes): Add "sigrie".

2
opcodes/aarch64-tbl.h
View File

@ -1367,7 +1367,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
{"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
/* AdvSIMD EXT. */
{"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
{"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
/* AdvSIMD modified immediate. */
{"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
{"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},