<gas changes>
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS. (build_modrm_byte): Add support to handle FMA4 instructions. (md_show_usage): Add fma4. <gas/testsuite changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * gas/i386/i386.exp: Add FMA4 tests. * gas/i386/x86-64-fma4.d: Ditto. * gas/i386/fma4.d: Ditto. * gas/i386/x86-64-fma4.s: Ditto. * gas/i386/fma4.s: Ditto. <opcodes changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (CpuFMA4): Add CpuFMA4. (i386_cpu_flags): New. * i386-gen.c: Add CPU_FMA4_FLAGS. * i386-opc.tbl: Add FMA4 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_VEX_FMA): New. Handle FMA4. (OP_XMM_VexW): Ditto. (OP_EX_VexW): Ditto. (VEXI4_Fixup): Ditto. (VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros. (PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New. (PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New. (PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New. (PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New. (PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New. (PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New. (PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New. (VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New. (VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New. (VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New. (get_vex_imm8): New. handle FMA4. (OP_EX_VexReg): Ditto.
This commit is contained in:
Dwarakanath Rajagopal
parent
d80a43f961
commit
922d8de8c1
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@ -1,3 +1,9 @@
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2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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* config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS.
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(build_modrm_byte): Add support to handle FMA4 instructions.
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(md_show_usage): Add fma4.
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2009-07-04 Alan Modra <amodra@bigpond.net.au>
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* config/tc-cr16.h (TC_LINKRELAX_FIXUP): Set only for code sections.
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@ -623,6 +623,8 @@ static const arch_entry cpu_arch[] =
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CPU_PCLMUL_FLAGS },
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{ ".fma", PROCESSOR_UNKNOWN,
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CPU_FMA_FLAGS },
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{ ".fma4", PROCESSOR_UNKNOWN,
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CPU_FMA4_FLAGS },
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{ ".movbe", PROCESSOR_UNKNOWN,
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CPU_MOVBE_FLAGS },
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{ ".ept", PROCESSOR_UNKNOWN,
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@ -4757,31 +4759,25 @@ build_modrm_byte (void)
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{
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unsigned int nds, reg;
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if (i.tm.opcode_modifier.veximmext
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&& i.tm.opcode_modifier.immext)
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{
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dest = i.operands - 2;
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gas_assert (dest == 3);
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}
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else
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dest = i.operands - 1;
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nds = dest - 1;
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source = 1;
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reg = 0;
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/* This instruction must have 4 operands: 4 register operands
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or 3 register operands plus 1 memory operand. It must have
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VexNDS and VexImmExt. */
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gas_assert (i.operands == 4
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&& (i.reg_operands == 4
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/* This instruction must have 4 register operands
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or 3 register operands plus 1 memory operand.
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It must have VexNDS and VexImmExt. */
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gas_assert ((i.reg_operands == 4
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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&& i.tm.opcode_modifier.vexnds
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&& i.tm.opcode_modifier.veximmext
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&& (operand_type_equal (&i.tm.operand_types[dest],
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®xmm)
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|| operand_type_equal (&i.tm.operand_types[dest],
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®ymm))
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&& (operand_type_equal (&i.tm.operand_types[nds],
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®xmm)
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|| operand_type_equal (&i.tm.operand_types[nds],
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®ymm))
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&& (operand_type_equal (&i.tm.operand_types[reg],
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®xmm)
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|| operand_type_equal (&i.tm.operand_types[reg],
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®ymm)));
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&& (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[dest], ®ymm)));
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/* Generate an 8bit immediate operand to encode the register
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operand. */
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@ -4789,11 +4785,36 @@ build_modrm_byte (void)
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i.op[i.operands].imms = exp;
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i.types[i.operands] = imm8;
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i.operands++;
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/* If VexW1 is set, the first operand is the source and
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the second operand is encoded in the immediate operand. */
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if (i.tm.opcode_modifier.vexw1)
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{
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source = 0;
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reg = 1;
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}
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else
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{
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source = 1;
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reg = 0;
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}
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/* FMA4 swaps REG and NDS. */
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if (i.tm.cpu_flags.bitfield.cpufma4)
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{
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unsigned int tmp;
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tmp = reg;
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reg = nds;
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nds = tmp;
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}
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gas_assert ((operand_type_equal (&i.tm.operand_types[reg], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[reg],
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®ymm))
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&& (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[nds],
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®ymm)));
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exp->X_op = O_constant;
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exp->X_add_number
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= ((i.op[0].regs->reg_num
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+ ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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= ((i.op[reg].regs->reg_num
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+ ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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i.vex.register_specifier = i.op[nds].regs;
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}
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else
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@ -4931,7 +4952,6 @@ build_modrm_byte (void)
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for (op = 0; op < i.operands; op++)
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if (operand_type_check (i.types[op], anymem))
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break;
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gas_assert (op < i.operands);
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default_seg = &ds;
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@ -7855,7 +7875,7 @@ md_show_usage (stream)
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mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
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avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
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clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
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svme, abm, padlock\n"));
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svme, abm, padlock, fma4\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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@ -1,3 +1,11 @@
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2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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* gas/i386/i386.exp: Add FMA4 tests.
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* gas/i386/x86-64-fma4.d: Ditto.
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* gas/i386/fma4.d: Ditto.
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* gas/i386/x86-64-fma4.s: Ditto.
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* gas/i386/fma4.s: Ditto.
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2009-07-01 Nick Clifton <nickc@redhat.com>
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PR 10168
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@ -0,0 +1,92 @@
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#objdump: -dw
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#name: i386 FMA4
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.*: file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
|
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[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
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[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
|
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[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
|
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[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
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|
|
@ -0,0 +1,91 @@
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# Check FMA4 instructions
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.allow_index_reg
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.text
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_start:
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vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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vfmaddpd (%ecx),%ymm6,%ymm2,%ymm7
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vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
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vfmaddps (%ecx),%ymm6,%ymm2,%ymm7
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vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubpd (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubps (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmsubaddpd (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmsubaddps (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmsubpd (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmsubps (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddpd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddpd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddps (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddps %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubpd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubpd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubps (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubps %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmsubaddpd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmsubaddpd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmsubaddps (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmsubaddps %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmsubpd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmsubpd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmsubps (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmsubps %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddsd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddsd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmsubsd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmsubsd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddss (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddss %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmsubss (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfmsubss %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmaddpd (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmaddps (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmsubpd (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmsubps (%ecx),%ymm6,%ymm2,%ymm7
|
||||
vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddpd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddpd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddps (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddps %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubpd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubpd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubps (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubps %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddsd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddsd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubsd (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubsd %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddss (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddss %xmm4,(%ecx),%xmm2,%xmm7
|
||||
vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubss (%ecx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubss %xmm4,(%ecx),%xmm2,%xmm7
|
||||
|
||||
|
|
@ -148,6 +148,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "sse2avx-opts-intel"
|
||||
run_dump_test "fma"
|
||||
run_dump_test "fma-intel"
|
||||
run_dump_test "fma4"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
|
|
@ -307,6 +308,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-avx-swap-intel"
|
||||
run_dump_test "x86-64-fma"
|
||||
run_dump_test "x86-64-fma-intel"
|
||||
run_dump_test "x86-64-fma4"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 FMA4
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
# Check 64bit FMA4 instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmaddpd (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmaddps (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubpd (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfmaddsubps (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddpd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddpd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddps (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddps %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubpd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubpd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubps (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddsubps %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddsd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddsd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfmaddss (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfmaddss %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmaddpd (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmaddps (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmsubpd (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
vfnmsubps (%rcx),%ymm6,%ymm2,%ymm7
|
||||
vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddpd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddpd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddps (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddps %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubpd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubpd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubps (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubps %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddsd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddsd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubsd (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmsubsd %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmaddss (%rcx),%xmm6,%xmm2,%xmm7
|
||||
vfnmaddss %xmm4,(%rcx),%xmm2,%xmm7
|
||||
vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
|
||||
vfnmsubss (%rcx),%xmm6,%xmm2,%xmm7
|
||||
|
||||
|
|
@ -1,3 +1,29 @@
|
|||
2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
|
||||
|
||||
* i386-opc.h (CpuFMA4): Add CpuFMA4.
|
||||
(i386_cpu_flags): New.
|
||||
* i386-gen.c: Add CPU_FMA4_FLAGS.
|
||||
* i386-opc.tbl: Add FMA4 instructions.
|
||||
* i386-tbl.h: Regenerate.
|
||||
* i386-init.h: Regenerate.
|
||||
* i386-dis.c (OP_VEX_FMA): New. Handle FMA4.
|
||||
(OP_XMM_VexW): Ditto.
|
||||
(OP_EX_VexW): Ditto.
|
||||
(VEXI4_Fixup): Ditto.
|
||||
(VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros.
|
||||
(PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New.
|
||||
(PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New.
|
||||
(PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New.
|
||||
(PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New.
|
||||
(PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New.
|
||||
(PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New.
|
||||
(PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New.
|
||||
(VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New.
|
||||
(VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New.
|
||||
(VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New.
|
||||
(get_vex_imm8): New. handle FMA4.
|
||||
(OP_EX_VexReg): Ditto.
|
||||
|
||||
2009-06-30 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
PR 10288
|
||||
|
|
|
|||
|
|
@ -93,10 +93,14 @@ static void OP_MS (int, int);
|
|||
static void OP_XS (int, int);
|
||||
static void OP_M (int, int);
|
||||
static void OP_VEX (int, int);
|
||||
static void OP_VEX_FMA (int, int);
|
||||
static void OP_EX_Vex (int, int);
|
||||
static void OP_EX_VexW (int, int);
|
||||
static void OP_XMM_Vex (int, int);
|
||||
static void OP_XMM_VexW (int, int);
|
||||
static void OP_REG_VexI4 (int, int);
|
||||
static void PCLMUL_Fixup (int, int);
|
||||
static void VEXI4_Fixup (int, int);
|
||||
static void VZERO_Fixup (int, int);
|
||||
static void VCMP_Fixup (int, int);
|
||||
static void OP_0f07 (int, int);
|
||||
|
|
@ -358,11 +362,18 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define Vex { OP_VEX, vex_mode }
|
||||
#define Vex128 { OP_VEX, vex128_mode }
|
||||
#define Vex256 { OP_VEX, vex256_mode }
|
||||
#define VexI4 { VEXI4_Fixup, 0}
|
||||
#define VexFMA { OP_VEX_FMA, vex_mode }
|
||||
#define Vex128FMA { OP_VEX_FMA, vex128_mode }
|
||||
#define EXdVex { OP_EX_Vex, d_mode }
|
||||
#define EXdVexS { OP_EX_Vex, d_swap_mode }
|
||||
#define EXqVex { OP_EX_Vex, q_mode }
|
||||
#define EXqVexS { OP_EX_Vex, q_swap_mode }
|
||||
#define EXVexW { OP_EX_VexW, x_mode }
|
||||
#define EXdVexW { OP_EX_VexW, d_mode }
|
||||
#define EXqVexW { OP_EX_VexW, q_mode }
|
||||
#define XMVex { OP_XMM_Vex, 0 }
|
||||
#define XMVexW { OP_XMM_VexW, 0 }
|
||||
#define XMVexI4 { OP_REG_VexI4, x_mode }
|
||||
#define PCLMUL { PCLMUL_Fixup, 0 }
|
||||
#define VZERO { VZERO_Fixup, 0 }
|
||||
|
|
@ -980,11 +991,31 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define PREFIX_VEX_3A4A (PREFIX_VEX_3A44 + 1)
|
||||
#define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
|
||||
#define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
|
||||
#define PREFIX_VEX_3A60 (PREFIX_VEX_3A4C + 1)
|
||||
#define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
|
||||
#define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
|
||||
#define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
|
||||
#define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
|
||||
#define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
|
||||
#define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
|
||||
#define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
|
||||
#define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
|
||||
#define PREFIX_VEX_3ADF (PREFIX_VEX_3A63 + 1)
|
||||
#define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
|
||||
#define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
|
||||
#define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
|
||||
#define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
|
||||
#define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
|
||||
#define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
|
||||
#define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
|
||||
#define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
|
||||
#define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
|
||||
#define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
|
||||
#define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
|
||||
#define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
|
||||
#define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
|
||||
#define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
|
||||
#define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
|
||||
#define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
|
||||
#define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1)
|
||||
|
||||
#define X86_64_06 0
|
||||
#define X86_64_07 (X86_64_06 + 1)
|
||||
|
|
@ -1216,7 +1247,15 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
|
||||
#define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
|
||||
#define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
|
||||
#define VEX_LEN_3ADF_P_2 (VEX_LEN_3A63_P_2 + 1)
|
||||
#define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1)
|
||||
#define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1)
|
||||
#define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1)
|
||||
#define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1)
|
||||
#define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1)
|
||||
#define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1)
|
||||
#define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1)
|
||||
#define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1)
|
||||
#define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1)
|
||||
|
||||
typedef void (*op_rtn) (int bytemode, int sizeflag);
|
||||
|
||||
|
|
@ -5028,6 +5067,38 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A5C */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A5D */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A5E */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A5F */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A60 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -5060,6 +5131,134 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A68 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A69 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A6A */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A6B */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A6C */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A6D */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A6E */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A6F */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A78 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A79 */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A7A */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A7B */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A7C */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A7D */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A7E */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A7F */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3ADF */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -6807,10 +7006,10 @@ static const struct dis386 vex_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A5C) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A5D) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A5E) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A5F) },
|
||||
/* 60 */
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A60) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A61) },
|
||||
|
|
@ -6821,14 +7020,14 @@ static const struct dis386 vex_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 68 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A68) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A69) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A6A) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A6B) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A6C) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A6D) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A6E) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A6F) },
|
||||
/* 70 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -6839,14 +7038,14 @@ static const struct dis386 vex_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 78 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A78) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A79) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A7A) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A7B) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A7C) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A7D) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A7E) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A7F) },
|
||||
/* 80 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -8153,6 +8352,54 @@ static const struct dis386 vex_len_table[][2] = {
|
|||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A6A_P_2 */
|
||||
{
|
||||
{ "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A6B_P_2 */
|
||||
{
|
||||
{ "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A6E_P_2 */
|
||||
{
|
||||
{ "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A6F_P_2 */
|
||||
{
|
||||
{ "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A7A_P_2 */
|
||||
{
|
||||
{ "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A7B_P_2 */
|
||||
{
|
||||
{ "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A7E_P_2 */
|
||||
{
|
||||
{ "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3A7F_P_2 */
|
||||
{
|
||||
{ "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
/* VEX_LEN_3ADF_P_2 */
|
||||
{
|
||||
{ "vaeskeygenassist", { XM, EXx, Ib } },
|
||||
|
|
@ -12242,6 +12489,182 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
|||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
|
||||
/* Get the VEX immediate byte without moving codep. */
|
||||
|
||||
static unsigned char
|
||||
get_vex_imm8 (int sizeflag)
|
||||
{
|
||||
int bytes_before_imm = 0;
|
||||
|
||||
/* Skip mod/rm byte. */
|
||||
MODRM_CHECK;
|
||||
codep++;
|
||||
|
||||
if (modrm.mod != 3)
|
||||
{
|
||||
/* There are SIB/displacement bytes. */
|
||||
if ((sizeflag & AFLAG) || address_mode == mode_64bit)
|
||||
{
|
||||
/* 32/64 bit address mode */
|
||||
int base = modrm.rm;
|
||||
|
||||
/* Check SIB byte. */
|
||||
if (base == 4)
|
||||
{
|
||||
FETCH_DATA (the_info, codep + 1);
|
||||
base = *codep & 7;
|
||||
bytes_before_imm++;
|
||||
}
|
||||
|
||||
switch (modrm.mod)
|
||||
{
|
||||
case 0:
|
||||
/* When modrm.rm == 5 or modrm.rm == 4 and base in
|
||||
SIB == 5, there is a 4 byte displacement. */
|
||||
if (base != 5)
|
||||
/* No displacement. */
|
||||
break;
|
||||
case 2:
|
||||
/* 4 byte displacement. */
|
||||
bytes_before_imm += 4;
|
||||
break;
|
||||
case 1:
|
||||
/* 1 byte displacement. */
|
||||
bytes_before_imm++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* 16 bit address mode */
|
||||
switch (modrm.mod)
|
||||
{
|
||||
case 0:
|
||||
/* When modrm.rm == 6, there is a 2 byte displacement. */
|
||||
if (modrm.rm != 6)
|
||||
/* No displacement. */
|
||||
break;
|
||||
case 2:
|
||||
/* 2 byte displacement. */
|
||||
bytes_before_imm += 2;
|
||||
break;
|
||||
case 1:
|
||||
/* 1 byte displacement. */
|
||||
bytes_before_imm++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
FETCH_DATA (the_info, codep + bytes_before_imm + 1);
|
||||
return codep [bytes_before_imm];
|
||||
}
|
||||
|
||||
static void
|
||||
OP_EX_VexReg (int bytemode, int sizeflag, int reg)
|
||||
{
|
||||
if (reg == -1 && modrm.mod != 3)
|
||||
{
|
||||
OP_E_memory (bytemode, sizeflag);
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (reg == -1)
|
||||
{
|
||||
reg = modrm.rm;
|
||||
USED_REX (REX_B);
|
||||
if (rex & REX_B)
|
||||
reg += 8;
|
||||
}
|
||||
else if (reg > 7 && address_mode != mode_64bit)
|
||||
BadOp ();
|
||||
}
|
||||
|
||||
switch (vex.length)
|
||||
{
|
||||
case 128:
|
||||
sprintf (scratchbuf, "%%xmm%d", reg);
|
||||
break;
|
||||
case 256:
|
||||
sprintf (scratchbuf, "%%ymm%d", reg);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_EX_VexW (int bytemode, int sizeflag)
|
||||
{
|
||||
int reg = -1;
|
||||
|
||||
if (!vex_w_done)
|
||||
{
|
||||
vex_w_done = 1;
|
||||
if (vex.w)
|
||||
reg = vex.register_specifier;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (!vex.w)
|
||||
reg = vex.register_specifier;
|
||||
}
|
||||
|
||||
OP_EX_VexReg (bytemode, sizeflag, reg);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_VEX_FMA (int bytemode, int sizeflag)
|
||||
{
|
||||
int reg = get_vex_imm8 (sizeflag) >> 4;
|
||||
|
||||
if (reg > 7 && address_mode != mode_64bit)
|
||||
BadOp ();
|
||||
|
||||
switch (vex.length)
|
||||
{
|
||||
case 128:
|
||||
switch (bytemode)
|
||||
{
|
||||
case vex_mode:
|
||||
case vex128_mode:
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
return;
|
||||
}
|
||||
|
||||
sprintf (scratchbuf, "%%xmm%d", reg);
|
||||
break;
|
||||
case 256:
|
||||
switch (bytemode)
|
||||
{
|
||||
case vex_mode:
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
return;
|
||||
}
|
||||
|
||||
sprintf (scratchbuf, "%%ymm%d", reg);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
|
||||
static void
|
||||
VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
|
||||
int sizeflag ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Skip the immediate byte and check for invalid bits. */
|
||||
FETCH_DATA (the_info, codep + 1);
|
||||
if (*codep++ & 0xf)
|
||||
BadOp ();
|
||||
}
|
||||
|
||||
static void
|
||||
OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
||||
{
|
||||
|
|
@ -12273,6 +12696,15 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
|||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_XMM_VexW (int bytemode, int sizeflag)
|
||||
{
|
||||
/* Turn off the REX.W bit since it is used for swapping operands
|
||||
now. */
|
||||
rex &= ~REX_W;
|
||||
OP_XMM (bytemode, sizeflag);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_EX_Vex (int bytemode, int sizeflag)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -116,6 +116,8 @@ static initializer cpu_flag_init[] =
|
|||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
|
||||
{ "CPU_FMA_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
|
||||
{ "CPU_FMA4_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" },
|
||||
{ "CPU_MOVBE_FLAGS",
|
||||
"CpuMovbe" },
|
||||
{ "CPU_RDTSCP_FLAGS",
|
||||
|
|
@ -273,6 +275,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuAES),
|
||||
BITFIELD (CpuPCLMUL),
|
||||
BITFIELD (CpuFMA),
|
||||
BITFIELD (CpuFMA4),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (CpuMovbe),
|
||||
BITFIELD (CpuEPT),
|
||||
|
|
|
|||
|
|
@ -21,191 +21,195 @@
|
|||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -86,8 +86,10 @@
|
|||
#define CpuPCLMUL (CpuAES + 1)
|
||||
/* FMA support required */
|
||||
#define CpuFMA (CpuPCLMUL + 1)
|
||||
/* FMA4 support required */
|
||||
#define CpuFMA4 (CpuFMA + 1)
|
||||
/* MOVBE Instuction support required */
|
||||
#define CpuMovbe (CpuFMA + 1)
|
||||
#define CpuMovbe (CpuFMA4 + 1)
|
||||
/* EPT Instructions required */
|
||||
#define CpuEPT (CpuMovbe + 1)
|
||||
/* RDTSCP Instuction support required */
|
||||
|
|
@ -144,6 +146,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuaes:1;
|
||||
unsigned int cpupclmul:1;
|
||||
unsigned int cpufma:1;
|
||||
unsigned int cpufma4:1;
|
||||
unsigned int cpumovbe:1;
|
||||
unsigned int cpuept:1;
|
||||
unsigned int cpurdtscp:1;
|
||||
|
|
|
|||
|
|
@ -2468,6 +2468,73 @@ vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreS
|
|||
vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// FMA4 instructions
|
||||
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// AMD 3DNow! instructions.
|
||||
|
||||
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
|
|
|||
5606
opcodes/i386-tbl.h
5606
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue