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2007-01-04 Paul Brook <paul@codesourcery.com> 

gas/
	* config/tc-arm.c (NEON_ENC_TAB): Fix encoding of vclt, vcle, vaclt
	and vacle.

	gas/testsuite/
	* gas/arm/neon-cov.d: Adjust expected output.
	* gas/arm/neon-omit.s: Add tests for vcgt and vcle.  Reorder vacle
	and vacle.
	* gas/arm/neon-omit.d: Adjust expected output.
This commit is contained in:
Paul Brook 2007-01-04 04:39:53 +00:00
parent 6aa8ef8295
commit 92559b5be6
6 changed files with 48 additions and 32 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2007-01-04 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (NEON_ENC_TAB): Fix encoding of vclt, vcle, vaclt
and vacle.
2007-01-03 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c: Update copyright year.

12
gas/config/tc-arm.c
View File

@ -10222,8 +10222,8 @@ struct neon_tab_entry
X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
/* Register variants of the following two instructions are encoded as
vcge / vcgt with the operands reversed. */ \
X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
@ -15726,10 +15726,10 @@ static const struct asm_opcode insns[] =
NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
NUF(vaclt, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
NUF(vacltq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
NUF(vacle, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
NUF(vacleq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2007-01-04 Paul Brook <paul@codesourcery.com>
* gas/arm/neon-cov.d: Adjust expected output.
* gas/arm/neon-omit.s: Add tests for vcgt and vcle. Reorder vacle
and vacle.
* gas/arm/neon-omit.d: Adjust expected output.
2006-12-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for "shrd %cl,%edx,%eax" and

48
gas/testsuite/gas/arm/neon-cov.d
View File

@ -596,27 +596,6 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e00 vcgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000300 vcgt\.s8 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2100300 vcgt\.s16 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2200300 vcgt\.s32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000300 vcgt\.u8 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100300 vcgt\.u16 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200300 vcgt\.u32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e00 vcgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2000350 vcge\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000350 vcge\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000310 vcge\.s8 d0, d0, d0
@ -638,6 +617,27 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3000e40 vcge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e40 vcge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e00 vcge\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000340 vcgt\.s8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000300 vcgt\.s8 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2100340 vcgt\.s16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2100300 vcgt\.s16 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2200340 vcgt\.s32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2200300 vcgt\.s32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000340 vcgt\.u8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000300 vcgt\.u8 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100340 vcgt\.u16 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100300 vcgt\.u16 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200340 vcgt\.u32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200300 vcgt\.u32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e40 vcgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e00 vcgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3000850 vceq\.i8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000850 vceq\.i8 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000810 vceq\.i8 d0, d0, d0
@ -910,12 +910,12 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0
0[0-9a-f]+ <[^>]+> f2000f10 vrecps\.f32 d0, d0, d0

2
gas/testsuite/gas/arm/neon-omit.d
View File

@ -37,7 +37,9 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f30cae5a vacge\.f32 q5, q6, q5
0[0-9a-f]+ <[^>]+> f320eede vacgt\.f32 q7, q8, q7
0[0-9a-f]+ <[^>]+> f32ee370 vcge\.u32 q7, q7, q8
0[0-9a-f]+ <[^>]+> f32ee360 vcgt\.u32 q7, q7, q8
0[0-9a-f]+ <[^>]+> f320e3de vcge\.u32 q7, q8, q7
0[0-9a-f]+ <[^>]+> f320e3ce vcgt\.u32 q7, q8, q7
0[0-9a-f]+ <[^>]+> f3a22102 vaddw\.u32 q1, q1, d2
0[0-9a-f]+ <[^>]+> f2a66304 vsubw\.s32 q3, q3, d4
0[0-9a-f]+ <[^>]+> f2244856 vtst\.32 q2, q2, q3

6
gas/testsuite/gas/arm/neon-omit.s
View File

@ -33,9 +33,11 @@
vmls.s32 q3,q4
vacge.f q1,q2
vacgt.f q3,q4
vaclt.f q5,q6
vacle.f q7,q8
vacle.f q5,q6
vaclt.f q7,q8
vcge.u32 q7,q8
vcgt.u32 q7,q8
vcle.u32 q7,q8
vclt.u32 q7,q8
vaddw.u32 q1,d2
vsubw.s32 q3,d4