2000-09-11 Kazu Hirata <kazu@hxi.com>
* config/tc-i370.c: Fix formatting. * config/tc-i960.c: Likewise. * config/tc-m68k.c: Likewise.
This commit is contained in:
Kazu Hirata
parent
2bba1017ee
commit
92774660ac
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@ -1,3 +1,9 @@
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2000-09-11 Kazu Hirata <kazu@hxi.com>
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* config/tc-i370.c: Fix formatting.
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* config/tc-i960.c: Likewise.
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* config/tc-m68k.c: Likewise.
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2000-09-09 Philip Blundell <philb@gnu.org>
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* configure.in (arm*-*-uclinux*): New target.
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@ -18,7 +18,7 @@
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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02111-1307, USA. */
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/* This assembler implements a very hacked version of an elf-like thing
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* that gcc emits (when gcc is suitably hacked). To make it behave more
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@ -75,7 +75,6 @@ const char EXP_CHARS[] = "eE";
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as in 0d1.0. */
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const char FLT_CHARS[] = "dD";
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void
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md_show_usage (stream)
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FILE *stream;
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@ -116,7 +115,6 @@ static void i370_elf_lcomm PARAMS ((int));
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static void i370_elf_validate_fix PARAMS ((fixS *, segT));
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#endif
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/* The target specific pseudo-ops which we support. */
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@ -186,7 +184,6 @@ struct pd_reg
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1. r<reg_num> which has the value <reg_num>.
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2. r.<reg_num> which has the value <reg_num>.
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Each floating point register has predefined names of the form:
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1. f<reg_num> which has the value <reg_num>.
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2. f.<reg_num> which has the value <reg_num>.
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@ -194,7 +191,6 @@ struct pd_reg
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There are only four floating point registers, and these are
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commonly labelled 0,2,4 and 6. Thus, there is no f1, f3, etc.
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There are individual registers as well:
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rbase or r.base has the value 3 (base register)
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rpgt or r.pgt has the value 4 (page origin table pointer)
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@ -205,7 +201,7 @@ struct pd_reg
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dsa or r.dsa has the value 13 (stack pointer)
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lr has the value 14 (link reg)
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The table is sorted. Suitable for searching by a binary search. */
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The table is sorted. Suitable for searching by a binary search. */
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static const struct pd_reg pre_defined_registers[] =
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{
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@ -222,7 +218,6 @@ static const struct pd_reg pre_defined_registers[] =
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{ "f4", 4 },
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{ "f6", 6 },
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{ "dsa",13 }, /* stack pointer */
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{ "lr", 14 }, /* Link Register */
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{ "pgt", 4 }, /* Page Origin Table Pointer */
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@ -533,7 +528,7 @@ md_parse_option (c, arg)
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/* Set i370_cpu if it is not already set.
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Currently defaults to the reasonable superset;
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but can be made more fine grained if desred. */
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but can be made more fine grained if desred. */
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static void
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i370_set_cpu ()
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@ -541,7 +536,7 @@ i370_set_cpu ()
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const char *default_os = TARGET_OS;
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const char *default_cpu = TARGET_CPU;
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/* override with the superset for the moment. */
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/* override with the superset for the moment. */
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i370_cpu = I370_OPCODE_ESA390_SUPERSET;
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if (i370_cpu == 0)
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{
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@ -581,7 +576,7 @@ md_begin ()
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i370_set_cpu ();
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#ifdef OBJ_ELF
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/* Set the ELF flags if desired. */
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/* Set the ELF flags if desired. */
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if (i370_flags)
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bfd_set_private_flags (stdoutput, i370_flags);
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#endif
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@ -751,8 +746,8 @@ i370_elf_suffix (str_p, exp_p)
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return BFD_RELOC_UNUSED;
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}
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/* Like normal .long/.short/.word, except support @got, etc. */
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/* clobbers input_line_pointer, checks end-of-line. */
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/* Like normal .long/.short/.word, except support @got, etc. */
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/* clobbers input_line_pointer, checks end-of-line. */
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static void
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i370_elf_cons (nbytes)
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register int nbytes; /* 1=.byte, 2=.word, 4=.long */
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@ -792,7 +787,7 @@ i370_elf_cons (nbytes)
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}
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while (*input_line_pointer++ == ',');
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input_line_pointer--; /* Put terminator back into stream. */
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input_line_pointer--; /* Put terminator back into stream. */
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demand_empty_rest_of_line ();
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}
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@ -1273,11 +1268,10 @@ i370_elf_validate_fix (fixp, seg)
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}
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#endif /* OBJ_ELF */
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#define LITERAL_POOL_SUPPORT
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#ifdef LITERAL_POOL_SUPPORT
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/* Provide support for literal pools within the text section. */
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/* Provide support for literal pools within the text section. */
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/* Loosely based on similar code from tc-arm.c */
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/*
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* We will use four symbols to locate four parts of the literal pool.
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@ -1528,7 +1522,7 @@ i370_addr_offset (expressionS *exx)
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expression (exx);
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/* OK, now we have to subtract the "using" location */
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/* normally branches appear in the text section only... */
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/* normally branches appear in the text section only... */
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if (0 == strncmp (now_seg->name, ".text", 5) || 0 > i370_using_other_regno)
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{
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i370_make_relative (exx, &i370_using_text_baseaddr);
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@ -1755,7 +1749,6 @@ i370_ltorg (ignore)
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else as_bad ("bad alignment of %d bytes in literal pool", biggest_literal_size);
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if (0 == biggest_align) biggest_align = 1;
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/* Align pool for short, word, double word accesses */
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frag_align (biggest_align, 0, 0);
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record_alignment (now_seg, biggest_align);
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@ -1763,7 +1756,7 @@ i370_ltorg (ignore)
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/* Note that the gas listing will print only the first five
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* entries in the pool .... wonder how to make it print more ...
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*/
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/* output largest literals first, then the smaller ones. */
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/* output largest literals first, then the smaller ones. */
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for (litsize=8; litsize; litsize /=2)
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{
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symbolS *current_poolP = NULL;
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@ -1841,13 +1834,13 @@ i370_using (ignore)
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char *star;
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/* if "*" appears in a using, it means "." */
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/* replace it with "." so that expr doesn't get confused. */
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/* replace it with "." so that expr doesn't get confused. */
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star = strchr (input_line_pointer, '*');
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if (star)
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*star = '.';
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/* the first arg to using will usually be ".", but it can
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* be a more complex exprsssion too ... */
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* be a more complex exprsssion too ... */
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expression (&baseaddr);
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if (star)
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*star = '*';
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@ -2171,7 +2164,7 @@ md_assemble (str)
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hold = input_line_pointer;
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input_line_pointer = str;
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/* register names are only allowed where there are registers ... */
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/* register names are only allowed where there are registers ... */
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if ((operand->flags & I370_OPERAND_GPR) != 0)
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{
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/* quickie hack to get past things like (,r13) */
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@ -2189,7 +2182,7 @@ md_assemble (str)
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/* check for a address constant expression */
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/* We will put PSW-relative addresses in the text section,
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* and adress literals in the .data (or other) section. */
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* and adress literals in the .data (or other) section. */
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else if (i370_addr_cons (&ex))
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use_other=1;
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else if (i370_addr_offset (&ex))
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@ -2224,7 +2217,7 @@ md_assemble (str)
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/* Allow @HA, @L, @H on constants.
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* Well actually, no we don't; there really don't make sense
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* (at least not to me) for the i370. However, this code is
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* left here for any dubious future expansion reasons ... */
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* left here for any dubious future expansion reasons ... */
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char *orig_str = str;
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if ((reloc = i370_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED)
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@ -2620,7 +2613,7 @@ md_atof (type, litp, sizep)
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}
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/* 360/370/390 have two float formats: an old, funky 360 single-precision
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* format, and the ieee format. Support only the ieee format. */
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* format, and the ieee format. Support only the ieee format. */
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t = atof_ieee (input_line_pointer, type, words);
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if (t)
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input_line_pointer = t;
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@ -2705,7 +2698,6 @@ md_pcrel_from_section (fixp, sec)
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return fixp->fx_frag->fr_address + fixp->fx_where;
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}
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/* Apply a fixup to the object code. This is called for all the
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fixups we generated by the call to fix_new_exp, above. In the call
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above we used a reloc code which was the largest legal reloc code
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@ -2797,7 +2789,7 @@ md_apply_fix3 (fixp, valuep, seg)
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#endif
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/* Fetch the instruction, insert the fully resolved operand
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value, and stuff the instruction back again.
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fisxp->fx_size is the length of the instruction. */
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fisxp->fx_size is the length of the instruction. */
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where = fixp->fx_frag->fr_literal + fixp->fx_where;
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insn.i[0] = bfd_getb32 ((unsigned char *) where);
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if (6 <= fixp->fx_size)
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@ -2824,7 +2816,7 @@ md_apply_fix3 (fixp, valuep, seg)
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relocs. In fact, we support *zero* operand relocations ...
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Why? Because we are not expecting the compiler to generate
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any operands that need relocation. Due to the 12-bit naturew of
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i370 addressing, this would be unusual. */
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i370 addressing, this would be unusual. */
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#if 0
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if ((operand->flags & I370_OPERAND_RELATIVE) != 0
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&& operand->bits == 12
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@ -1,5 +1,5 @@
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/* tc-i960.c - All the i80960-specific stuff
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Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 1999
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Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
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Free Software Foundation, Inc.
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This file is part of GAS.
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@ -19,7 +19,7 @@
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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/* See comment on md_parse_option for 80960-specific invocation options. */
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/* See comment on md_parse_option for 80960-specific invocation options. */
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/* There are 4 different lengths of (potentially) symbol-based displacements
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in the 80960 instruction set, each of which could require address fix-ups
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@ -178,7 +178,7 @@ const char comment_chars[] = "#";
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#NO_APP at the beginning of its output.
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*/
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/* Also note that comments started like this one will always work. */
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/* Also note that comments started like this one will always work. */
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const char line_comment_chars[] = "";
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@ -192,7 +192,6 @@ const char EXP_CHARS[] = "eE";
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*/
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const char FLT_CHARS[] = "fFdDtT";
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/* Table used by base assembler to relax addresses based on varying length
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instructions. The fields are:
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1) most positive reach of this state,
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@ -242,13 +241,11 @@ const pseudo_typeS md_pseudo_table[] =
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#define adds(e) e.X_add_symbol
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#define offs(e) e.X_add_number
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/* Branch-prediction bits for CTRL/COBR format opcodes */
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#define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
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#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
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#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
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/* Some instruction opcodes that we need explicitly */
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#define BE 0x12000000
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#define BG 0x11000000
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@ -268,14 +265,12 @@ const pseudo_typeS md_pseudo_table[] =
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#define CALLS 0x66003800
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#define RET 0x0a000000
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/* These masks are used to build up a set of MEMB mode bits. */
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/* These masks are used to build up a set of MEMB mode bits. */
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#define A_BIT 0x0400
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#define I_BIT 0x0800
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#define MEMB_BIT 0x1000
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#define D_BIT 0x2000
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/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
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used). */
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#define MEMA_ABASE 0x2000
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@ -294,7 +289,6 @@ typedef struct
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memS;
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/* The two pieces of info we need to generate a register operand */
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struct regop
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{
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@ -303,7 +297,6 @@ struct regop
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int n; /* Register number or literal value */
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};
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/* Number and assembler mnemonic for all registers that can appear in
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operands. */
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static const struct
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@ -449,13 +442,11 @@ aregs[] =
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{ NULL, 0 }, /* END OF LIST */
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};
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/* Hash tables */
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static struct hash_control *op_hash; /* Opcode mnemonics */
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static struct hash_control *reg_hash; /* Register name hash table */
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static struct hash_control *areg_hash; /* Abase register hash table */
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/* Architecture for which we are assembling */
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#define ARCH_ANY 0 /* Default: no architecture checking done */
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#define ARCH_KA 1
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@ -470,7 +461,6 @@ int iclasses_seen; /* OR of instruction classes (I_* constants)
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* instructions.
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*/
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/* BRANCH-PREDICTION INSTRUMENTATION
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The following supports generation of branch-prediction instrumentation
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@ -592,7 +582,6 @@ md_assemble (textP)
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const char *bp_error_msg = _("branch prediction invalid on this opcode");
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/* Parse instruction into opcode and operands */
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memset (args, '\0', sizeof (args));
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n_ops = i_scan (textP, args);
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@ -611,8 +600,6 @@ md_assemble (textP)
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}
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}
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/* Check for branch-prediction suffix on opcode mnemonic, strip it off */
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n = strlen (args[0]) - 1;
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branch_predict = 0;
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@ -735,7 +722,6 @@ md_chars_to_number (val, n)
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return retval;
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}
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#define MAX_LITTLENUMS 6
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#define LNUM_SIZE sizeof(LITTLENUM_TYPE)
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@ -808,7 +794,6 @@ md_atof (type, litP, sizeP)
|
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return 0;
|
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}
|
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/*****************************************************************************
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md_number_to_imm
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@ -822,7 +807,6 @@ md_number_to_imm (buf, val, n)
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md_number_to_chars (buf, val, n);
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}
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/*****************************************************************************
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md_number_to_disp
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@ -918,7 +902,6 @@ md_number_to_field (instrP, val, bfixP)
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|
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A table of all such "Labels" is also generated.
|
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-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
|
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Select the 80960 architecture. Instructions or features not
|
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supported by the selected architecture cause fatal errors.
|
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|
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@ -1264,7 +1247,6 @@ cobr_fmt (arg, opcode, oP)
|
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instr |= (regop.n << 14) | regop.special;
|
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}
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|
||||
|
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if (n < 3)
|
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{
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emit (instr);
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@ -1293,7 +1275,6 @@ cobr_fmt (arg, opcode, oP)
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}
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} /* cobr_fmt() */
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/*****************************************************************************
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ctrl_fmt: generate a CTRL-format instruction
|
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|
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|
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@ -1309,7 +1290,6 @@ ctrl_fmt (targP, opcode, num_ops)
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* how often the branch is taken
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*/
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if (num_ops == 0)
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{
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emit (opcode); /* Output opcode */
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|
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@ -1339,7 +1319,6 @@ ctrl_fmt (targP, opcode, num_ops)
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|
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}
|
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|
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/*****************************************************************************
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emit: output instruction binary
|
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|
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@ -1359,7 +1338,6 @@ emit (instr)
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return toP;
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}
|
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|
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/*****************************************************************************
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get_args: break individual arguments out of comma-separated list
|
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|
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|
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@ -1439,7 +1417,6 @@ get_args (p, args)
|
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return n;
|
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}
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/*****************************************************************************
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get_cdisp: handle displacement for a COBR or CTRL instruction.
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|
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@ -1529,7 +1506,6 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
|
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}
|
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}
|
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|
||||
|
||||
/*****************************************************************************
|
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get_ispec: parse a memory operand for an index specification
|
||||
|
||||
|
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@ -1600,7 +1576,6 @@ get_regnum (regname)
|
|||
return (rP == NULL) ? -1 : *rP;
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
i_scan: perform lexical scan of ascii assembler instruction.
|
||||
|
||||
|
|
@ -1621,7 +1596,7 @@ get_regnum (regname)
|
|||
*************************************************************************** */
|
||||
static int
|
||||
i_scan (iP, args)
|
||||
/* Pointer to ascii instruction; MUCKED BY US. */
|
||||
/* Pointer to ascii instruction; MUCKED BY US. */
|
||||
register char *iP;
|
||||
/* Output arg: pointers to opcode and operands placed here. MUST
|
||||
ACCOMMODATE 4 ENTRIES. */
|
||||
|
|
@ -1652,7 +1627,6 @@ i_scan (iP, args)
|
|||
return (get_args (iP, args));
|
||||
} /* i_scan() */
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
mem_fmt: generate a MEMA- or MEMB-format instruction
|
||||
|
||||
|
|
@ -1680,7 +1654,7 @@ mem_fmt (args, oP, callx)
|
|||
memset (&instr, '\0', sizeof (memS));
|
||||
instr.opcode = oP->opcode;
|
||||
|
||||
/* Process operands. */
|
||||
/* Process operands. */
|
||||
for (i = 1; i <= oP->num_ops; i++)
|
||||
{
|
||||
opdesc = oP->operand[i - 1];
|
||||
|
|
@ -1771,7 +1745,6 @@ mem_fmt (args, oP, callx)
|
|||
}
|
||||
} /* memfmt() */
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
|
||||
|
||||
|
|
@ -1804,7 +1777,6 @@ mema_to_memb (opcodeP)
|
|||
md_number_to_chars (opcodeP, opcode, 4);
|
||||
} /* mema_to_memb() */
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
parse_expr: parse an expression
|
||||
|
||||
|
|
@ -1858,7 +1830,6 @@ parse_expr (textP, expP)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
parse_ldcont:
|
||||
Parse and replace a 'ldconst' pseudo-instruction with an appropriate
|
||||
|
|
@ -1885,7 +1856,6 @@ parse_ldconst (arg)
|
|||
static char buf2[5]; /* Literal for second operand */
|
||||
expressionS e; /* Parsed expression */
|
||||
|
||||
|
||||
arg[3] = NULL; /* So we can tell at the end if it got used or not */
|
||||
|
||||
parse_expr (arg[1], &e);
|
||||
|
|
@ -2020,7 +1990,6 @@ parse_memop (memP, argP, optype)
|
|||
16 /* MEM16 */
|
||||
};
|
||||
|
||||
|
||||
iprel_flag = mode = 0;
|
||||
|
||||
/* Any index present? */
|
||||
|
|
@ -2208,7 +2177,7 @@ parse_po (po_num)
|
|||
|
||||
extern char is_end_of_line[];
|
||||
|
||||
/* Advance input pointer to end of line. */
|
||||
/* Advance input pointer to end of line. */
|
||||
p = input_line_pointer;
|
||||
while (!is_end_of_line[(unsigned char) *input_line_pointer])
|
||||
{
|
||||
|
|
@ -2358,7 +2327,6 @@ reg_fmt (args, oP)
|
|||
struct regop regop; /* Description of register operand */
|
||||
int n_ops; /* Number of operands */
|
||||
|
||||
|
||||
instr = oP->opcode;
|
||||
n_ops = oP->num_ops;
|
||||
|
||||
|
|
@ -2425,7 +2393,6 @@ reg_fmt (args, oP)
|
|||
emit (instr);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
relax_cobr:
|
||||
Replace cobr instruction in a code fragment with equivalent branch and
|
||||
|
|
@ -2512,7 +2479,6 @@ relax_cobr (fragP)
|
|||
frag_wane (fragP);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
reloc_callj: Relocate a 'callj' instruction
|
||||
|
||||
|
|
@ -2580,7 +2546,6 @@ reloc_callj (fixP)
|
|||
/* else Symbol is neither a sysproc nor a leafproc */
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
s_leafproc: process .leafproc pseudo-op
|
||||
|
||||
|
|
@ -2610,7 +2575,7 @@ s_leafproc (n_ops, args)
|
|||
return;
|
||||
} /* Check number of arguments */
|
||||
|
||||
/* Find or create symbol for 'call' entry point. */
|
||||
/* Find or create symbol for 'call' entry point. */
|
||||
callP = symbol_find_or_make (args[1]);
|
||||
|
||||
if (TC_S_IS_CALLNAME (callP))
|
||||
|
|
@ -2644,7 +2609,6 @@ s_leafproc (n_ops, args)
|
|||
} /* if only one arg, or the args are the same */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
s_sysproc: process .sysproc pseudo-op
|
||||
|
||||
|
|
@ -2670,7 +2634,7 @@ s_sysproc (n_ops, args)
|
|||
return;
|
||||
} /* bad arg count */
|
||||
|
||||
/* Parse "entry_num" argument and check it for validity. */
|
||||
/* Parse "entry_num" argument and check it for validity. */
|
||||
parse_expr (args[2], &exp);
|
||||
if (exp.X_op != O_constant
|
||||
|| (offs (exp) < 0)
|
||||
|
|
@ -2692,7 +2656,6 @@ s_sysproc (n_ops, args)
|
|||
TC_S_FORCE_TO_SYSPROC (symP);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
shift_ok:
|
||||
Determine if a "shlo" instruction can be used to implement a "ldconst".
|
||||
|
|
@ -2729,7 +2692,6 @@ shift_ok (n)
|
|||
return shift;
|
||||
}
|
||||
|
||||
|
||||
/* syntax: issue syntax error */
|
||||
|
||||
static void
|
||||
|
|
@ -2738,7 +2700,6 @@ syntax ()
|
|||
as_bad (_("syntax error"));
|
||||
} /* syntax() */
|
||||
|
||||
|
||||
/* targ_has_sfr:
|
||||
|
||||
Return TRUE iff the target architecture supports the specified
|
||||
|
|
@ -2764,7 +2725,6 @@ targ_has_sfr (n)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/* targ_has_iclass:
|
||||
|
||||
Return TRUE iff the target architecture supports the indicated
|
||||
|
|
@ -2826,7 +2786,7 @@ s_endian (ignore)
|
|||
demand_empty_rest_of_line ();
|
||||
}
|
||||
|
||||
/* We have no need to default values of symbols. */
|
||||
/* We have no need to default values of symbols. */
|
||||
|
||||
/* ARGSUSED */
|
||||
symbolS *
|
||||
|
|
@ -2838,7 +2798,7 @@ md_undefined_symbol (name)
|
|||
|
||||
/* Exactly what point is a PC-relative offset relative TO?
|
||||
On the i960, they're relative to the address of the instruction,
|
||||
which we have set up as the address of the fixup too. */
|
||||
which we have set up as the address of the fixup too. */
|
||||
long
|
||||
md_pcrel_from (fixP)
|
||||
fixS *fixP;
|
||||
|
|
@ -2940,7 +2900,7 @@ tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
|
|||
ri.r_index = S_GET_TYPE (symbolP);
|
||||
}
|
||||
|
||||
/* Output the relocation information in machine-dependent form. */
|
||||
/* Output the relocation information in machine-dependent form. */
|
||||
md_ri_to_chars (where, &ri);
|
||||
}
|
||||
|
||||
|
|
@ -3248,7 +3208,7 @@ i960_validate_fix (fixP, this_segment_type, add_symbolPP)
|
|||
if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
|
||||
{
|
||||
/* Relocation should be done via the associated 'bal'
|
||||
entry point symbol. */
|
||||
entry point symbol. */
|
||||
|
||||
if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
|
||||
{
|
||||
|
|
@ -3273,7 +3233,7 @@ i960_validate_fix (fixP, this_segment_type, add_symbolPP)
|
|||
displacement and are only to be used for local branches:
|
||||
flag as error, don't generate relocation. */
|
||||
as_bad (_("can't use COBR format with external label"));
|
||||
fixP->fx_addsy = NULL; /* No relocations please. */
|
||||
fixP->fx_addsy = NULL; /* No relocations please. */
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,8 +46,8 @@ const char *m68k_comment_chars = "|";
|
|||
.line and .file directives will appear in the pre-processed output */
|
||||
/* Note that input_file.c hand checks for '#' at the beginning of the
|
||||
first line of the input file. This is because the compiler outputs
|
||||
#NO_APP at the beginning of its output. */
|
||||
/* Also note that comments like this one will always work. */
|
||||
#NO_APP at the beginning of its output. */
|
||||
/* Also note that comments like this one will always work. */
|
||||
const char line_comment_chars[] = "#*";
|
||||
|
||||
const char line_separator_chars[] = ";";
|
||||
|
|
@ -68,7 +68,7 @@ const int md_reloc_size = 8; /* Size of relocation record */
|
|||
|
||||
/* Are we trying to generate PIC code? If so, absolute references
|
||||
ought to be made into linkage table references or pc-relative
|
||||
references. Not implemented. For ELF there are other means
|
||||
references. Not implemented. For ELF there are other means
|
||||
to denote pic relocations. */
|
||||
int flag_want_pic;
|
||||
|
||||
|
|
@ -195,7 +195,7 @@ static const enum m68k_register m68060_control_regs[] = {
|
|||
0
|
||||
};
|
||||
static const enum m68k_register mcf_control_regs[] = {
|
||||
CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
|
||||
CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
|
||||
RAMBAR0, RAMBAR1, MBAR,
|
||||
0
|
||||
};
|
||||
|
|
@ -437,7 +437,7 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]);
|
|||
on the 68000. The 68000 doesn't support long branches with branchs */
|
||||
|
||||
/* This table desribes how you change sizes for the various types of variable
|
||||
size expressions. This version only supports two kinds. */
|
||||
size expressions. This version only supports two kinds. */
|
||||
|
||||
/* Note that calls to frag_var need to specify the maximum expansion
|
||||
needed; this is currently 10 bytes for DBCC. */
|
||||
|
|
@ -563,7 +563,6 @@ const pseudo_typeS md_pseudo_table[] =
|
|||
{0, 0, 0}
|
||||
};
|
||||
|
||||
|
||||
/* The mote pseudo ops are put into the opcode table, since they
|
||||
don't start with a . they look like opcodes to gas.
|
||||
*/
|
||||
|
|
@ -794,7 +793,7 @@ int
|
|||
tc_m68k_fix_adjustable (fixP)
|
||||
fixS *fixP;
|
||||
{
|
||||
/* Prevent all adjustments to global symbols. */
|
||||
/* Prevent all adjustments to global symbols. */
|
||||
if (S_IS_EXTERNAL (fixP->fx_addsy)
|
||||
|| S_IS_WEAK (fixP->fx_addsy))
|
||||
return 0;
|
||||
|
|
@ -955,7 +954,7 @@ tc_gen_reloc (section, fixp)
|
|||
#define relaxable_symbol(symbol) 1
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Handle of the OPCODE hash table. NULL means any use before
|
||||
m68k_ip_begin() will crash. */
|
||||
static struct hash_control *op_hash;
|
||||
|
|
@ -984,7 +983,7 @@ m68k_ip (instring)
|
|||
instring++; /* skip leading whitespace */
|
||||
|
||||
/* Scan up to end of operation-code, which MUST end in end-of-string
|
||||
or exactly 1 space. */
|
||||
or exactly 1 space. */
|
||||
pdot = 0;
|
||||
for (p = instring; *p != '\0'; p++)
|
||||
{
|
||||
|
|
@ -1093,7 +1092,7 @@ m68k_ip (instring)
|
|||
for (losing = 0;;)
|
||||
{
|
||||
/* If we didn't get the right number of ops, or we have no
|
||||
common model with this pattern then reject this pattern. */
|
||||
common model with this pattern then reject this pattern. */
|
||||
|
||||
ok_arch |= opcode->m_arch;
|
||||
if (opsfound != opcode->m_opnum
|
||||
|
|
@ -1756,7 +1755,7 @@ m68k_ip (instring)
|
|||
&& opP->reg != BC))
|
||||
{
|
||||
losing++;
|
||||
} /* not a cache specifier. */
|
||||
} /* not a cache specifier. */
|
||||
break;
|
||||
|
||||
case '_':
|
||||
|
|
@ -1769,7 +1768,7 @@ m68k_ip (instring)
|
|||
losing++;
|
||||
/* FIXME: kludge instead of fixing parser:
|
||||
upper/lower registers are *not* CONTROL
|
||||
registers, but ordinary ones. */
|
||||
registers, but ordinary ones. */
|
||||
if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
|
||||
|| (opP->reg >= DATA0U && opP->reg <= DATA7U))
|
||||
opP->mode = DREG;
|
||||
|
|
@ -1789,7 +1788,7 @@ m68k_ip (instring)
|
|||
if (!losing)
|
||||
{
|
||||
break;
|
||||
} /* got it. */
|
||||
} /* got it. */
|
||||
|
||||
opcode = opcode->m_next;
|
||||
|
||||
|
|
@ -2145,9 +2144,9 @@ m68k_ip (instring)
|
|||
&& m68k_index_width_default == SIZE_LONG))
|
||||
nextword |= 0x800;
|
||||
|
||||
if ((opP->index.scale != 1
|
||||
if ((opP->index.scale != 1
|
||||
&& cpu_of_arch (current_architecture) < m68020)
|
||||
|| (opP->index.scale == 8
|
||||
|| (opP->index.scale == 8
|
||||
&& arch_coldfire_p (current_architecture)))
|
||||
{
|
||||
opP->error =
|
||||
|
|
@ -2823,7 +2822,7 @@ m68k_ip (instring)
|
|||
install_operand (s[1], tmpreg);
|
||||
break;
|
||||
#ifndef NO_68851
|
||||
/* JF: These are out of order, I fear. */
|
||||
/* JF: These are out of order, I fear. */
|
||||
case 'f':
|
||||
switch (opP->reg)
|
||||
{
|
||||
|
|
@ -2961,7 +2960,7 @@ m68k_ip (instring)
|
|||
}
|
||||
|
||||
/* By the time whe get here (FINALLY) the_ins contains the complete
|
||||
instruction, ready to be emitted. . . */
|
||||
instruction, ready to be emitted. . . */
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -3427,7 +3426,7 @@ static const struct init_entry init_table[] =
|
|||
{ "za6", ZADDR6 },
|
||||
{ "za7", ZADDR7 },
|
||||
|
||||
/* Upper and lower data and address registers, used by macw and msacw. */
|
||||
/* Upper and lower data and address registers, used by macw and msacw. */
|
||||
{ "d0l", DATA0L },
|
||||
{ "d1l", DATA1L },
|
||||
{ "d2l", DATA2L },
|
||||
|
|
@ -3725,7 +3724,7 @@ md_begin ()
|
|||
{
|
||||
ins = &m68k_opcodes[i];
|
||||
/* We *could* ignore insns that don't match our arch here
|
||||
but just leaving them out of the hash. */
|
||||
but just leaving them out of the hash. */
|
||||
slak->m_operands = ins->args;
|
||||
slak->m_opnum = strlen (slak->m_operands) / 2;
|
||||
slak->m_arch = ins->arch;
|
||||
|
|
@ -4284,7 +4283,7 @@ md_convert_frag_1 (fragP)
|
|||
|
||||
/* Address in gas core of the place to store the displacement. */
|
||||
/* This convinces the native rs6000 compiler to generate the code we
|
||||
want. */
|
||||
want. */
|
||||
register char *buffer_address = fragP->fr_literal;
|
||||
buffer_address += fragP->fr_fix;
|
||||
/* end ibm compiler workaround */
|
||||
|
|
@ -4322,7 +4321,7 @@ md_convert_frag_1 (fragP)
|
|||
{
|
||||
if (flag_keep_pcrel)
|
||||
as_bad (_("long branch not supported"));
|
||||
|
||||
|
||||
if (fragP->fr_opcode[0] == 0x61)
|
||||
/* BSR */
|
||||
{
|
||||
|
|
@ -4354,7 +4353,7 @@ md_convert_frag_1 (fragP)
|
|||
{
|
||||
/* This should never happen, because if it's a conditional
|
||||
branch and we are on a 68000, BCC68000 should have been
|
||||
picked instead of ABRANCH. */
|
||||
picked instead of ABRANCH. */
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
|
|
@ -4369,13 +4368,13 @@ md_convert_frag_1 (fragP)
|
|||
/* change bcc into b!cc/jmp absl long */
|
||||
if (flag_keep_pcrel)
|
||||
as_bad (_("long branch not supported"));
|
||||
|
||||
|
||||
fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
|
||||
fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
|
||||
|
||||
/* JF: these used to be fr_opcode[2,3], but they may be in a
|
||||
different frag, in which case refering to them is a no-no.
|
||||
Only fr_opcode[0,1] are guaranteed to work. */
|
||||
Only fr_opcode[0,1] are guaranteed to work. */
|
||||
*buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
|
||||
*buffer_address++ = (char) 0xf9;
|
||||
fragP->fr_fix += 2; /* account for jmp instruction */
|
||||
|
|
@ -4586,7 +4585,7 @@ md_estimate_size_before_relax (fragP, segment)
|
|||
{
|
||||
/* This should never happen, because if it's a conditional
|
||||
branch and we are on a 68000, BCC68000 should have been
|
||||
picked instead of ABRANCH. */
|
||||
picked instead of ABRANCH. */
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
|
|
@ -4699,10 +4698,10 @@ md_estimate_size_before_relax (fragP, segment)
|
|||
else
|
||||
{
|
||||
/* Change dbcc into dbcc/bral. */
|
||||
/* JF: these used to be fr_opcode[2-4], which is wrong. */
|
||||
/* JF: these used to be fr_opcode[2-4], which is wrong. */
|
||||
buffer_address[0] = 0x00; /* branch offset = 4 */
|
||||
buffer_address[1] = 0x04;
|
||||
buffer_address[2] = 0x60; /* put in bra pc + ... */
|
||||
buffer_address[2] = 0x60; /* put in bra pc + ... */
|
||||
/* JF: these were fr_opcode[5-7] */
|
||||
buffer_address[3] = 0x06; /* Plus 6 */
|
||||
if (HAVE_LONG_BRANCH (current_architecture))
|
||||
|
|
@ -4808,7 +4807,7 @@ md_estimate_size_before_relax (fragP, segment)
|
|||
bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
|
||||
nibble as nuthin. (on Sun 3 at least) */
|
||||
/* Translate the internal relocation information into target-specific
|
||||
format. */
|
||||
format. */
|
||||
#ifdef comment
|
||||
void
|
||||
md_ri_to_chars (the_bytes, ri)
|
||||
|
|
@ -5090,7 +5089,7 @@ s_even (ignore)
|
|||
|
||||
temp = 1; /* JF should be 2? */
|
||||
temp_fill = get_absolute_expression ();
|
||||
if (!need_pass_2) /* Never make frag if expect extra pass. */
|
||||
if (!need_pass_2) /* Never make frag if expect extra pass. */
|
||||
frag_align (temp, (int) temp_fill, 0);
|
||||
demand_empty_rest_of_line ();
|
||||
record_alignment (now_seg, temp);
|
||||
|
|
@ -5953,7 +5952,7 @@ build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
|
|||
cc = reverse_mri_condition (cc);
|
||||
truelab = falselab;
|
||||
}
|
||||
|
||||
|
||||
if (leftstart != NULL)
|
||||
{
|
||||
buf = (char *) xmalloc (20
|
||||
|
|
@ -5975,7 +5974,7 @@ build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
|
|||
mri_assemble (buf);
|
||||
free (buf);
|
||||
}
|
||||
|
||||
|
||||
buf = (char *) xmalloc (20 + strlen (truelab));
|
||||
s = buf;
|
||||
*s++ = 'b';
|
||||
|
|
@ -7127,7 +7126,7 @@ md_section_align (segment, size)
|
|||
/* Exactly what point is a PC-relative offset relative TO?
|
||||
On the 68k, it is relative to the address of the first extension
|
||||
word. The difference between the addresses of the offset and the
|
||||
first extension word is stored in fx_pcrel_adjust. */
|
||||
first extension word is stored in fx_pcrel_adjust. */
|
||||
long
|
||||
md_pcrel_from (fixP)
|
||||
fixS *fixP;
|
||||
|
|
|
|||
Loading…
Reference in New Issue