2000-09-11 Kazu Hirata <kazu@hxi.com>
* config/tc-i370.c: Fix formatting. * config/tc-i960.c: Likewise. * config/tc-m68k.c: Likewise.
This commit is contained in:
Kazu Hirata
parent
2bba1017ee
commit
92774660ac
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@ -1,3 +1,9 @@
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2000-09-11 Kazu Hirata <kazu@hxi.com>
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* config/tc-i370.c: Fix formatting.
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* config/tc-i960.c: Likewise.
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* config/tc-m68k.c: Likewise.
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2000-09-09 Philip Blundell <philb@gnu.org>
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* configure.in (arm*-*-uclinux*): New target.
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@ -75,7 +75,6 @@ const char EXP_CHARS[] = "eE";
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as in 0d1.0. */
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const char FLT_CHARS[] = "dD";
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void
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md_show_usage (stream)
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FILE *stream;
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@ -116,7 +115,6 @@ static void i370_elf_lcomm PARAMS ((int));
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static void i370_elf_validate_fix PARAMS ((fixS *, segT));
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#endif
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/* The target specific pseudo-ops which we support. */
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@ -186,7 +184,6 @@ struct pd_reg
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1. r<reg_num> which has the value <reg_num>.
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2. r.<reg_num> which has the value <reg_num>.
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Each floating point register has predefined names of the form:
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1. f<reg_num> which has the value <reg_num>.
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2. f.<reg_num> which has the value <reg_num>.
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@ -194,7 +191,6 @@ struct pd_reg
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There are only four floating point registers, and these are
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commonly labelled 0,2,4 and 6. Thus, there is no f1, f3, etc.
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There are individual registers as well:
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rbase or r.base has the value 3 (base register)
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rpgt or r.pgt has the value 4 (page origin table pointer)
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@ -222,7 +218,6 @@ static const struct pd_reg pre_defined_registers[] =
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{ "f4", 4 },
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{ "f6", 6 },
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{ "dsa",13 }, /* stack pointer */
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{ "lr", 14 }, /* Link Register */
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{ "pgt", 4 }, /* Page Origin Table Pointer */
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@ -1273,7 +1268,6 @@ i370_elf_validate_fix (fixp, seg)
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}
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#endif /* OBJ_ELF */
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#define LITERAL_POOL_SUPPORT
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#ifdef LITERAL_POOL_SUPPORT
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@ -1755,7 +1749,6 @@ i370_ltorg (ignore)
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else as_bad ("bad alignment of %d bytes in literal pool", biggest_literal_size);
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if (0 == biggest_align) biggest_align = 1;
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/* Align pool for short, word, double word accesses */
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frag_align (biggest_align, 0, 0);
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record_alignment (now_seg, biggest_align);
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@ -2705,7 +2698,6 @@ md_pcrel_from_section (fixp, sec)
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return fixp->fx_frag->fr_address + fixp->fx_where;
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}
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/* Apply a fixup to the object code. This is called for all the
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fixups we generated by the call to fix_new_exp, above. In the call
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above we used a reloc code which was the largest legal reloc code
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@ -1,5 +1,5 @@
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/* tc-i960.c - All the i80960-specific stuff
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Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 1999
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Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
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Free Software Foundation, Inc.
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This file is part of GAS.
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@ -192,7 +192,6 @@ const char EXP_CHARS[] = "eE";
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*/
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const char FLT_CHARS[] = "fFdDtT";
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/* Table used by base assembler to relax addresses based on varying length
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instructions. The fields are:
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1) most positive reach of this state,
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@ -242,13 +241,11 @@ const pseudo_typeS md_pseudo_table[] =
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#define adds(e) e.X_add_symbol
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#define offs(e) e.X_add_number
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/* Branch-prediction bits for CTRL/COBR format opcodes */
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#define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
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#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
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#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
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/* Some instruction opcodes that we need explicitly */
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#define BE 0x12000000
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#define BG 0x11000000
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@ -268,14 +265,12 @@ const pseudo_typeS md_pseudo_table[] =
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#define CALLS 0x66003800
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#define RET 0x0a000000
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/* These masks are used to build up a set of MEMB mode bits. */
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#define A_BIT 0x0400
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#define I_BIT 0x0800
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#define MEMB_BIT 0x1000
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#define D_BIT 0x2000
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/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
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used). */
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#define MEMA_ABASE 0x2000
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@ -294,7 +289,6 @@ typedef struct
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memS;
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/* The two pieces of info we need to generate a register operand */
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struct regop
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{
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@ -303,7 +297,6 @@ struct regop
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int n; /* Register number or literal value */
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};
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/* Number and assembler mnemonic for all registers that can appear in
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operands. */
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static const struct
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@ -449,13 +442,11 @@ aregs[] =
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{ NULL, 0 }, /* END OF LIST */
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};
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/* Hash tables */
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static struct hash_control *op_hash; /* Opcode mnemonics */
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static struct hash_control *reg_hash; /* Register name hash table */
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static struct hash_control *areg_hash; /* Abase register hash table */
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/* Architecture for which we are assembling */
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#define ARCH_ANY 0 /* Default: no architecture checking done */
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#define ARCH_KA 1
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@ -470,7 +461,6 @@ int iclasses_seen; /* OR of instruction classes (I_* constants)
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* instructions.
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*/
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/* BRANCH-PREDICTION INSTRUMENTATION
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The following supports generation of branch-prediction instrumentation
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@ -592,7 +582,6 @@ md_assemble (textP)
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const char *bp_error_msg = _("branch prediction invalid on this opcode");
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/* Parse instruction into opcode and operands */
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memset (args, '\0', sizeof (args));
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n_ops = i_scan (textP, args);
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@ -611,8 +600,6 @@ md_assemble (textP)
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}
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}
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/* Check for branch-prediction suffix on opcode mnemonic, strip it off */
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n = strlen (args[0]) - 1;
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branch_predict = 0;
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@ -735,7 +722,6 @@ md_chars_to_number (val, n)
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return retval;
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}
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#define MAX_LITTLENUMS 6
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#define LNUM_SIZE sizeof(LITTLENUM_TYPE)
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@ -808,7 +794,6 @@ md_atof (type, litP, sizeP)
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return 0;
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}
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/*****************************************************************************
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md_number_to_imm
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@ -822,7 +807,6 @@ md_number_to_imm (buf, val, n)
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md_number_to_chars (buf, val, n);
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}
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/*****************************************************************************
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md_number_to_disp
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@ -918,7 +902,6 @@ md_number_to_field (instrP, val, bfixP)
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A table of all such "Labels" is also generated.
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-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
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Select the 80960 architecture. Instructions or features not
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supported by the selected architecture cause fatal errors.
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@ -1264,7 +1247,6 @@ cobr_fmt (arg, opcode, oP)
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instr |= (regop.n << 14) | regop.special;
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}
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if (n < 3)
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{
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emit (instr);
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@ -1293,7 +1275,6 @@ cobr_fmt (arg, opcode, oP)
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}
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} /* cobr_fmt() */
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/*****************************************************************************
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ctrl_fmt: generate a CTRL-format instruction
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@ -1309,7 +1290,6 @@ ctrl_fmt (targP, opcode, num_ops)
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* how often the branch is taken
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*/
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if (num_ops == 0)
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{
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emit (opcode); /* Output opcode */
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@ -1339,7 +1319,6 @@ ctrl_fmt (targP, opcode, num_ops)
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}
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/*****************************************************************************
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emit: output instruction binary
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@ -1359,7 +1338,6 @@ emit (instr)
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return toP;
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}
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/*****************************************************************************
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get_args: break individual arguments out of comma-separated list
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@ -1439,7 +1417,6 @@ get_args (p, args)
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return n;
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}
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/*****************************************************************************
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get_cdisp: handle displacement for a COBR or CTRL instruction.
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@ -1529,7 +1506,6 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
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}
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}
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/*****************************************************************************
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get_ispec: parse a memory operand for an index specification
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@ -1600,7 +1576,6 @@ get_regnum (regname)
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return (rP == NULL) ? -1 : *rP;
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}
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/*****************************************************************************
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i_scan: perform lexical scan of ascii assembler instruction.
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@ -1652,7 +1627,6 @@ i_scan (iP, args)
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return (get_args (iP, args));
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} /* i_scan() */
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/*****************************************************************************
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mem_fmt: generate a MEMA- or MEMB-format instruction
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@ -1771,7 +1745,6 @@ mem_fmt (args, oP, callx)
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}
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} /* memfmt() */
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/*****************************************************************************
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mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
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@ -1804,7 +1777,6 @@ mema_to_memb (opcodeP)
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md_number_to_chars (opcodeP, opcode, 4);
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} /* mema_to_memb() */
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/*****************************************************************************
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parse_expr: parse an expression
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@ -1858,7 +1830,6 @@ parse_expr (textP, expP)
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}
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}
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/*****************************************************************************
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parse_ldcont:
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Parse and replace a 'ldconst' pseudo-instruction with an appropriate
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@ -1885,7 +1856,6 @@ parse_ldconst (arg)
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static char buf2[5]; /* Literal for second operand */
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expressionS e; /* Parsed expression */
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arg[3] = NULL; /* So we can tell at the end if it got used or not */
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parse_expr (arg[1], &e);
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@ -2020,7 +1990,6 @@ parse_memop (memP, argP, optype)
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16 /* MEM16 */
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};
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iprel_flag = mode = 0;
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/* Any index present? */
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@ -2358,7 +2327,6 @@ reg_fmt (args, oP)
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struct regop regop; /* Description of register operand */
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int n_ops; /* Number of operands */
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instr = oP->opcode;
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n_ops = oP->num_ops;
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@ -2425,7 +2393,6 @@ reg_fmt (args, oP)
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emit (instr);
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}
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/*****************************************************************************
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relax_cobr:
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Replace cobr instruction in a code fragment with equivalent branch and
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@ -2512,7 +2479,6 @@ relax_cobr (fragP)
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frag_wane (fragP);
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}
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/*****************************************************************************
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reloc_callj: Relocate a 'callj' instruction
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@ -2580,7 +2546,6 @@ reloc_callj (fixP)
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/* else Symbol is neither a sysproc nor a leafproc */
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}
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/*****************************************************************************
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s_leafproc: process .leafproc pseudo-op
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@ -2644,7 +2609,6 @@ s_leafproc (n_ops, args)
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} /* if only one arg, or the args are the same */
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}
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/*
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s_sysproc: process .sysproc pseudo-op
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@ -2692,7 +2656,6 @@ s_sysproc (n_ops, args)
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TC_S_FORCE_TO_SYSPROC (symP);
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}
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/*****************************************************************************
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shift_ok:
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Determine if a "shlo" instruction can be used to implement a "ldconst".
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@ -2729,7 +2692,6 @@ shift_ok (n)
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return shift;
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}
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/* syntax: issue syntax error */
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static void
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@ -2738,7 +2700,6 @@ syntax ()
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as_bad (_("syntax error"));
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} /* syntax() */
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/* targ_has_sfr:
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Return TRUE iff the target architecture supports the specified
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@ -2764,7 +2725,6 @@ targ_has_sfr (n)
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}
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}
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/* targ_has_iclass:
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Return TRUE iff the target architecture supports the indicated
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@ -563,7 +563,6 @@ const pseudo_typeS md_pseudo_table[] =
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{0, 0, 0}
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};
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/* The mote pseudo ops are put into the opcode table, since they
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don't start with a . they look like opcodes to gas.
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*/
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