From 93c6c0152b36ea7c3ae33b588e67c8ea0089b7eb Mon Sep 17 00:00:00 2001
From: Doug Evans <dje@google.com>
Date: Tue, 5 Oct 1999 01:27:35 +0000
Subject: [PATCH] 	* gas/m32r/error.exp: New testcase driver. 	*
 gas/m32r/m32rx.exp: New testcase driver. 	* gas/m32r/fslotx.[sd]: New
 testcase. 	* gas/m32r/m32rx.[sd]: New testcase. 	*
 gas/m32r/relax-s.[sd]: New testcase. 	* gas/m32r/interfere.s: New testcase. 
 * gas/m32r/wrongsize.s: New testcase.

---
 gas/testsuite/ChangeLog            |  10 +
 gas/testsuite/gas/m32r/error.exp   |  15 +
 gas/testsuite/gas/m32r/fslotx.d    |  23 ++
 gas/testsuite/gas/m32r/fslotx.s    |  19 +
 gas/testsuite/gas/m32r/interfere.s |  14 +
 gas/testsuite/gas/m32r/m32rx.d     | 337 ++++++++++++++++
 gas/testsuite/gas/m32r/m32rx.exp   |   7 +
 gas/testsuite/gas/m32r/m32rx.s     | 590 +++++++++++++++++++++++++++++
 gas/testsuite/gas/m32r/relax-2.d   |  18 +
 gas/testsuite/gas/m32r/relax-2.s   |  11 +
 gas/testsuite/gas/m32r/wrongsize.s |  10 +
 11 files changed, 1054 insertions(+)
 create mode 100644 gas/testsuite/gas/m32r/error.exp
 create mode 100644 gas/testsuite/gas/m32r/fslotx.d
 create mode 100644 gas/testsuite/gas/m32r/fslotx.s
 create mode 100644 gas/testsuite/gas/m32r/interfere.s
 create mode 100644 gas/testsuite/gas/m32r/m32rx.d
 create mode 100644 gas/testsuite/gas/m32r/m32rx.exp
 create mode 100644 gas/testsuite/gas/m32r/m32rx.s
 create mode 100644 gas/testsuite/gas/m32r/relax-2.d
 create mode 100644 gas/testsuite/gas/m32r/relax-2.s
 create mode 100644 gas/testsuite/gas/m32r/wrongsize.s

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index c400d61cf9..b47a215dc3 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+Mon Oct  4 18:25:49 1999  Doug Evans  <devans@canuck.cygnus.com>
+
+	* gas/m32r/error.exp: New testcase driver.
+	* gas/m32r/m32rx.exp: New testcase driver.
+	* gas/m32r/fslotx.[sd]: New testcase.
+	* gas/m32r/m32rx.[sd]: New testcase.
+	* gas/m32r/relax-s.[sd]: New testcase.
+	* gas/m32r/interfere.s: New testcase.
+	* gas/m32r/wrongsize.s: New testcase.
+
 1999-09-17  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
 	* gas/i386/i386.exp: Enable reloc and white tests for COFF.
diff --git a/gas/testsuite/gas/m32r/error.exp b/gas/testsuite/gas/m32r/error.exp
new file mode 100644
index 0000000000..a188719b74
--- /dev/null
+++ b/gas/testsuite/gas/m32r/error.exp
@@ -0,0 +1,15 @@
+# Test assembler warnings and errors.
+
+if [istarget m32r-*-*] {
+
+    load_lib gas-dg.exp
+
+    dg-init
+
+    dg-runtest "$srcdir/$subdir/wrongsize.s" "" ""
+    dg-runtest "$srcdir/$subdir/interfere.s" "" ""
+    dg-runtest "$srcdir/$subdir/outofrange.s" "" ""
+
+    dg-finish
+
+}
diff --git a/gas/testsuite/gas/m32r/fslotx.d b/gas/testsuite/gas/m32r/fslotx.d
new file mode 100644
index 0000000000..d3e2d1a287
--- /dev/null
+++ b/gas/testsuite/gas/m32r/fslotx.d
@@ -0,0 +1,23 @@
+#as: -m32rx
+#objdump: -dr
+#name: fslotx
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0 <bcl>:
+ *0:	78 00 f0 00 	bcl 0 <bcl> \|\| nop
+ *4:	60 08 f0 00 	ldi r0,[#]*8 \|\| nop
+
+0+8 <bcl_s>:
+ *8:	78 00 f0 00 	bcl 8 <bcl_s> \|\| nop
+ *c:	60 08 f0 00 	ldi r0,[#]*8 \|\| nop
+
+0+10 <bncl>:
+  10:	79 00 f0 00 	bncl 10 <bncl> \|\| nop
+  14:	60 08 f0 00 	ldi r0,[#]*8 \|\| nop
+
+0+18 <bncl_s>:
+  18:	79 00 f0 00 	bncl 18 <bncl_s> \|\| nop
+  1c:	60 08 f0 00 	ldi r0,[#]*8 \|\| nop
diff --git a/gas/testsuite/gas/m32r/fslotx.s b/gas/testsuite/gas/m32r/fslotx.s
new file mode 100644
index 0000000000..9cfb2312cc
--- /dev/null
+++ b/gas/testsuite/gas/m32r/fslotx.s
@@ -0,0 +1,19 @@
+# Test the FILL-SLOT attribute.
+# The FILL-SLOT attribute ensures the next insn begins on a 32 byte boundary.
+# This is needed for example with bl because the subroutine will return
+# to a 32 bit boundary.
+
+	.text
+bcl:
+	bcl bcl
+	ldi r0,#8
+bcl_s:
+	bcl.s bcl_s
+	ldi r0,#8
+
+bncl:
+	bncl bncl
+	ldi r0,#8
+bncl_s:
+	bncl.s bncl_s
+	ldi r0,#8
diff --git a/gas/testsuite/gas/m32r/interfere.s b/gas/testsuite/gas/m32r/interfere.s
new file mode 100644
index 0000000000..775ecdef8b
--- /dev/null
+++ b/gas/testsuite/gas/m32r/interfere.s
@@ -0,0 +1,14 @@
+; Test error messages in instances where output operands interfere.
+
+; { dg-do assemble { target m32r-*-* } }
+; { dg-options -m32rx }
+
+interfere:
+	trap #1      || cmp  r3, r4	; { dg-error "write to the same" }
+		; { dg-warning "same" "out->in" { target *-*-* } { 7 } }
+	rte          || addx r3, r4	; { dg-error "write to the same" }
+		; { dg-warning "same" "out->in" { target *-*-* } { 9 } }
+	cmp  r1, r2  || addx r3, r4	; { dg-error "write to the same" }
+		; { dg-warning "same" "out->in" { target *-*-* } { 11 } }
+	mvtc r0, psw || addx r1, r4	; { dg-error "write to the same" }
+		; { dg-warning "same" "out->in" { target *-*-* } { 13 } }
diff --git a/gas/testsuite/gas/m32r/m32rx.d b/gas/testsuite/gas/m32r/m32rx.d
new file mode 100644
index 0000000000..6713dd20da
--- /dev/null
+++ b/gas/testsuite/gas/m32r/m32rx.d
@@ -0,0 +1,337 @@
+#as: -m32rx --no-warn-explicit-parallel-conflicts --hidden -O
+#objdump: -dr
+#name: m32rx
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <bcl>:
+   0:	78 00 f0 00 	bcl 0 <bcl> \|\| nop
+
+0+0004 <bncl>:
+   4:	79 ff f0 00 	bncl 0 <bcl> \|\| nop
+
+0+0008 <cmpz>:
+   8:	00 7d f0 00 	cmpz fp \|\| nop
+
+0+000c <cmpeq>:
+   c:	0d 6d f0 00 	cmpeq fp,fp \|\| nop
+
+0+0010 <maclh1>:
+  10:	5d cd f0 00 	maclh1 fp,fp \|\| nop
+
+0+0014 <msblo>:
+  14:	5d dd f0 00 	msblo fp,fp \|\| nop
+
+0+0018 <mulwu1>:
+  18:	5d ad f0 00 	mulwu1 fp,fp \|\| nop
+
+0+001c <macwu1>:
+  1c:	5d bd f0 00 	macwu1 fp,fp \|\| nop
+
+0+0020 <sadd>:
+  20:	50 e4 f0 00 	sadd \|\| nop
+
+0+0024 <satb>:
+  24:	8d 6d 03 00 	satb fp,fp
+
+0+0028 <mulhi>:
+  28:	3d 8d f0 00 	mulhi fp,fp,a1 \|\| nop
+
+0+002c <mullo>:
+  2c:	3d 1d f0 00 	mullo fp,fp \|\| nop
+
+0+0030 <divh>:
+  30:	9d 0d 00 10 	divh fp,fp
+
+0+0034 <machi>:
+  34:	3d cd f0 00 	machi fp,fp,a1 \|\| nop
+
+0+0038 <maclo>:
+  38:	3d 5d f0 00 	maclo fp,fp \|\| nop
+
+0+003c <mvfachi>:
+  3c:	5d f4 f0 00 	mvfachi fp,a1 \|\| nop
+
+0+0040 <mvfacmi>:
+  40:	5d f6 f0 00 	mvfacmi fp,a1 \|\| nop
+
+0+0044 <mvfaclo>:
+  44:	5d f5 f0 00 	mvfaclo fp,a1 \|\| nop
+
+0+0048 <mvtachi>:
+  48:	5d 74 f0 00 	mvtachi fp,a1 \|\| nop
+
+0+004c <mvtaclo>:
+  4c:	5d 71 f0 00 	mvtaclo fp \|\| nop
+
+0+0050 <rac>:
+  50:	54 90 f0 00 	rac a1 \|\| nop
+
+0+0054 <rac_ds>:
+  54:	54 90 f0 00 	rac a1 \|\| nop
+
+0+0058 <rac_dsi>:
+  58:	50 94 f0 00 	rac a0,a1 \|\| nop
+
+0+005c <rach>:
+  5c:	54 80 f0 00 	rach a1 \|\| nop
+
+0+0060 <rach_ds>:
+  60:	50 84 f0 00 	rach a0,a1 \|\| nop
+
+0+0064 <rach_dsi>:
+  64:	54 81 f0 00 	rach a1,a0,#0x2 \|\| nop
+
+0+0068 <bc__add>:
+  68:	7c e6 8d ad 	bc 0 <bcl> \|\| add fp,fp
+  6c:	7c e5 0d ad 	bc 0 <bcl> -> add fp,fp
+
+0+0070 <bcl__addi>:
+  70:	78 e4 cd 4d 	bcl 0 <bcl> \|\| addi fp,#77
+  74:	78 e3 cd 4d 	bcl 0 <bcl> \|\| addi fp,#77
+
+0+0078 <bl__addv>:
+  78:	7e e2 8d 8d 	bl 0 <bcl> \|\| addv fp,fp
+  7c:	7e e1 8d 8d 	bl 0 <bcl> \|\| addv fp,fp
+
+0+0080 <bnc__addx>:
+  80:	7d e0 8d 9d 	bnc 0 <bcl> \|\| addx fp,fp
+  84:	7d df 0d 9d 	bnc 0 <bcl> -> addx fp,fp
+
+0+0088 <bncl__and>:
+  88:	79 de 8d cd 	bncl 0 <bcl> \|\| and fp,fp
+  8c:	0d cd 79 dd 	and fp,fp -> bncl 0 <bcl>
+
+0+0090 <bra__cmp>:
+  90:	7f dc 8d 4d 	bra 0 <bcl> \|\| cmp fp,fp
+  94:	7f db 8d 4d 	bra 0 <bcl> \|\| cmp fp,fp
+
+0+0098 <jl__cmpeq>:
+  98:	1e cd 8d 6d 	jl fp \|\| cmpeq fp,fp
+  9c:	1e cd 8d 6d 	jl fp \|\| cmpeq fp,fp
+
+0+00a0 <jmp__cmpu>:
+  a0:	1f cd 8d 5d 	jmp fp \|\| cmpu fp,fp
+  a4:	1f cd 8d 5d 	jmp fp \|\| cmpu fp,fp
+
+0+00a8 <ld__cmpz>:
+  a8:	2d cd 80 71 	ld fp,@fp \|\| cmpz r1
+  ac:	2d cd 80 71 	ld fp,@fp \|\| cmpz r1
+
+0+00b0 <ld__ldi>:
+  b0:	2d e1 e2 4d 	ld fp,@r1\+ \|\| ldi r2,#77
+  b4:	2d e1 e2 4d 	ld fp,@r1\+ \|\| ldi r2,#77
+
+0+00b8 <ldb__mv>:
+  b8:	2d 8d 92 8d 	ldb fp,@fp \|\| mv r2,fp
+  bc:	2d 8d 12 8d 	ldb fp,@fp -> mv r2,fp
+
+0+00c0 <ldh__neg>:
+  c0:	2d ad 82 3d 	ldh fp,@fp \|\| neg r2,fp
+  c4:	2d ad 02 3d 	ldh fp,@fp -> neg r2,fp
+
+0+00c8 <ldub__nop>:
+  c8:	2d 9d f0 00 	ldub fp,@fp \|\| nop
+  cc:	2d 9d f0 00 	ldub fp,@fp \|\| nop
+
+0+00d0 <lduh__not>:
+  d0:	2d bd 82 bd 	lduh fp,@fp \|\| not r2,fp
+  d4:	2d bd 02 bd 	lduh fp,@fp -> not r2,fp
+
+0+00d8 <lock__or>:
+  d8:	2d dd 82 ed 	lock fp,@fp \|\| or r2,fp
+  dc:	2d dd 02 ed 	lock fp,@fp -> or r2,fp
+
+0+00e0 <mvfc__sub>:
+  e0:	1d 91 82 2d 	mvfc fp,cbr \|\| sub r2,fp
+  e4:	1d 91 02 2d 	mvfc fp,cbr -> sub r2,fp
+
+0+00e8 <mvtc__subv>:
+  e8:	12 ad 82 0d 	mvtc fp,spi \|\| subv r2,fp
+  ec:	12 ad 82 0d 	mvtc fp,spi \|\| subv r2,fp
+
+0+00f0 <rte__subx>:
+  f0:	10 d6 82 2d 	rte \|\| sub r2,fp
+  f4:	10 d6 02 1d 	rte -> subx r2,fp
+
+0+00f8 <sll__xor>:
+  f8:	1d 41 82 dd 	sll fp,r1 \|\| xor r2,fp
+  fc:	1d 41 02 dd 	sll fp,r1 -> xor r2,fp
+
+0+0100 <slli__machi>:
+ 100:	5d 56 b2 4d 	slli fp,#0x16 \|\| machi r2,fp
+ 104:	5d 56 32 4d 	slli fp,#0x16 -> machi r2,fp
+
+0+0108 <sra__maclh1>:
+ 108:	1d 2d d2 cd 	sra fp,fp \|\| maclh1 r2,fp
+ 10c:	1d 2d 52 cd 	sra fp,fp -> maclh1 r2,fp
+
+0+0110 <srai__maclo>:
+ 110:	5d 36 b2 5d 	srai fp,#0x16 \|\| maclo r2,fp
+ 114:	5d 36 32 5d 	srai fp,#0x16 -> maclo r2,fp
+
+0+0118 <srl__macwhi>:
+ 118:	1d 0d b2 6d 	srl fp,fp \|\| macwhi r2,fp
+ 11c:	1d 0d 32 6d 	srl fp,fp -> macwhi r2,fp
+
+0+0120 <srli__macwlo>:
+ 120:	5d 16 b2 7d 	srli fp,#0x16 \|\| macwlo r2,fp
+ 124:	5d 16 32 7d 	srli fp,#0x16 -> macwlo r2,fp
+
+0+0128 <st__macwu1>:
+ 128:	2d 4d d2 bd 	st fp,@fp \|\| macwu1 r2,fp
+ 12c:	2d 4d d2 bd 	st fp,@fp \|\| macwu1 r2,fp
+
+0+0130 <st__msblo>:
+ 130:	2d 6d d2 dd 	st fp,@\+fp \|\| msblo r2,fp
+ 134:	2d 6d 52 dd 	st fp,@\+fp -> msblo r2,fp
+
+0+0138 <st__mul>:
+ 138:	2d 7d 92 6d 	st fp,@-fp \|\| mul r2,fp
+ 13c:	2d 7d 12 6d 	st fp,@-fp -> mul r2,fp
+
+0+0140 <stb__mulhi>:
+ 140:	2d 0d b2 0d 	stb fp,@fp \|\| mulhi r2,fp
+ 144:	2d 0d b2 0d 	stb fp,@fp \|\| mulhi r2,fp
+
+0+0148 <sth__mullo>:
+ 148:	2d 2d b2 1d 	sth fp,@fp \|\| mullo r2,fp
+ 14c:	2d 2d b2 1d 	sth fp,@fp \|\| mullo r2,fp
+
+0+0150 <trap__mulwhi>:
+ 150:	10 f2 b2 2d 	trap #0x2 \|\| mulwhi r2,fp
+ 154:	10 f2 f0 00 	trap #0x2 \|\| nop
+ 158:	32 2d f0 00 	mulwhi r2,fp \|\| nop
+
+0+015c <unlock__mulwlo>:
+ 15c:	2d 5d b2 3d 	unlock fp,@fp \|\| mulwlo r2,fp
+ 160:	2d 5d b2 3d 	unlock fp,@fp \|\| mulwlo r2,fp
+
+0+0164 <add__mulwu1>:
+ 164:	0d ad d2 ad 	add fp,fp \|\| mulwu1 r2,fp
+ 168:	0d ad 52 ad 	add fp,fp -> mulwu1 r2,fp
+
+0+016c <addi__mvfachi>:
+ 16c:	4d 4d d2 f0 	addi fp,#77 \|\| mvfachi r2
+ 170:	4d 4d d2 f0 	addi fp,#77 \|\| mvfachi r2
+
+0+0174 <addv__mvfaclo>:
+ 174:	0d 8d d2 f5 	addv fp,fp \|\| mvfaclo r2,a1
+ 178:	0d 8d d2 f5 	addv fp,fp \|\| mvfaclo r2,a1
+
+0+017c <addx__mvfacmi>:
+ 17c:	0d 9d d2 f2 	addx fp,fp \|\| mvfacmi r2
+ 180:	0d 9d d2 f2 	addx fp,fp \|\| mvfacmi r2
+
+0+0184 <and__mvtachi>:
+ 184:	0d cd d2 70 	and fp,fp \|\| mvtachi r2
+ 188:	0d cd d2 70 	and fp,fp \|\| mvtachi r2
+
+0+018c <cmp__mvtaclo>:
+ 18c:	0d 4d d2 71 	cmp fp,fp \|\| mvtaclo r2
+ 190:	0d 4d d2 71 	cmp fp,fp \|\| mvtaclo r2
+
+0+0194 <cmpeq__rac>:
+ 194:	0d 6d d4 90 	cmpeq fp,fp \|\| rac a1
+ 198:	0d 6d d4 90 	cmpeq fp,fp \|\| rac a1
+
+0+019c <cmpu__rach>:
+ 19c:	0d 5d d0 84 	cmpu fp,fp \|\| rach a0,a1
+ 1a0:	0d 5d d4 84 	cmpu fp,fp \|\| rach a1,a1
+
+0+01a4 <cmpz__sadd>:
+ 1a4:	00 7d d0 e4 	cmpz fp \|\| sadd
+ 1a8:	00 7d d0 e4 	cmpz fp \|\| sadd
+
+0+01ac <sc>:
+ 1ac:	74 01 d0 e4 	sc \|\| sadd
+
+0+01b0 <snc>:
+ 1b0:	75 01 d0 e4 	snc \|\| sadd
+
+0+01b4 <jc>:
+ 1b4:	1c cd f0 00 	jc fp \|\| nop
+
+0+01b8 <jnc>:
+ 1b8:	1d cd f0 00 	jnc fp \|\| nop
+
+0+01bc <pcmpbz>:
+ 1bc:	03 7d f0 00 	pcmpbz fp \|\| nop
+
+0+01c0 <sat>:
+ 1c0:	8d 6d 00 00 	sat fp,fp
+
+0+01c4 <sath>:
+ 1c4:	8d 6d 02 00 	sath fp,fp
+
+0+01c8 <jc__pcmpbz>:
+ 1c8:	1c cd 83 7d 	jc fp \|\| pcmpbz fp
+ 1cc:	1c cd 03 7d 	jc fp -> pcmpbz fp
+
+0+01d0 <jnc__ldi>:
+ 1d0:	1d cd ed 4d 	jnc fp \|\| ldi fp,#77
+ 1d4:	1d cd 6d 4d 	jnc fp -> ldi fp,#77
+
+0+01d8 <sc__mv>:
+ 1d8:	74 01 9d 82 	sc \|\| mv fp,r2
+ 1dc:	74 01 9d 82 	sc \|\| mv fp,r2
+
+0+01e0 <snc__neg>:
+ 1e0:	75 01 8d 32 	snc \|\| neg fp,r2
+ 1e4:	75 01 8d 32 	snc \|\| neg fp,r2
+
+0+01e8 <nop__sadd>:
+ 1e8:	70 00 d0 e4 	nop \|\| sadd
+
+0+01ec <sadd__nop>:
+ 1ec:	70 00 d0 e4 	nop \|\| sadd
+
+0+01f0 <sadd__nop_reverse>:
+ 1f0:	70 00 d0 e4 	nop \|\| sadd
+
+0+01f4 <add__not>:
+ 1f4:	00 a1 83 b5 	add r0,r1 \|\| not r3,r5
+
+0+01f8 <add__not_dest_clash>:
+ 1f8:	03 a4 03 b5 	add r3,r4 -> not r3,r5
+
+0+01fc <add__not__src_clash>:
+ 1fc:	03 a4 05 b3 	add r3,r4 -> not r5,r3
+
+0+0200 <add__not__no_clash>:
+ 200:	03 a4 84 b5 	add r3,r4 \|\| not r4,r5
+
+0+0204 <mul__sra>:
+ 204:	13 24 91 62 	sra r3,r4 \|\| mul r1,r2
+
+0+0208 <mul__sra__reverse_src_clash>:
+ 208:	13 24 91 63 	sra r3,r4 \|\| mul r1,r3
+
+0+020c <bc__add_>:
+ 20c:	7c 04 01 a2 	bc 21c <label> -> add r1,r2
+
+0+0210 <add__bc>:
+ 210:	7c 03 83 a4 	bc 21c <label> \|\| add r3,r4
+
+0+0214 <bc__add__forced_parallel>:
+ 214:	7c 02 85 a6 	bc 21c <label> \|\| add r5,r6
+
+0+0218 <add__bc__forced_parallel>:
+ 218:	7c 01 87 a8 	bc 21c <label> \|\| add r7,r8
+
+0+021c <label>:
+ 21c:	70 00 f0 00 	nop \|\| nop
+
+0+0220 <mulwhi>:
+ 220:	3d 2d 3d ad 	mulwhi fp,fp -> mulwhi fp,fp,a1
+
+0+0224 <mulwlo>:
+ 224:	3d 3d 3d bd 	mulwlo fp,fp -> mulwlo fp,fp,a1
+
+0+0228 <macwhi>:
+ 228:	3d 6d 3d ed 	macwhi fp,fp -> macwhi fp,fp,a1
+
+0+022c <macwlo>:
+ 22c:	3d 7d 3d fd 	macwlo fp,fp -> macwlo fp,fp,a1
diff --git a/gas/testsuite/gas/m32r/m32rx.exp b/gas/testsuite/gas/m32r/m32rx.exp
new file mode 100644
index 0000000000..6dd33ded87
--- /dev/null
+++ b/gas/testsuite/gas/m32r/m32rx.exp
@@ -0,0 +1,7 @@
+# M32Rx assembler testsuite.
+
+if [istarget m32r*-*-*] {
+    run_dump_test "m32rx"
+    run_dump_test "fslotx"
+    run_dump_test "relax-2"
+}
diff --git a/gas/testsuite/gas/m32r/m32rx.s b/gas/testsuite/gas/m32r/m32rx.s
new file mode 100644
index 0000000000..b86dab0bcc
--- /dev/null
+++ b/gas/testsuite/gas/m32r/m32rx.s
@@ -0,0 +1,590 @@
+# Test new instructions
+branchpoint:
+	
+	.text
+	.global bcl
+bcl:
+	bcl branchpoint
+
+	.text
+	.global bncl
+bncl:
+	bncl branchpoint
+
+	.text
+	.global cmpz
+cmpz:
+	cmpz fp
+
+	.text
+	.global cmpeq
+cmpeq:
+	cmpeq fp, fp
+
+	.text
+	.global maclh1
+maclh1:
+	maclh1 fp, fp
+	
+	.text
+	.global macsl0
+msblo:
+	msblo fp, fp
+	
+	.text
+	.global mulwu1
+mulwu1:
+	mulwu1 fp, fp
+	
+	.text
+	.global macwu1
+macwu1:
+	macwu1 fp, fp
+	
+	.text
+	.global sadd
+sadd:
+	sadd
+	
+	.text
+	.global satb
+satb:
+	satb fp, fp
+
+	
+	.text
+	.global mulhi
+mulhi:
+	mulhi fp, fp, a1
+	
+	.text
+	.global mullo
+mullo:
+	mullo fp, fp, a0
+	
+	.text
+	.global divh
+divh:
+	divh fp, fp
+	
+	.text
+	.global machi
+machi:
+	machi fp, fp, a1
+	
+	.text
+	.global maclo
+maclo:
+	maclo fp, fp, a0
+	
+	.text
+	.global mvfachi
+mvfachi:
+	mvfachi fp, a1
+	
+	.text
+	.global mvfacmi
+mvfacmi:
+	mvfacmi fp, a1
+	
+	.text
+	.global mvfaclo
+mvfaclo:
+	mvfaclo fp, a1
+	
+	.text
+	.global mvtachi
+mvtachi:
+	mvtachi fp, a1
+	
+	.text
+	.global mvtaclo
+mvtaclo:
+	mvtaclo fp, a0
+	
+	.text
+	.global rac
+rac:
+	rac a1
+	
+	.text
+	.global rac_ds
+rac_ds:
+	rac a1, a0
+	
+	.text
+	.global rac_dsi
+rac_dsi:
+	rac a0, a1, #1
+	
+	.text
+	.global rach
+rach:
+	rach a1
+	
+	.text
+	.global rach_ds
+rach_ds:
+	rach a0, a1
+	
+	.text
+	.global rach_dsi
+rach_dsi:
+	rach a1, a0, #2
+	
+# Test explicitly parallel and implicitly parallel instructions
+# Including apparent instruction sequence reordering.
+	.text
+	.global bc__add
+bc__add:
+	bc bcl || add fp, fp
+# Use bc.s here as bc is relaxable and thus a nop will be emitted.
+	bc.s bcl
+	add fp, fp
+
+	.text
+	.global bcl__addi
+bcl__addi:	
+	bcl bcl || addi fp, #77
+	addi fp, #77
+# Use bcl.s here as bcl is relaxable and thus the parallelization won't happen.
+	bcl.s bcl
+
+	.text
+	.global bl__addv
+bl__addv:
+	bl bcl || addv fp, fp
+	addv fp, fp
+# Use bl.s here as bl is relaxable and thus the parallelization won't happen.
+	bl.s bcl
+	
+	.text
+	.global bnc__addx
+bnc__addx:
+	bnc bcl || addx fp, fp
+# Use bnc.s here as bnc is relaxable and thus the parallelization attempt won't
+# happen.  Things still won't be parallelized, but we want this test to try.
+	bnc.s bcl
+	addx fp, fp
+
+	.text
+	.global bncl__and
+bncl__and:
+	bncl bcl || and fp, fp
+	and fp, fp
+	bncl bcl
+
+	.text
+	.global bra__cmp
+bra__cmp:
+	bra bcl || cmp fp, fp
+	cmp fp, fp
+# Use bra.s here as bra is relaxable and thus the parallelization won't happen.
+	bra.s bcl
+	
+	.text
+	.global jl__cmpeq
+jl__cmpeq:
+	jl fp || cmpeq fp, fp
+	cmpeq fp, fp
+	jl fp
+	
+	.text
+	.global jmp__cmpu
+jmp__cmpu:
+	jmp fp || cmpu fp, fp
+	cmpu fp, fp
+	jmp fp
+	
+	.text
+	.global ld__cmpz
+ld__cmpz:
+	ld fp, @fp || cmpz r1
+	cmpz r1
+	ld fp, @fp 
+	
+	.text
+	.global ld__ldi
+ld__ldi:
+	ld fp, @r1+ || ldi r2, #77
+	ld fp, @r1+ 
+	ldi r2, #77
+	
+	.text
+	.global ldb__mv
+ldb__mv:
+	ldb fp, @fp || mv r2, fp
+	ldb fp, @fp 
+	mv r2, fp
+
+	.text
+	.global ldh__neg
+ldh__neg:
+	ldh fp, @fp || neg r2, fp
+	ldh fp, @fp
+	neg r2, fp
+
+	.text
+	.global ldub__nop
+ldub__nop:
+	ldub fp, @fp || nop
+	ldub fp, @fp 
+	nop
+
+	.text
+	.global lduh__not
+lduh__not:
+	lduh fp, @fp || not r2, fp
+	lduh fp, @fp
+	not r2, fp
+
+	.text
+	.global lock__or
+lock__or:
+	lock fp, @fp || or r2, fp
+	lock fp, @fp
+	or r2, fp
+
+	.text
+	.global mvfc__sub
+mvfc__sub:
+	mvfc fp, cr1 || sub r2, fp
+	mvfc fp, cr1
+	sub r2, fp
+
+	.text
+	.global mvtc__subv
+mvtc__subv:
+	mvtc fp, cr2 || subv r2, fp
+	mvtc fp, cr2
+	subv r2, fp
+
+	.text
+	.global rte__subx
+rte__subx:
+	rte || sub r2, fp
+	rte
+	subx r2, fp
+
+	.text
+	.global sll__xor
+sll__xor:
+	sll fp, r1 || xor r2, fp
+	sll fp, r1
+	xor r2, fp
+
+	.text
+	.global slli__machi
+slli__machi:
+	slli fp, #22 || machi r2, fp
+	slli fp, #22
+	machi r2, fp
+
+	.text
+	.global sra__maclh1
+sra__maclh1:
+	sra fp, fp || maclh1 r2, fp
+	sra fp, fp
+	maclh1 r2, fp
+
+	.text
+	.global srai__maclo
+srai__maclo:
+	srai fp, #22 || maclo r2, fp
+	srai fp, #22
+	maclo r2, fp
+
+	.text
+	.global srl__macwhi
+srl__macwhi:
+	srl fp, fp || macwhi r2, fp
+	srl fp, fp
+	macwhi r2, fp
+
+	.text
+	.global srli__macwlo
+srli__macwlo:
+	srli fp, #22 || macwlo r2, fp
+	srli fp, #22
+	macwlo r2, fp
+	
+	.text
+	.global st__macwu1
+st__macwu1:
+	st fp, @fp || macwu1 r2, fp
+	st fp, @fp
+	macwu1 r2, fp
+
+	.text
+	.global st__msblo
+st__msblo:
+	st fp, @+fp || msblo r2, fp
+	st fp, @+fp 
+	msblo r2, fp
+
+	.text
+	.global st__mul
+st__mul:
+	st fp, @-fp || mul r2, fp
+	st fp, @-fp
+	mul r2, fp
+
+	.text
+	.global stb__mulhi
+stb__mulhi:
+	stb fp, @fp || mulhi r2, fp
+	stb fp, @fp
+	mulhi r2, fp
+	
+	.text
+	.global sth__mullo
+sth__mullo:
+	sth fp, @fp || mullo r2, fp
+	sth fp, @fp 
+	mullo r2, fp
+
+	.text
+	.global trap__mulwhi
+trap__mulwhi:
+	trap #2 || mulwhi r2, fp
+	trap #2
+	mulwhi r2, fp
+
+	.text
+	.global unlock__mulwlo
+unlock__mulwlo:
+	unlock fp, @fp || mulwlo r2, fp
+	unlock fp, @fp
+	mulwlo r2, fp
+
+	.text
+	.global add__mulwu1
+add__mulwu1:
+	add fp, fp || mulwu1 r2, fp
+	add fp, fp
+	mulwu1 r2, fp
+
+	.text
+	.global addi__mvfachi
+addi__mvfachi:
+	addi fp, #77 || mvfachi r2, a0
+	addi fp, #77
+	mvfachi r2, a0
+
+	.text
+	.global addv__mvfaclo
+addv__mvfaclo:
+	addv fp, fp || mvfaclo r2, a1
+	addv fp, fp
+	mvfaclo r2, a1
+
+	.text
+	.global addx__mvfacmi
+addx__mvfacmi:
+	addx fp, fp || mvfacmi r2, a0
+	addx fp, fp
+	mvfacmi r2, a0
+
+	.text
+	.global and__mvtachi
+and__mvtachi:
+	and fp, fp || mvtachi r2, a0
+	and fp, fp
+	mvtachi r2, a0
+	
+	.text
+	.global cmp__mvtaclo
+cmp__mvtaclo:
+	cmp fp, fp || mvtaclo r2, a0
+	cmp fp, fp
+	mvtaclo r2, a0
+
+	.text
+	.global cmpeq__rac
+cmpeq__rac:
+	cmpeq fp, fp || rac a1
+	cmpeq fp, fp
+	rac a1
+
+	.text
+	.global cmpu__rach
+cmpu__rach:
+	cmpu fp, fp || rach a0, a1
+	cmpu fp, fp
+	rach a1, a1, #1
+
+	.text
+	.global cmpz__sadd
+cmpz__sadd:
+	cmpz fp || sadd
+	cmpz fp
+	sadd
+
+
+	
+# Test private instructions	
+	.text
+	.global sc
+sc:
+	sc
+	sadd
+	
+	.text
+	.global snc
+snc:
+	snc
+	sadd 
+	
+	.text
+	.global jc
+jc:
+	jc fp
+	
+	.text
+	.global jnc
+jnc:
+	jnc fp
+		
+	.text
+	.global pcmpbz
+pcmpbz:
+	pcmpbz fp
+	
+	.text
+	.global sat
+sat:
+	sat fp, fp
+	
+	.text
+	.global sath
+sath:
+	sath fp, fp 
+
+
+# Test parallel versions of the private instructions
+	
+	.text
+	.global jc__pcmpbz
+jc__pcmpbz:
+	jc fp || pcmpbz fp
+	jc fp 
+	pcmpbz fp
+	
+	.text
+	.global jnc__ldi
+jnc__ldi:
+	jnc fp || ldi fp, #77
+	jnc fp
+	ldi fp, #77
+	
+	.text
+	.global sc__mv
+sc__mv:
+	sc || mv fp, r2
+	sc 
+	mv fp, r2
+
+	.text
+	.global snc__neg
+snc__neg:
+	snc || neg fp, r2
+	snc 
+	neg fp, r2
+	
+# Test automatic and explicit parallelisation of instructions
+	.text
+	.global nop__sadd
+nop__sadd:
+	nop
+	sadd
+
+	.text
+	.global sadd__nop
+sadd__nop:
+	sadd
+	nop
+
+	.text
+	.global sadd__nop_reverse
+sadd__nop_reverse:
+	sadd || nop
+
+	.text
+	.global add__not
+add__not:
+	add  r0, r1
+	not  r3, r5
+
+	.text
+	.global add__not__dest_clash
+add__not_dest_clash:
+	add  r3, r4
+	not  r3, r5
+
+	.text
+	.global add__not__src_clash
+add__not__src_clash:
+	add  r3, r4
+	not  r5, r3
+
+	.text
+	.global add__not__no_clash
+add__not__no_clash:
+	add  r3, r4
+	not  r4, r5
+
+	.text
+	.global mul__sra
+mul__sra:
+	mul  r1, r2
+	sra  r3, r4
+	
+	.text
+	.global mul__sra__reverse_src_clash
+mul__sra__reverse_src_clash:
+	mul  r1, r3
+	sra  r3, r4
+	
+	.text
+	.global bc__add_
+bc__add_:
+	bc.s label
+	add r1, r2
+
+	.text
+	.global add__bc
+add__bc:
+	add r3, r4
+	bc.s  label
+
+	.text
+	.global bc__add__forced_parallel
+bc__add__forced_parallel:
+	bc label || add r5, r6
+
+	.text
+	.global add__bc__forced_parallel
+add__bc__forced_parallel:
+	add r7, r8 || bc label
+label:
+	nop
+
+; Additional testcases.
+; These insns were added to the chip later.
+
+	.text
+mulwhi:
+	mulwhi fp, fp, a0
+	mulwhi fp, fp, a1
+	
+mulwlo:
+	mulwlo fp, fp, a0
+	mulwlo fp, fp, a1
+
+macwhi:
+	macwhi fp, fp, a0
+	macwhi fp, fp, a1
+
+macwlo:
+	macwlo fp, fp, a0
+	macwlo fp, fp, a1
diff --git a/gas/testsuite/gas/m32r/relax-2.d b/gas/testsuite/gas/m32r/relax-2.d
new file mode 100644
index 0000000000..2f83e8b345
--- /dev/null
+++ b/gas/testsuite/gas/m32r/relax-2.d
@@ -0,0 +1,18 @@
+#as: --m32rx
+#objdump: -dr
+#name: relax-2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0 <label1>:
+   0:	fd 00 00 83 	bnc 20c <label3>
+   4:	70 00 f0 00 	nop \|\| nop
+   8:	43 03 c2 02 	addi r3,[#]3 \|\| addi r2,[#]2
+
+0+0c <label2>:
+	...
+
+0+020c <label3>:
+ 20c:	70 00 f0 00 	nop \|\| nop
diff --git a/gas/testsuite/gas/m32r/relax-2.s b/gas/testsuite/gas/m32r/relax-2.s
new file mode 100644
index 0000000000..179dec7935
--- /dev/null
+++ b/gas/testsuite/gas/m32r/relax-2.s
@@ -0,0 +1,11 @@
+; Test whether parallel insns get inappropriately moved during relaxation.
+
+        .text
+label1:
+        bnc     label3
+        nop
+        addi    r3, #3 || addi  r2, #2
+label2:
+        .space 512
+label3:
+        nop
diff --git a/gas/testsuite/gas/m32r/wrongsize.s b/gas/testsuite/gas/m32r/wrongsize.s
new file mode 100644
index 0000000000..088f478943
--- /dev/null
+++ b/gas/testsuite/gas/m32r/wrongsize.s
@@ -0,0 +1,10 @@
+; Test error messages in instances where an insn of a particular size
+; is required.
+
+; { dg-do assemble { target m32r-*-* } }
+
+wrongsize:
+	cmpi r8,#10 -> ldi r0,#8  ; { dg-error "not a 16 bit instruction" }
+	ldi r0,#8 -> cmpi r8,#10  ; { dg-error "not a 16 bit instruction" }
+	cmpi r8,#10 || ldi r0,#8  ; { dg-error "not a 16 bit instruction" }
+	ldi r0,#8 || cmpi r8,#10  ; { dg-error "not a 16 bit instruction" }