Combine aarch64_decode_stp_offset_wb and aarch64_decode_stp_offset
This patch combines both aarch64_decode_stp_offset_wb and aarch64_decode_stp_offset together. gdb: 2015-11-05 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_decode_stp_offset): New argument wback. (aarch64_decode_stp_offset_wb): Removed. (aarch64_analyze_prologue): Don't use aarch64_decode_stp_offset_wb.
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@ -1,3 +1,11 @@
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2015-11-05 Yao Qi <yao.qi@linaro.org>
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* aarch64-tdep.c (aarch64_decode_stp_offset): New argument
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wback.
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(aarch64_decode_stp_offset_wb): Removed.
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(aarch64_analyze_prologue): Don't use
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aarch64_decode_stp_offset_wb.
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2015-11-04 Marcin Kościelnicki <koriakin@0x04.net>
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2015-11-04 Marcin Kościelnicki <koriakin@0x04.net>
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PR/18376
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PR/18376
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@ -416,42 +416,9 @@ aarch64_decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
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return 0;
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return 0;
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}
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}
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/* Decode an opcode if it represents the following instruction:
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/* Decode an opcode if it represents the following instructions:
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STP rt, rt2, [rn, #imm]
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STP rt, rt2, [rn, #imm]
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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RT1 receives the 'rt' field from the decoded instruction.
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RT2 receives the 'rt2' field from the decoded instruction.
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RN receives the 'rn' field from the decoded instruction.
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IMM receives the 'imm' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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static int
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aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
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unsigned *rt2, unsigned *rn, int32_t *imm)
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{
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if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
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{
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*rt1 = (insn >> 0) & 0x1f;
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*rn = (insn >> 5) & 0x1f;
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*rt2 = (insn >> 10) & 0x1f;
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*imm = extract_signed_bitfield (insn, 7, 15);
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*imm <<= 3;
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if (aarch64_debug)
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{
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debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
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core_addr_to_string_nz (addr), insn, *rt1, *rt2,
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*rn, *imm);
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}
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return 1;
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}
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return 0;
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}
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/* Decode an opcode if it represents the following instruction:
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STP rt, rt2, [rn, #imm]!
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STP rt, rt2, [rn, #imm]!
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ADDR specifies the address of the opcode.
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ADDR specifies the address of the opcode.
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@ -460,26 +427,29 @@ aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
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RT2 receives the 'rt2' field from the decoded instruction.
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RT2 receives the 'rt2' field from the decoded instruction.
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RN receives the 'rn' field from the decoded instruction.
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RN receives the 'rn' field from the decoded instruction.
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IMM receives the 'imm' field from the decoded instruction.
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IMM receives the 'imm' field from the decoded instruction.
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*WBACK receives the bit 23 from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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static int
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static int
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aarch64_decode_stp_offset_wb (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
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aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
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unsigned *rt2, unsigned *rn, int32_t *imm)
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unsigned *rt2, unsigned *rn, int32_t *imm,
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int *wback)
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{
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{
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if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
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if (decode_masked_match (insn, 0xff400000, 0xa9000000))
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{
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{
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*rt1 = (insn >> 0) & 0x1f;
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*rt1 = (insn >> 0) & 0x1f;
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*rn = (insn >> 5) & 0x1f;
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*rn = (insn >> 5) & 0x1f;
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*rt2 = (insn >> 10) & 0x1f;
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*rt2 = (insn >> 10) & 0x1f;
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*imm = extract_signed_bitfield (insn, 7, 15);
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*imm = extract_signed_bitfield (insn, 7, 15);
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*imm <<= 3;
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*imm <<= 3;
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*wback = bit (insn, 23);
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if (aarch64_debug)
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if (aarch64_debug)
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{
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{
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debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
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debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]%s\n",
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core_addr_to_string_nz (addr), insn, *rt1, *rt2,
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core_addr_to_string_nz (addr), insn, *rt1, *rt2,
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*rn, *imm);
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*rn, *imm, *wback ? "" : "!");
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}
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}
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return 1;
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return 1;
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}
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}
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@ -550,6 +520,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
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unsigned rt1;
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unsigned rt1;
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unsigned rt2;
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unsigned rt2;
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int op_is_sub;
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int op_is_sub;
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int wback;
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int32_t imm;
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int32_t imm;
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unsigned cond;
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unsigned cond;
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int is64;
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int is64;
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@ -622,7 +593,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
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is64 ? 8 : 4, regs[rt]);
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is64 ? 8 : 4, regs[rt]);
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}
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}
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else if (aarch64_decode_stp_offset (start, insn, &rt1, &rt2, &rn,
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else if (aarch64_decode_stp_offset (start, insn, &rt1, &rt2, &rn,
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&imm))
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&imm, &wback))
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{
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{
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/* If recording this store would invalidate the store area
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/* If recording this store would invalidate the store area
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(perhaps because rn is not known) then we should abandon
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(perhaps because rn is not known) then we should abandon
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@ -639,26 +610,10 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
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regs[rt1]);
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regs[rt1]);
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pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
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pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
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regs[rt2]);
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regs[rt2]);
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}
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else if (aarch64_decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn,
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&imm))
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{
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/* If recording this store would invalidate the store area
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(perhaps because rn is not known) then we should abandon
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further prologue analysis. */
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if (pv_area_store_would_trash (stack,
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pv_add_constant (regs[rn], imm)))
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break;
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if (pv_area_store_would_trash (stack,
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if (wback)
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pv_add_constant (regs[rn], imm + 8)))
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regs[rn] = pv_add_constant (regs[rn], imm);
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break;
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pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
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regs[rt1]);
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pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
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regs[rt2]);
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regs[rn] = pv_add_constant (regs[rn], imm);
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}
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}
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else if (aarch64_decode_tb (start, insn, &is_tbnz, &bit, &rn,
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else if (aarch64_decode_tb (start, insn, &is_tbnz, &bit, &rn,
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&offset))
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&offset))
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