PRU GAS Port
* NEWS: Mention new PRU target. * Makefile.am: Add PRU target. * config/obj-elf.c: Ditto. * configure.tgt: Ditto. * config/tc-pru.c: New file. * config/tc-pru.h: New file. * doc/Makefile.am: Add documentation for PRU GAS port. * doc/all.texi, Ditto. * doc/as.texinfo: Ditto. * doc/c-pru.texi: Document PRU GAS options. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/pru/alu.d: New file for PRU GAS testsuite. * testsuite/gas/pru/alu.s: Ditto. * testsuite/gas/pru/branch.d: Ditto. * testsuite/gas/pru/branch.s: Ditto. * testsuite/gas/pru/illegal.l: Ditto. * testsuite/gas/pru/illegal.s: Ditto. * testsuite/gas/pru/ldi.d: Ditto. * testsuite/gas/pru/ldi.s: Ditto. * testsuite/gas/pru/ldst.d: Ditto. * testsuite/gas/pru/ldst.s: Ditto. * testsuite/gas/pru/loop.d: Ditto. * testsuite/gas/pru/loop.s: Ditto. * testsuite/gas/pru/misc.d: Ditto. * testsuite/gas/pru/misc.s: Ditto. * testsuite/gas/pru/pru.exp: Ditto. * testsuite/gas/pru/pseudo.d: Ditto. * testsuite/gas/pru/pseudo.s: Ditto. * testsuite/gas/pru/warn_reglabel.l: Ditto. * testsuite/gas/pru/warn_reglabel.s: Ditto. * testsuite/gas/pru/xfr.d: Ditto. * testsuite/gas/pru/xfr.s: Ditto. * testsuite/gas/lns/lns.exp: Mark lns-common-1-alt variant for PRU. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
This commit is contained in:
Dimitar Dimitrov
Alan Modra
parent
2b100bb5cf
commit
93f11b16ec
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@ -1,3 +1,41 @@
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2016-12-31 Dimitar Dimitrov <dimitar@dinux.eu>
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* NEWS: Mention new PRU target.
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* Makefile.am: Add PRU target.
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* config/obj-elf.c: Ditto.
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* configure.tgt: Ditto.
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* config/tc-pru.c: New file.
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* config/tc-pru.h: New file.
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* doc/Makefile.am: Add documentation for PRU GAS port.
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* doc/all.texi, Ditto.
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* doc/as.texinfo: Ditto.
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* doc/c-pru.texi: Document PRU GAS options.
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* Makefile.in: Regenerate.
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* doc/Makefile.in: Regenerate.
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* po/POTFILES.in: Regenerate.
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* testsuite/gas/pru/alu.d: New file for PRU GAS testsuite.
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* testsuite/gas/pru/alu.s: Ditto.
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* testsuite/gas/pru/branch.d: Ditto.
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* testsuite/gas/pru/branch.s: Ditto.
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* testsuite/gas/pru/illegal.l: Ditto.
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* testsuite/gas/pru/illegal.s: Ditto.
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* testsuite/gas/pru/ldi.d: Ditto.
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* testsuite/gas/pru/ldi.s: Ditto.
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* testsuite/gas/pru/ldst.d: Ditto.
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* testsuite/gas/pru/ldst.s: Ditto.
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* testsuite/gas/pru/loop.d: Ditto.
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* testsuite/gas/pru/loop.s: Ditto.
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* testsuite/gas/pru/misc.d: Ditto.
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* testsuite/gas/pru/misc.s: Ditto.
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* testsuite/gas/pru/pru.exp: Ditto.
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* testsuite/gas/pru/pseudo.d: Ditto.
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* testsuite/gas/pru/pseudo.s: Ditto.
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* testsuite/gas/pru/warn_reglabel.l: Ditto.
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* testsuite/gas/pru/warn_reglabel.s: Ditto.
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* testsuite/gas/pru/xfr.d: Ditto.
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* testsuite/gas/pru/xfr.s: Ditto.
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* testsuite/gas/lns/lns.exp: Mark lns-common-1-alt variant for PRU.
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2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips16-asmacro.d: New test.
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@ -177,6 +177,7 @@ TARGET_CPU_CFILES = \
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config/tc-pdp11.c \
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config/tc-pj.c \
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config/tc-ppc.c \
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config/tc-pru.c \
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config/tc-riscv.c \
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config/tc-rl78.c \
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config/tc-rx.c \
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@ -251,6 +252,7 @@ TARGET_CPU_HFILES = \
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config/tc-pdp11.h \
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config/tc-pj.h \
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config/tc-ppc.h \
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config/tc-pru.h \
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config/tc-riscv.h \
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config/tc-rl78.h \
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config/tc-rx.h \
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@ -473,6 +473,7 @@ TARGET_CPU_CFILES = \
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config/tc-pdp11.c \
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config/tc-pj.c \
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config/tc-ppc.c \
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config/tc-pru.c \
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config/tc-riscv.c \
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config/tc-rl78.c \
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config/tc-rx.c \
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@ -547,6 +548,7 @@ TARGET_CPU_HFILES = \
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config/tc-pdp11.h \
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config/tc-pj.h \
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config/tc-ppc.h \
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config/tc-pru.h \
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config/tc-riscv.h \
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config/tc-rl78.h \
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config/tc-rx.h \
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@ -906,6 +908,7 @@ distclean-compile:
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pru.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@
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@ -1627,6 +1630,20 @@ tc-ppc.obj: config/tc-ppc.c
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi`
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tc-pru.o: config/tc-pru.c
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@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-pru.o -MD -MP -MF $(DEPDIR)/tc-pru.Tpo -c -o tc-pru.o `test -f 'config/tc-pru.c' || echo '$(srcdir)/'`config/tc-pru.c
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@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-pru.Tpo $(DEPDIR)/tc-pru.Po
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-pru.c' object='tc-pru.o' libtool=no @AMDEPBACKSLASH@
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-pru.o `test -f 'config/tc-pru.c' || echo '$(srcdir)/'`config/tc-pru.c
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tc-pru.obj: config/tc-pru.c
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@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-pru.obj -MD -MP -MF $(DEPDIR)/tc-pru.Tpo -c -o tc-pru.obj `if test -f 'config/tc-pru.c'; then $(CYGPATH_W) 'config/tc-pru.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-pru.c'; fi`
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@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-pru.Tpo $(DEPDIR)/tc-pru.Po
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-pru.c' object='tc-pru.obj' libtool=no @AMDEPBACKSLASH@
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-pru.obj `if test -f 'config/tc-pru.c'; then $(CYGPATH_W) 'config/tc-pru.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-pru.c'; fi`
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tc-riscv.o: config/tc-riscv.c
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@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
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@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
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2
gas/NEWS
2
gas/NEWS
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@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for the Texas Instruments PRU processor.
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Changes in 2.28:
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* Add support for the RISC-V architecture.
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@ -64,6 +64,10 @@
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#include "elf/nios2.h"
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#endif
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#ifdef TC_PRU
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#include "elf/pru.h"
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#endif
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static void obj_elf_line (int);
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static void obj_elf_size (int);
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static void obj_elf_type (int);
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,154 @@
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/* Definitions for TI PRU assembler.
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Copyright (C) 2014-2016 Free Software Foundation, Inc.
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#ifndef __TC_PRU__
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#define __TC_PRU__
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#define TARGET_BYTES_BIG_ENDIAN 0
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/* Words are big enough to hold addresses. */
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#define WORKING_DOT_WORD 1
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extern const char *pru_target_format (void);
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#define TARGET_FORMAT pru_target_format ()
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#define TARGET_ARCH bfd_arch_pru
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/* A PRU instruction consists of tokens and separator characters
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the tokens are things like the instruction name (add, or jmp etc),
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the register indices ($5, $7 etc), and constant expressions. The
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separator characters are commas, brackets and space.
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The instruction name is always separated from other tokens by a space
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The maximum number of tokens in an instruction is 6 (the instruction name,
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4 arguments, and a 4th string representing the expected instruction opcode
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after assembly. The latter is only used when the assemble is running in
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self test mode, otherwise its presence will generate an error. */
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#define PRU_MAX_INSN_TOKENS 7
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/* There are no machine-specific operands so we #define this to nothing. */
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#define md_operand(x)
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/* Function prototypes exported to rest of GAS. */
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extern void md_assemble (char *op_str);
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extern void md_end (void);
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extern void md_begin (void);
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#define tc_fix_adjustable(fixp) pru_fix_adjustable (fixp)
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extern int pru_fix_adjustable (struct fix *);
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#define tc_frob_label(lab) pru_frob_label (lab)
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extern void pru_frob_label (symbolS *);
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extern void md_convert_frag (bfd * headers, segT sec, fragS * fragP);
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#define DIFF_EXPR_OK
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/* FIXME This seems appropriate, given that we intentionally prevent
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PRU's .text from being used in a DIFF expression with symbols from
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other sections. Revisit once GDB is ported. */
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#define CFI_DIFF_EXPR_OK 0
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#define TC_PARSE_CONS_RETURN_TYPE int
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#define TC_PARSE_CONS_RETURN_NONE 0
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#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \
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pru_parse_cons_expression (EXP, NBYTES)
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extern int pru_parse_cons_expression (expressionS *exp, int size);
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#define TC_CONS_FIX_NEW pru_cons_fix_new
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extern void pru_cons_fix_new (struct frag *frag, int where,
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unsigned int nbytes, struct expressionS *exp,
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const int is_pmem);
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/* If you define this macro, it means that `tc_gen_reloc' may return
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multiple relocation entries for a single fixup. In this case, the
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return value of `tc_gen_reloc' is a pointer to a null terminated
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array. */
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#undef RELOC_EXPANSION_POSSIBLE
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/* No shared lib support, so we don't need to ensure externally
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visible symbols can be overridden. */
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#define EXTERN_FORCE_RELOC 0
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/* If defined, this macro allows control over whether fixups for a
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given section will be processed when the linkrelax variable is
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set. Define it to zero and handle things in md_apply_fix instead. */
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#define TC_LINKRELAX_FIXUP(SEG) 0
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/* If this macro returns non-zero, it guarantees that a relocation will be
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emitted even when the value can be resolved locally. Do that if
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linkrelax is turned on. */
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#define TC_FORCE_RELOCATION(fix) pru_force_relocation (fix)
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#define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \
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(! SEG_NORMAL (seg) || pru_force_relocation (fix))
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extern int pru_force_relocation (struct fix *);
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/* Do not use PC relative fixups and relocations for
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anything but real PCREL relocations. */
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#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \
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(((FIX)->fx_r_type != BFD_RELOC_PRU_S10_PCREL) \
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&& ((FIX)->fx_r_type != BFD_RELOC_PRU_U8_PCREL))
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/* Values passed to md_apply_fix don't include the symbol value. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
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/* We don't want gas to fixup the following memory related relocations.
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We will need them in case that we want to do linker relaxation.
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We could in principle keep these fixups in gas when not relaxing.
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However, there is no serious performance penalty when making the linker
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make the fixup work. Check also that fx_addsy is not NULL, in order to
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make sure that the fixup refers to some sort of label. */
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#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \
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if ((FIXP->fx_r_type == BFD_RELOC_PRU_LDI32 \
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|| FIXP->fx_r_type == BFD_RELOC_PRU_U16 \
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|| FIXP->fx_r_type == BFD_RELOC_PRU_U16_PMEMIMM \
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|| FIXP->fx_r_type == BFD_RELOC_PRU_S10_PCREL \
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|| FIXP->fx_r_type == BFD_RELOC_PRU_U8_PCREL \
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|| FIXP->fx_r_type == BFD_RELOC_PRU_32_PMEM \
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|| FIXP->fx_r_type == BFD_RELOC_PRU_16_PMEM) \
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&& FIXP->fx_addsy != NULL \
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&& FIXP->fx_subsy == NULL) \
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{ \
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symbol_mark_used_in_reloc (FIXP->fx_addsy); \
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goto SKIP; \
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}
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/* This macro is evaluated for any fixup with a fx_subsy that
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fixup_segment cannot reduce to a number. If the macro returns
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false an error will be reported. */
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#define TC_VALIDATE_FIX_SUB(fix, seg) pru_validate_fix_sub (fix)
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extern int pru_validate_fix_sub (struct fix *);
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/* We want .cfi_* pseudo-ops for generating unwind info. */
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#define TARGET_USE_CFIPOP 1
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#define DWARF2_DEFAULT_RETURN_COLUMN 31
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#define DWARF2_CIE_DATA_ALIGNMENT (-4)
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#define tc_regname_to_dw2regnum pru_regname_to_dw2regnum
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extern int pru_regname_to_dw2regnum (char *regname);
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#define tc_cfi_frame_initial_instructions pru_frame_initial_instructions
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extern void pru_frame_initial_instructions (void);
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/* The difference between same-section symbols may be affected by linker
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relaxation, so do not resolve such expressions in the assembler. */
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#define md_allow_local_subtract(l,r,s) pru_allow_local_subtract (l, r, s)
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extern bfd_boolean pru_allow_local_subtract (expressionS *, expressionS *,
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segT);
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#endif /* __TC_PRU__ */
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@ -396,6 +396,8 @@ case ${generic_target} in
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ppc-*-kaos*) fmt=elf ;;
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ppc-*-lynxos*) fmt=elf em=lynx ;;
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pru-*-*) fmt=elf ;;
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riscv*-*-*) fmt=elf endian=little em=linux ;;
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s390-*-linux-*) fmt=elf em=linux ;;
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|
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@ -80,6 +80,7 @@ CPU_DOCS = \
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c-pdp11.texi \
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c-pj.texi \
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c-ppc.texi \
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c-pru.texi \
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c-rl78.texi \
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c-riscv.texi \
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c-rx.texi \
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|
|
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@ -355,6 +355,7 @@ CPU_DOCS = \
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c-pdp11.texi \
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c-pj.texi \
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c-ppc.texi \
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c-pru.texi \
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c-rl78.texi \
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c-riscv.texi \
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c-rx.texi \
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|
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@ -62,6 +62,7 @@
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@set PDP11
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@set PJ
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@set PPC
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@set PRU
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@set RL78
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@set RISCV
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@set RX
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|
|
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|
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@ -493,6 +493,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-msolaris}|@b{-mno-solaris}]
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[@b{-nops=@var{count}}]
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@end ifset
|
||||
@ifset PRU
|
||||
|
||||
@emph{Target PRU options:}
|
||||
[@b{-link-relax}]
|
||||
[@b{-mnolink-relax}]
|
||||
[@b{-mno-warn-regname-label}]
|
||||
@end ifset
|
||||
@ifset RL78
|
||||
|
||||
@emph{Target RL78 options:}
|
||||
|
|
@ -1232,6 +1239,24 @@ Generate ``little endian'' format output.
|
|||
@end table
|
||||
@end ifset
|
||||
|
||||
@ifset PRU
|
||||
|
||||
@ifclear man
|
||||
@xref{PRU Options}, for the options available when @value{AS} is configured
|
||||
for a PRU processor.
|
||||
@end ifclear
|
||||
|
||||
@ifset man
|
||||
@c man begin OPTIONS
|
||||
The following options are available when @value{AS} is configured for a
|
||||
PRU processor.
|
||||
@c man end
|
||||
@c man begin INCLUDE
|
||||
@include c-pru.texi
|
||||
@c ended inside the included file
|
||||
@end ifset
|
||||
@end ifset
|
||||
|
||||
@ifset M68HC11
|
||||
The following options are available when @value{AS} is configured for the
|
||||
Motorola 68HC11 or 68HC12 series.
|
||||
|
|
@ -7596,6 +7621,9 @@ subject, see the hardware manufacturer's manual.
|
|||
@ifset PPC
|
||||
* PPC-Dependent:: PowerPC Dependent Features
|
||||
@end ifset
|
||||
@ifset PRU
|
||||
* PRU-Dependent:: PRU Dependent Features
|
||||
@end ifset
|
||||
@ifset RL78
|
||||
* RL78-Dependent:: RL78 Dependent Features
|
||||
@end ifset
|
||||
|
|
@ -7825,6 +7853,10 @@ family.
|
|||
@include c-ppc.texi
|
||||
@end ifset
|
||||
|
||||
@ifset PRU
|
||||
@include c-pru.texi
|
||||
@end ifset
|
||||
|
||||
@ifset RL78
|
||||
@include c-rl78.texi
|
||||
@end ifset
|
||||
|
|
|
|||
|
|
@ -0,0 +1,150 @@
|
|||
@c Copyright (C) 2015-2016 Free Software Foundation, Inc.
|
||||
@c This is part of the GAS manual.
|
||||
@c For copying conditions, see the file as.texinfo.
|
||||
@c man end
|
||||
@ifset GENERIC
|
||||
@page
|
||||
@node PRU-Dependent
|
||||
@chapter PRU Dependent Features
|
||||
@end ifset
|
||||
|
||||
@cindex PRU support
|
||||
@menu
|
||||
* PRU Options:: Options
|
||||
* PRU Syntax:: Syntax
|
||||
* PRU Relocations:: Relocations
|
||||
* PRU Directives:: PRU Machine Directives
|
||||
* PRU Opcodes:: Opcodes
|
||||
@end menu
|
||||
|
||||
@node PRU Options
|
||||
@section Options
|
||||
@cindex PRU options
|
||||
@cindex options for PRU
|
||||
|
||||
@c man begin OPTIONS
|
||||
@table @gcctabopt
|
||||
|
||||
@cindex @code{mlink-relax} command line option, PRU
|
||||
@item -mlink-relax
|
||||
Assume that LD would optimize LDI32 instructions by checking the upper
|
||||
16 bits of the @var{expression}. If they are all zeros, then LD would
|
||||
shorten the LDI32 instruction to a single LDI. In such case @code{@value{AS}}
|
||||
will output DIFF relocations for diff expressions.
|
||||
|
||||
@cindex @code{mno-link-relax} command line option, PRU
|
||||
@item -mno-link-relax
|
||||
Assume that LD would not optimize LDI32 instructions. As a consequence,
|
||||
DIFF relocations will not be emitted.
|
||||
|
||||
@cindex @code{mno-warn-regname-label} command line option, PRU
|
||||
@item -mno-warn-regname-label
|
||||
Do not warn if a label name matches a register name. Usually assembler
|
||||
programmers will want this warning to be emitted. C compilers may want
|
||||
to turn this off.
|
||||
|
||||
@end table
|
||||
@c man end
|
||||
|
||||
@node PRU Syntax
|
||||
@section Syntax
|
||||
@menu
|
||||
* PRU Chars:: Special Characters
|
||||
@end menu
|
||||
|
||||
|
||||
@node PRU Chars
|
||||
@subsection Special Characters
|
||||
|
||||
@cindex line comment character, PRU
|
||||
@cindex PRU line comment character
|
||||
@samp{#} and @samp{;} are the line comment characters.
|
||||
|
||||
|
||||
@node PRU Relocations
|
||||
@section PRU Machine Relocations
|
||||
|
||||
@cindex machine relocations, PRU
|
||||
@cindex PRU machine relocations
|
||||
|
||||
@table @code
|
||||
|
||||
@cindex @code{pmem} directive, PRU
|
||||
@item %pmem(@var{expression})
|
||||
Convert @var{expression} from byte-address to a
|
||||
word-address. In other words, shift right by two.
|
||||
|
||||
@item %label(@var{expression})
|
||||
Mark the given operand as a label. This is useful if you need to jump to
|
||||
a label that matches a register name.
|
||||
|
||||
@smallexample
|
||||
@group
|
||||
r1:
|
||||
jmp r1 ; Will jump to register R1
|
||||
jmp %label(r1) ; Will jump to label r1
|
||||
@end group
|
||||
@end smallexample
|
||||
|
||||
@end table
|
||||
|
||||
|
||||
@node PRU Directives
|
||||
@section PRU Machine Directives
|
||||
|
||||
@cindex machine directives, PRU
|
||||
@cindex PRU machine directives
|
||||
|
||||
@table @code
|
||||
|
||||
@cindex @code{align} directive, PRU
|
||||
@item .align @var{expression} [, @var{expression}]
|
||||
This is the generic @code{.align} directive, however
|
||||
this aligns to a power of two.
|
||||
|
||||
@cindex @code{word} directive, PRU
|
||||
@item .word @var{expression}
|
||||
Create an aligned constant 4 bytes in size.
|
||||
|
||||
@cindex @code{dword} directive, PRU
|
||||
@item .dword @var{expression}
|
||||
Create an aligned constant 8 bytes in size.
|
||||
|
||||
@cindex @code{2byte} directive, PRU
|
||||
@item .2byte @var{expression}
|
||||
Create an unaligned constant 2 bytes in size.
|
||||
|
||||
@cindex @code{4byte} directive, PRU
|
||||
@item .4byte @var{expression}
|
||||
Create an unaligned constant 4 bytes in size.
|
||||
|
||||
@cindex @code{8byte} directive, PRU
|
||||
@item .8byte @var{expression}
|
||||
Create an unaligned constant 8 bytes in size.
|
||||
|
||||
@cindex @code{16byte} directive, PRU
|
||||
@item .16byte @var{expression}
|
||||
Create an unaligned constant 16 bytes in size.
|
||||
|
||||
@cindex @code{set no_warn_regname_label} directive, PRU
|
||||
@item .set no_warn_regname_label
|
||||
Do not output warnings when a label name matches a register name. Equivalent
|
||||
to passing the @code{-mno-warn-regname-label} command line option.
|
||||
|
||||
@end table
|
||||
|
||||
@node PRU Opcodes
|
||||
@section Opcodes
|
||||
|
||||
@cindex PRU opcodes
|
||||
@cindex opcodes for PRU
|
||||
@code{@value{AS}} implements all the standard PRU core V3 opcodes in the
|
||||
original pasm assembler. Older cores are not supported by @code{@value{AS}}.
|
||||
|
||||
GAS also implements the LDI32 pseudo instruction for loading a 32-bit
|
||||
immediate value into a register.
|
||||
|
||||
@smallexample
|
||||
ldi32 sp, __stack_top
|
||||
ldi32 r14, 0x12345678
|
||||
@end smallexample
|
||||
|
|
@ -131,6 +131,8 @@ config/tc-pj.c
|
|||
config/tc-pj.h
|
||||
config/tc-ppc.c
|
||||
config/tc-ppc.h
|
||||
config/tc-pru.c
|
||||
config/tc-pru.h
|
||||
config/tc-riscv.c
|
||||
config/tc-riscv.h
|
||||
config/tc-rl78.c
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ if {
|
|||
|| [istarget mn10*-*-*]
|
||||
|| [istarget msp430-*-*]
|
||||
|| [istarget nds32*-*-*]
|
||||
|| [istarget pru-*-*]
|
||||
|| [istarget rl78-*-*]
|
||||
|| [istarget xtensa*-*-*] } {
|
||||
run_dump_test "lns-common-1-alt"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU ALU
|
||||
|
||||
# Test the ALU instructions
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 00e4e4e4 add fp, fp, fp
|
||||
0+0004 <[^>]*> 01ffe4e4 add fp, fp, 255
|
||||
0+0008 <[^>]*> 0100e4e4 add fp, fp, 0
|
||||
0+000c <[^>]*> 0100e4e4 add fp, fp, 0
|
||||
0+0010 <[^>]*> 0100a424 add fp.b1, fp.w1, 0
|
||||
0+0014 <[^>]*> 00634221 add r1.b1, sp.b2, ra.b3
|
||||
0+0018 <[^>]*> 02634221 adc r1.b1, sp.b2, ra.b3
|
||||
0+001c <[^>]*> 03634221 adc r1.b1, sp.b2, 99
|
||||
0+0020 <[^>]*> 00e0e0e0 add r0, r0, r0
|
||||
0+0024 <[^>]*> 02e0e0e0 adc r0, r0, r0
|
||||
0+0028 <[^>]*> 050affe1 sub r1, r31, 10
|
||||
0+002c <[^>]*> 070affe1 suc r1, r31, 10
|
||||
0+0030 <[^>]*> 090affff lsl r31, r31, 10
|
||||
0+0034 <[^>]*> 0b0affff lsr r31, r31, 10
|
||||
0+0038 <[^>]*> 0d0a70f0 rsb r16, r16.b3, 10
|
||||
0+003c <[^>]*> 0f0a70f0 rsc r16, r16.b3, 10
|
||||
0+0040 <[^>]*> 11aa61a1 and r1.w1, r1.b3, 170
|
||||
0+0044 <[^>]*> 13aa61a1 or r1.w1, r1.b3, 170
|
||||
0+0048 <[^>]*> 15aa61a1 xor r1.w1, r1.b3, 170
|
||||
0+004c <[^>]*> 1700e1e2 not sp, r1
|
||||
0+0050 <[^>]*> 18e2e1e1 min r1, r1, sp
|
||||
0+0054 <[^>]*> 1ac3e2e1 max r1, sp, ra.w2
|
||||
0+0058 <[^>]*> 1cc3e2e1 clr r1, sp, ra.w2
|
||||
0+005c <[^>]*> 1f0ce2e1 set r1, sp, 12
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Source file used to test the ALU class of instructions.
|
||||
|
||||
foo:
|
||||
# Test various addressing modes
|
||||
add fp, fp, fp
|
||||
add fp, fp, 0xff
|
||||
add fp, fp, 0
|
||||
add fp, fp, 0
|
||||
add fp.b1, fp.w1, 0
|
||||
add r1.b1, r2.b2, r3.b3
|
||||
adc r1.b1, r2.b2, r3.b3
|
||||
adc r1.b1, r2.b2, 101-2
|
||||
|
||||
# Test ALU opcodes
|
||||
add r0, r0, r0
|
||||
adc r0, r0, r0
|
||||
sub r1, r31, 10
|
||||
suc r1, r31, 10
|
||||
lsl r31, r31, 10
|
||||
lsr r31, r31, 10
|
||||
rsb r16, r16.b3, 10
|
||||
rsc r16, r16.b3, 10
|
||||
and r1.w1, r1.b3, 0xaa
|
||||
or r1.w1, r1.b3, 0xaa
|
||||
xor r1.w1, r1.b3, 0xaa
|
||||
not r2, r1
|
||||
min r1, r1, r2
|
||||
max r1, r2, r3.w2
|
||||
clr r1, r2, r3.w2
|
||||
set r1, r2, 12
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU branch
|
||||
|
||||
# Test the branch instructions
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 20ea0000 jmp r10
|
||||
0+0004 <[^>]*> 208a0000 jmp r10.w0
|
||||
0+0008 <[^>]*> 21004000 jmp 00000100 <[^>]*>
|
||||
0+000c <[^>]*> 22ca00f6 jal r22, r10.w2
|
||||
0+0010 <[^>]*> 230000f7 jal r23, 00000000 <[^>]*>
|
||||
0+0014 <[^>]*> 23ffffb7 jal r23.w1, 0003fffc <[^>]*>
|
||||
0+0018 <[^>]*> 6100f700 qbgt 00000018 <[^>]*>, r23, 0
|
||||
[\t ]*18: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+001c <[^>]*> 71ff5700 qbge 0000001c <[^>]*>, r23.b2, 255
|
||||
[\t ]*1c: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+0020 <[^>]*> 4820b600 qblt 00000020 <[^>]*>, r22.w1, r0.b1
|
||||
[\t ]*20: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+0024 <[^>]*> 58210000 qble 00000024 <[^>]*>, r0.b0, r1.b1
|
||||
[\t ]*24: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+0028 <[^>]*> 50034100 qbeq 00000028 <[^>]*>, r1.b2, ra.b0
|
||||
[\t ]*28: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+002c <[^>]*> 68f6f500 qbne 0000002c <[^>]*>, r21, r22
|
||||
[\t ]*2c: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+0030 <[^>]*> 78000000 qba 00000030 <[^>]*>
|
||||
[\t ]*30: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
#0+0034 <[^>]*> d0edec00 qbbs 00000034 <[^>]*>, r12, r13
|
||||
0+0034 <[^>]*> d0edec00 wbc r12, r13
|
||||
[\t ]*34: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
#0+0038 <[^>]*> d105ec00 qbbs 00000038 <[^>]*>, r12, 5
|
||||
0+0038 <[^>]*> d105ec00 wbc r12, 5
|
||||
[\t ]*38: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
#0+003c <[^>]*> c8edec00 qbbc 0000003c <[^>]*>, r12, r13
|
||||
0+003c <[^>]*> c8edec00 wbs r12, r13
|
||||
[\t ]*3c: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
#0+0040 <[^>]*> c905ec00 qbbc 00000040 <[^>]*>, r12, 5
|
||||
0+0040 <[^>]*> c905ec00 wbs r12, 5
|
||||
[\t ]*40: R_PRU_S10_PCREL[\t ]*.text\+0x60
|
||||
0+0044 <[^>]*> 6100f700 qbgt 00000044 <[^>]*>, r23, 0
|
||||
[\t ]*44: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
0+0048 <[^>]*> 71ff5700 qbge 00000048 <[^>]*>, r23.b2, 255
|
||||
[\t ]*48: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
0+004c <[^>]*> 4820b600 qblt 0000004c <[^>]*>, r22.w1, r0.b1
|
||||
[\t ]*4c: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
0+0050 <[^>]*> 58210000 qble 00000050 <[^>]*>, r0.b0, r1.b1
|
||||
[\t ]*50: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
0+0054 <[^>]*> 50034100 qbeq 00000054 <[^>]*>, r1.b2, ra.b0
|
||||
[\t ]*54: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
0+0058 <[^>]*> 68f6f500 qbne 00000058 <[^>]*>, r21, r22
|
||||
[\t ]*58: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
0+005c <[^>]*> 78000000 qba 0000005c <[^>]*>
|
||||
[\t ]*5c: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
#0+0060 <[^>]*> d0edec00 qbbs 00000060 <[^>]*>, r12, r13
|
||||
0+0060 <[^>]*> d0edec00 wbc r12, r13
|
||||
[\t ]*60: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
#0+0064 <[^>]*> d105ec00 qbbs 00000064 <[^>]*>, r12, 5
|
||||
0+0064 <[^>]*> d105ec00 wbc r12, 5
|
||||
[\t ]*64: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
#0+0068 <[^>]*> c8edec00 qbbc 00000068 <[^>]*>, r12, r13
|
||||
0+0068 <[^>]*> c8edec00 wbs r12, r13
|
||||
[\t ]*68: R_PRU_S10_PCREL[\t ]*.text\+0xc
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# Source file used to test the miscellaneous instructions.
|
||||
|
||||
foo:
|
||||
L1:
|
||||
jmp r10
|
||||
jmp r10.w0
|
||||
jmp 0x100
|
||||
|
||||
L2:
|
||||
jal r22, r10.w2
|
||||
jal r23, 0
|
||||
jal r23.w1, 0x3fffc
|
||||
|
||||
# relative branches - forward jump
|
||||
L3:
|
||||
qbgt L5, r23, 0
|
||||
qbge L5, r23.b2, 255
|
||||
qblt L5, r22.w1, r0.b1
|
||||
qble L5, r0.b0, r1.b1
|
||||
qbeq L5, r1.b2, r3.b0
|
||||
qbne L5, r21, r22
|
||||
qba L5
|
||||
|
||||
qbbs L5, r12, r13
|
||||
qbbs L5, r12, 5
|
||||
qbbc L5, r12, r13
|
||||
qbbc L5, r12, 5
|
||||
|
||||
# relative branches - backward jump
|
||||
L4:
|
||||
qbgt L2, r23, 0
|
||||
qbge L2, r23.b2, 255
|
||||
qblt L2, r22.w1, r0.b1
|
||||
qble L2, r0.b0, r1.b1
|
||||
qbeq L2, r1.b2, r3.b0
|
||||
qbne L2, r21, r22
|
||||
qba L2
|
||||
|
||||
L5:
|
||||
qbbs L2, r12, r13
|
||||
qbbs L2, r12, 5
|
||||
qbbc L2, r12, r13
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
.*illegal.s: Assembler messages:
|
||||
.*illegal.s:5: Error: unknown register r56
|
||||
.*illegal.s:8: Error: unrecognised instruction fop
|
||||
.*illegal.s:10: Error: too many arguments
|
||||
.*illegal.s:11: Error: too many arguments
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# Source file used to test illegal operands.
|
||||
|
||||
foo:
|
||||
# Illegal registers
|
||||
add r56,r4,r5
|
||||
add r4,r0,r2
|
||||
# Illegal opcodes
|
||||
fop r3,r4,r5
|
||||
# Extra operands
|
||||
nop Crapola
|
||||
add r2, r2, r2, r4
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU ldi
|
||||
|
||||
# Test the load/store operations
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 240000f0 ldi r16, 0
|
||||
[\t ]*0: R_PRU_LDI32 \*ABS\*\+0x12345678
|
||||
0+0004 <[^>]*> 240000d0 ldi r16.w2, 0
|
||||
0+0008 <[^>]*> 241234f0 ldi r16, 4660
|
||||
0+000c <[^>]*> 240000f0 ldi r16, 0
|
||||
[\t ]*c: R_PRU_U16_PMEMIMM .text
|
||||
0+0010 <[^>]*> 240000f0 ldi r16, 0
|
||||
[\t ]*10: R_PRU_LDI32 var1
|
||||
0+0014 <[^>]*> 240000d0 ldi r16.w2, 0
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
# Source file used to test the LDI instructions.
|
||||
|
||||
.extern var1
|
||||
foo:
|
||||
# immediate load
|
||||
ldi32 r16, 0x12345678
|
||||
ldi r16, 0x1234
|
||||
ldi r16, %pmem(foo)
|
||||
ldi32 r16, var1
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU load-store
|
||||
|
||||
# Test the load/store operations
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 240000f0 ldi r16, 0
|
||||
0+0004 <[^>]*> 24fffff0 ldi r16, 65535
|
||||
0+0008 <[^>]*> 2401fff0 ldi r16, 511
|
||||
0+000c <[^>]*> f0611e20 lbbo r0.b1, r30, r1.b3, 1
|
||||
0+0010 <[^>]*> fe41bec0 lbbo r0.b2, r30, r1.b2, 124
|
||||
0+0014 <[^>]*> f1ff1e60 lbbo r0.b3, r30, 255, 1
|
||||
0+0018 <[^>]*> f1011e80 lbbo r0.b0, r30, 1, 2
|
||||
0+001c <[^>]*> fb005e00 lbbo r0.b0, r30, 0, 85
|
||||
0+0020 <[^>]*> fea1d912 lbbo r18.b0, r25, r1.w1, r0.b0
|
||||
0+0024 <[^>]*> ff65d992 lbbo r18.b0, r25, 101, r0.b1
|
||||
0+0028 <[^>]*> fee1f992 lbbo r18.b0, r25, r1, r0.b3
|
||||
0+002c <[^>]*> e0611e20 sbbo r0.b1, r30, r1.b3, 1
|
||||
0+0030 <[^>]*> ee41bec0 sbbo r0.b2, r30, r1.b2, 124
|
||||
0+0034 <[^>]*> e1ff1e60 sbbo r0.b3, r30, 255, 1
|
||||
0+0038 <[^>]*> e1011e80 sbbo r0.b0, r30, 1, 2
|
||||
0+003c <[^>]*> eb005e00 sbbo r0.b0, r30, 0, 85
|
||||
0+0040 <[^>]*> eee1d912 sbbo r18.b0, r25, r1, r0.b0
|
||||
0+0044 <[^>]*> ef65d992 sbbo r18.b0, r25, 101, r0.b1
|
||||
0+0048 <[^>]*> eee1f992 sbbo r18.b0, r25, r1, r0.b3
|
||||
0+004c <[^>]*> 9105608a lbco r10.b0, 0, 5, 8
|
||||
0+0050 <[^>]*> 90ab618a lbco r10.b0, 1, r11.w1, 8
|
||||
0+0054 <[^>]*> 91057f8a lbco r10.b0, 31, 5, 8
|
||||
0+0058 <[^>]*> 8105608a sbco r10.b0, 0, 5, 8
|
||||
0+005c <[^>]*> 80ab618a sbco r10.b0, 1, r11.w1, 8
|
||||
0+0060 <[^>]*> 81057f8a sbco r10.b0, 31, 5, 8
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# Source file used to test the load/store instructions.
|
||||
|
||||
foo:
|
||||
# immediate load
|
||||
ldi r16, 0
|
||||
ldi r16, 0xffff
|
||||
ldi r16, 511
|
||||
|
||||
# load
|
||||
lbbo &r0.b1, r30, r1.b3, 1
|
||||
lbbo r0.b2, r30, r1.b2, 124
|
||||
lbbo r0.b3, r30, 255, 1
|
||||
lbbo &r0, r30, 1, 2
|
||||
lbbo r0, r30, 0, 0x55
|
||||
lbbo r18, r25, r1.w1, r0.b0
|
||||
lbbo r18, r25, 101, r0.b1
|
||||
lbbo r18, r25, r1, r0.b3
|
||||
|
||||
# store
|
||||
sbbo &r0.b1, r30, r1.b3, 1
|
||||
sbbo r0.b2, r30, r1.b2, 124
|
||||
sbbo r0.b3, r30, 255, 1
|
||||
sbbo &r0, r30, 1, 2
|
||||
sbbo r0, r30, 0, 0x55
|
||||
sbbo r18, r25, r1, r0.b0
|
||||
sbbo r18, r25, 101, r0.b1
|
||||
sbbo r18, r25, r1, r0.b3
|
||||
|
||||
# load with constant table address
|
||||
lbco r10, 0, 5, 8
|
||||
lbco r10, 1, r11.w1, 8
|
||||
lbco r10, 31, 5, 8
|
||||
|
||||
# store with constant table address
|
||||
sbco r10, 0, 5, 8
|
||||
sbco r10, 1, r11.w1, 8
|
||||
sbco r10, 31, 5, 8
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU loop
|
||||
|
||||
# Test the loop instructions
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 304a0000 loop 00000000 <[^>]*>, r10.b2
|
||||
[\t ]*0: R_PRU_U8_PCREL[\t ]*.text\+0x14
|
||||
0+0004 <[^>]*> 30eb8000 iloop 00000004 <[^>]*>, r11
|
||||
[\t ]*4: R_PRU_U8_PCREL[\t ]*.text\+0x14
|
||||
0+0008 <[^>]*> 00e0e0e0 add r0, r0, r0
|
||||
0+000c <[^>]*> 00e0e0e0 add r0, r0, r0
|
||||
0+0010 <[^>]*> 00e0e0e0 add r0, r0, r0
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# Source file used to test the loop instructions.
|
||||
|
||||
foo:
|
||||
L1:
|
||||
loop L2, r10.b2
|
||||
iloop L2, r11
|
||||
add r0, r0, r0
|
||||
add r0, r0, r0
|
||||
add r0, r0, r0
|
||||
L2:
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU misc
|
||||
|
||||
# Test the miscellaneous instruction
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 2a000000 halt
|
||||
0+0004 <[^>]*> 3e800000 slp 1
|
||||
0+0008 <[^>]*> 3e000000 slp 0
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# Source file used to test the miscellaneous instructions.
|
||||
|
||||
foo:
|
||||
halt
|
||||
slp 1
|
||||
slp 0
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# Copyright (C) 2014-2016 Free Software Foundation, Inc.
|
||||
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
#
|
||||
# Some generic PRU tests
|
||||
#
|
||||
|
||||
if { [istarget pru-*-*] } {
|
||||
run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
|
||||
|
||||
run_list_test "illegal" ""
|
||||
run_list_test "warn_reglabel" ""
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU pseudo
|
||||
|
||||
# Test the pseudo instruction
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 1300e2e1 mov r1, sp
|
||||
0+0004 <[^>]*> 12e0e0e0 nop
|
||||
0+0008 <[^>]*> 230100c3 call 00000400 <[^>]*>
|
||||
0+000c <[^>]*> 22ea00c3 call r10
|
||||
0+0010 <[^>]*> 20c30000 ret
|
||||
0+0014 <[^>]*> d10cac00 wbc r12.w1, 12
|
||||
0+0018 <[^>]*> c8e1ec00 wbs r12, r1
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# Source file used to test the pseudo instructions.
|
||||
|
||||
foo:
|
||||
mov r1, r2
|
||||
nop
|
||||
call 0x400
|
||||
call r10
|
||||
ret
|
||||
wbc r12.w1, 12
|
||||
wbs r12, r1
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
.*warn_reglabel.s: Assembler messages:
|
||||
.*warn_reglabel.s:3: Warning: Label "r30" matches a CPU register name
|
||||
.*warn_reglabel.s:5: Warning: Label "r1.b2" matches a CPU register name
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# Source file used to test warnings
|
||||
|
||||
r30:
|
||||
nop
|
||||
r1.b2:
|
||||
nop
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: PRU xfr
|
||||
|
||||
# Test the XFR class of instruction
|
||||
|
||||
.*: +file format elf32-pru
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 2eff8002 zero sp.b0, 1
|
||||
0+0004 <[^>]*> 2eff81d7 zero r23.b2, 4
|
||||
0+0008 <[^>]*> 2effbd80 zero r0.b0, 124
|
||||
0+000c <[^>]*> 2eff0002 fill sp.b0, 1
|
||||
0+0010 <[^>]*> 2eff01b7 fill r23.b1, 4
|
||||
0+0014 <[^>]*> 2eff3d80 fill r0.b0, 124
|
||||
0+0018 <[^>]*> 2e80000a xin 0, r10.b0, 1
|
||||
0+001c <[^>]*> 2e803daa xin 0, r10.b1, 124
|
||||
0+0020 <[^>]*> 2efe806a xin 253, r10.b3, 1
|
||||
0+0024 <[^>]*> 2efebdca xin 253, r10.b2, 124
|
||||
0+0028 <[^>]*> 2eaaaa0c xin 85, r12.b0, 85
|
||||
0+002c <[^>]*> 2f00000a xout 0, r10.b0, 1
|
||||
0+0030 <[^>]*> 2f003daa xout 0, r10.b1, 124
|
||||
0+0034 <[^>]*> 2f7e806a xout 253, r10.b3, 1
|
||||
0+0038 <[^>]*> 2f7ebdca xout 253, r10.b2, 124
|
||||
0+003c <[^>]*> 2f2aaa0c xout 85, r12.b0, 85
|
||||
0+0040 <[^>]*> 2f80000a xchg 0, r10.b0, 1
|
||||
0+0044 <[^>]*> 2f803daa xchg 0, r10.b1, 124
|
||||
0+0048 <[^>]*> 2ffe806a xchg 253, r10.b3, 1
|
||||
0+004c <[^>]*> 2ffebdca xchg 253, r10.b2, 124
|
||||
0+0050 <[^>]*> 2faaaa0c xchg 85, r12.b0, 85
|
||||
0+0054 <[^>]*> 2e80400a sxin 0, r10.b0, 1
|
||||
0+0058 <[^>]*> 2e807daa sxin 0, r10.b1, 124
|
||||
0+005c <[^>]*> 2efec06a sxin 253, r10.b3, 1
|
||||
0+0060 <[^>]*> 2efefdca sxin 253, r10.b2, 124
|
||||
0+0064 <[^>]*> 2eaaea0c sxin 85, r12.b0, 85
|
||||
0+0068 <[^>]*> 2f00400a sxout 0, r10.b0, 1
|
||||
0+006c <[^>]*> 2f007daa sxout 0, r10.b1, 124
|
||||
0+0070 <[^>]*> 2f7ec06a sxout 253, r10.b3, 1
|
||||
0+0074 <[^>]*> 2f7efdca sxout 253, r10.b2, 124
|
||||
0+0078 <[^>]*> 2f2aea0c sxout 85, r12.b0, 85
|
||||
0+007c <[^>]*> 2f80400a sxchg 0, r10.b0, 1
|
||||
0+0080 <[^>]*> 2f807daa sxchg 0, r10.b1, 124
|
||||
0+0084 <[^>]*> 2ffec06a sxchg 253, r10.b3, 1
|
||||
0+0088 <[^>]*> 2ffefdca sxchg 253, r10.b2, 124
|
||||
0+008c <[^>]*> 2faaea0c sxchg 85, r12.b0, 85
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
# Source file used to test the XFR-class of instructions.
|
||||
|
||||
foo:
|
||||
# register clear and fill
|
||||
zero r2, 1
|
||||
zero r23.b2, 4
|
||||
zero r0, 124
|
||||
fill r2, 1
|
||||
fill r23.b1, 4
|
||||
fill r0, 124
|
||||
|
||||
# XIN
|
||||
xin 0, r10, 1
|
||||
xin 0, r10.b1, 124
|
||||
xin 253, r10.b3, 1
|
||||
xin 253, r10.b2, 124
|
||||
xin 85, r12.b0, 85
|
||||
|
||||
# XOUT
|
||||
xout 0, r10, 1
|
||||
xout 0, r10.b1, 124
|
||||
xout 253, r10.b3, 1
|
||||
xout 253, r10.b2, 124
|
||||
xout 85, r12.b0, 85
|
||||
|
||||
# XCHG
|
||||
xchg 0, r10, 1
|
||||
xchg 0, r10.b1, 124
|
||||
xchg 253, r10.b3, 1
|
||||
xchg 253, r10.b2, 124
|
||||
xchg 85, r12.b0, 85
|
||||
|
||||
# SXIN
|
||||
sxin 0, r10, 1
|
||||
sxin 0, r10.b1, 124
|
||||
sxin 253, r10.b3, 1
|
||||
sxin 253, r10.b2, 124
|
||||
sxin 85, r12.b0, 85
|
||||
|
||||
# SXOUT
|
||||
sxout 0, r10, 1
|
||||
sxout 0, r10.b1, 124
|
||||
sxout 253, r10.b3, 1
|
||||
sxout 253, r10.b2, 124
|
||||
sxout 85, r12.b0, 85
|
||||
|
||||
# XCHG
|
||||
sxchg 0, r10, 1
|
||||
sxchg 0, r10.b1, 124
|
||||
sxchg 253, r10.b3, 1
|
||||
sxchg 253, r10.b2, 124
|
||||
sxchg 85, r12.b0, 85
|
||||
Loading…
Reference in New Issue