* gas/config/tc-arm.c (do_t_mov_cmp): In unified syntax encode movs as
lsls and not adds. * gas/testsuite/gas/arm/thumb2_it_auto.d: Update for change in movs encoding. gas/arm/thumb2_it.d: Likewise. gas/arm/thumb32.d: Likewise.
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@ -1,3 +1,8 @@
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2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (do_t_mov_cmp): In unified syntax encode movs as
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lsls and not adds.
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2010-05-27 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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2010-05-27 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (encode_thumb2_ldmstm): Make warning about
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* config/tc-arm.c (encode_thumb2_ldmstm): Make warning about
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@ -10369,8 +10369,8 @@ do_t_mov_cmp (void)
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case T_MNEM_movs:
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case T_MNEM_movs:
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/* We know we have low registers at this point.
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/* We know we have low registers at this point.
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Generate ADD Rd, Rs, #0. */
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Generate LSLS Rd, Rs, #0. */
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inst.instruction = T_OPCODE_ADD_I3;
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inst.instruction = T_OPCODE_LSL_I;
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inst.instruction |= Rn;
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inst.instruction |= Rn;
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inst.instruction |= Rm << 3;
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inst.instruction |= Rm << 3;
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break;
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break;
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@ -1,3 +1,9 @@
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2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/thumb2_it_auto.d: Update for change in movs encoding.
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gas/arm/thumb2_it.d: Likewise.
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gas/arm/thumb32.d: Likewise.
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2010-05-27 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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2010-05-27 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/thumb2_ldmstm.d: Add new testcases.
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* gas/arm/thumb2_ldmstm.d: Add new testcases.
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@ -45,7 +45,7 @@ Disassembly of section .text:
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0+062 <[^>]+> bf08 it eq
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0+062 <[^>]+> bf08 it eq
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0+064 <[^>]+> 4640 moveq r0, r8
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0+064 <[^>]+> 4640 moveq r0, r8
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0+066 <[^>]+> 4608 mov r0, r1
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0+066 <[^>]+> 4608 mov r0, r1
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0+068 <[^>]+> 1c08 adds r0, r1, #0
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0+068 <[^>]+> 0008 lsls r0, r1, #0
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0+06a <[^>]+> ea5f 0008 movs.w r0, r8
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0+06a <[^>]+> ea5f 0008 movs.w r0, r8
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0+06e <[^>]+> bf01 itttt eq
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0+06e <[^>]+> bf01 itttt eq
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0+070 <[^>]+> 43c8 mvneq r0, r1
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0+070 <[^>]+> 43c8 mvneq r0, r1
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@ -45,7 +45,7 @@ Disassembly of section .text:
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0+062 <[^>]+> bf08 it eq
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0+062 <[^>]+> bf08 it eq
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0+064 <[^>]+> 4640 moveq r0, r8
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0+064 <[^>]+> 4640 moveq r0, r8
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0+066 <[^>]+> 4608 mov r0, r1
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0+066 <[^>]+> 4608 mov r0, r1
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0+068 <[^>]+> 1c08 adds r0, r1, #0
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0+068 <[^>]+> 0008 lsls r0, r1, #0
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0+06a <[^>]+> ea5f 0008 movs.w r0, r8
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0+06a <[^>]+> ea5f 0008 movs.w r0, r8
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0+06e <[^>]+> bf01 itttt eq
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0+06e <[^>]+> bf01 itttt eq
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0+070 <[^>]+> 43c8 mvneq r0, r1
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0+070 <[^>]+> 43c8 mvneq r0, r1
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@ -618,9 +618,9 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> eb10 0f09 cmn\.w r0, r9
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0[0-9a-f]+ <[^>]+> eb10 0f09 cmn\.w r0, r9
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0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81
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0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81
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0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81
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0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81
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0[0-9a-f]+ <[^>]+> 1c00 adds r0, r0, #0
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0[0-9a-f]+ <[^>]+> 0000 lsls r0, r0, #0
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0[0-9a-f]+ <[^>]+> 4600 mov r0, r0
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0[0-9a-f]+ <[^>]+> 4600 mov r0, r0
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0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0
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0[0-9a-f]+ <[^>]+> 0005 lsls r5, r0, #0
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0[0-9a-f]+ <[^>]+> 4628 mov r0, r5
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0[0-9a-f]+ <[^>]+> 4628 mov r0, r5
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0[0-9a-f]+ <[^>]+> ea4f 4065 mov\.w r0, r5, asr #17
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0[0-9a-f]+ <[^>]+> ea4f 4065 mov\.w r0, r5, asr #17
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0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0
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0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0
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