Power10 VSX 32-byte storage access
bfd/ * elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp. opcodes/ * ppc-opc.c (insert_xtp, extract_xtp): New functions. (XTP, DQXP, DQXP_MASK): Define. (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. (prefix_opcodes): Add plxvp and pstxvp. gas/ * testsuite/gas/ppc/vsx_32byte.d, * testsuite/gas/ppc/vsx_32byte.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. ld/ * testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp. * testsuite/ld-powerpc/pcrelopt.d: Update.
This commit is contained in:
Alan Modra
parent
f4791f1afa
commit
94ba9882d5
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@ -1,3 +1,7 @@
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2020-05-11 Alan Modra <amodra@gmail.com>
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* elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp.
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2020-05-11 Alan Modra <amodra@gmail.com>
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* elf64-ppc.c: Rename powerxx to power10 throughout.
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@ -8605,6 +8605,15 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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off = insn2 & 0xffff;
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break;
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case 6: /* lxvp, stxvp */
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if ((insn2 & 0xe) != 0)
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return FALSE;
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| ((insn2 & 1) == 0 ? 58ULL << 26 : 62ULL << 26)
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| (insn2 & (31ULL << 21)));
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off = insn2 & 0xfff0;
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break;
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case 62: /* std, stq */
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if ((insn2 & 1) != 0)
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return FALSE;
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@ -1,3 +1,9 @@
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2020-05-11 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/vsx_32byte.d,
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* testsuite/gas/ppc/vsx_32byte.s: New test.
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* testsuite/gas/ppc/ppc.exp: Run it.
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2020-05-11 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/vec_mul.s,
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@ -133,3 +133,4 @@ if { [supports_ppc64] } then {
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}
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run_dump_test "byte_rev"
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run_dump_test "vec_mul"
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run_dump_test "vsx_32byte"
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@ -0,0 +1,33 @@
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#as: -mpower10
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#objdump: -dr -Mpower10
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#name: VSX 32-byte loads and stores
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.*
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Disassembly of section \.text:
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0+0 <_start>:
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.*: (18 5f 00 00|00 00 5f 18) lxvp vs2,0\(r31\)
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.*: (1b e0 ff f0|f0 ff e0 1b) lxvp vs62,-16\(0\)
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.*: (04 00 00 00|00 00 00 04) plxvp vs4,1\(r30\)
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.*: (e8 9e 00 01|01 00 9e e8)
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.*: (04 03 ff ff|ff ff 03 04) plxvp vs60,-1\(r9\)
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.*: (eb a9 ff ff|ff ff a9 eb)
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.*: (04 10 12 34|34 12 10 04) plxvp vs6,305419896
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.*: (e8 c0 56 78|78 56 c0 e8)
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.*: (04 13 ff ff|ff ff 13 04) plxvp vs58,-32
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.*: (eb 60 ff e0|e0 ff 60 eb)
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.*: (7f 20 0a 9a|9a 0a 20 7f) lxvpx vs56,0,r1
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.*: (19 1d 00 01|01 00 1d 19) stxvp vs8,0\(r29\)
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.*: (1a e0 ff f1|f1 ff e0 1a) stxvp vs54,-16\(0\)
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.*: (04 00 00 00|00 00 00 04) pstxvp vs10,1\(r28\)
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.*: (f9 5c 00 01|01 00 5c f9)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 03 ff ff|ff ff 03 04) pstxvp vs52,-1\(r8\)
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.*: (fa a8 ff ff|ff ff a8 fa)
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.*: (04 10 12 34|34 12 10 04) pstxvp vs12,305419896
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.*: (f9 80 56 78|78 56 80 f9)
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.*: (04 13 ff ff|ff ff 13 04) pstxvp vs50,-80
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.*: (fa 60 ff b0|b0 ff 60 fa)
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.*: (7e 20 0b 9a|9a 0b 20 7e) stxvpx vs48,0,r1
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@ -0,0 +1,17 @@
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.text
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_start:
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lxvp 2,0(31)
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lxvp 62,-16(0)
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plxvp 4,1(30)
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plxvp 60,-1(9)
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plxvp 6,0x12345678(0),1
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plxvp 58,_start-.
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lxvpx 56,0,1
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stxvp 8,0(29)
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stxvp 54,-16(0)
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pstxvp 10,1(28)
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pstxvp 52,-1(8)
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pstxvp 12,0x12345678(0),1
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pstxvp 50,_start-.
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stxvpx 48,0,1
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@ -1,3 +1,8 @@
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2020-05-11 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp.
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* testsuite/ld-powerpc/pcrelopt.d: Update.
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2020-05-11 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
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@ -94,3 +94,15 @@ Disassembly of section \.text:
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.*: (06 10 00 01|01 00 10 06) pla r7,65972
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.*: (38 e0 01 b4|b4 01 e0 38)
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.*: (88 c7 00 00|00 00 c7 88) lbz r6,0\(r7\)
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.*: (04 10 00 01|01 00 10 04) plxvp vs62,65960
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.*: (eb e0 01 a8|a8 01 e0 eb)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 00 01|01 00 10 04) plxvp vs0,65948
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.*: (e8 00 01 9c|9c 01 00 e8)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 00 01|01 00 10 04) pstxvp vs62,65936
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.*: (fb e0 01 90|90 01 e0 fb)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 00 01|01 00 10 04) pstxvp vs0,65924
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.*: (f8 00 01 84|84 01 00 f8)
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.*: (60 00 00 00|00 00 00 60) nop
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@ -127,5 +127,21 @@ _start:
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pld 7,sym@got@pcrel
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lbz 6,0(7)
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pld 9,sym@got@pcrel
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.reloc .-8,R_PPC64_PCREL_OPT,0f-(.-8)
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0: lxvp 62,0(9)
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pld 9,sym@got@pcrel
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.reloc .-8,R_PPC64_PCREL_OPT,0f-(.-8)
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0: lxvp 0,0(9)
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pld 9,sym@got@pcrel
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.reloc .-8,R_PPC64_PCREL_OPT,0f-(.-8)
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0: stxvp 62,0(9)
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pld 9,sym@got@pcrel
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.reloc .-8,R_PPC64_PCREL_OPT,0f-(.-8)
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0: stxvp 0,0(9)
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.data
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sym: .space 32
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@ -1,3 +1,10 @@
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (insert_xtp, extract_xtp): New functions.
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(XTP, DQXP, DQXP_MASK): Define.
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(powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
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(prefix_opcodes): Add plxvp and pstxvp.
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
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@ -1594,6 +1594,25 @@ extract_xc6 (uint64_t insn,
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return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
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}
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/* The split XTp field in a vector paired insn. */
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static uint64_t
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insert_xtp (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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return insn | ((value & 0x1e) << 21) | ((value & 0x20) << (21 - 5));
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}
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static int64_t
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extract_xtp (uint64_t insn,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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int *invalid ATTRIBUTE_UNUSED)
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{
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return ((insn >> (21 - 5)) & 0x20) | ((insn >> 21) & 0x1e);
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}
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static uint64_t
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insert_dm (uint64_t insn,
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int64_t value,
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@ -2817,8 +2836,12 @@ const struct powerpc_operand powerpc_operands[] =
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#define XTQ6 XSQ6
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{ 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
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/* The split XTp field in a vector paired instruction. */
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#define XTP XSQ6 + 1
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{ 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR },
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/* The XT field in a plxv instruction. Runs into the OP field. */
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#define XTOP XSQ6 + 1
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#define XTOP XTP + 1
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{ 0x3f, 21, NULL, NULL, PPC_OPERAND_VSR },
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/* The XA field in an XX3 form instruction. This is split. */
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@ -3070,6 +3093,10 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
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#define DQX_MASK DQX (0x3f, 7)
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/* A DQ form VSX vector paired instruction. */
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#define DQXP(op, xop) (OP (op) | ((xop) & 0xf))
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#define DQXP_MASK DQXP (0x3f, 0xf)
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/* A DS form instruction. */
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#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
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#define DS_MASK DSO (0x3f, 3)
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@ -4704,6 +4731,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
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{"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}},
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{"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}},
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{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
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{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
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@ -6190,6 +6220,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
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{"lxvpx", X(31,333), XX1_MASK, POWER10, 0, {XTP, RA0, RB}},
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{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
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{"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
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@ -6568,6 +6600,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
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{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
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{"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XTP, RA0, RB}},
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{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
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{"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
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@ -8045,8 +8079,10 @@ const struct powerpc_opcode prefix_opcodes[] = {
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{"pstfd", PMLS|OP(54), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}},
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{"plq", P8LS|OP(56), P_D_MASK, POWER10, 0, {RTQ, D34, PRAQ, PCREL}},
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{"pld", P8LS|OP(57), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
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{"plxvp", P8LS|OP(58), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}},
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{"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},
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{"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
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{"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}},
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};
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const unsigned int prefix_num_opcodes =
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