Add Aarch64 SVE target description
No code uses the new descriptions yet. gdb/ * aarch64-linux-nat.c (aarch64_linux_read_description): Add parmeter zero. * aarch64-linux-tdep.c (aarch64_linux_core_read_description): Likewise. * aarch64-tdep.c (tdesc_aarch64_list): Add. (aarch64_read_description): Use VQ to index tdesc_aarch64_list. (aarch64_gdbarch_init): Add parmeter zero. * aarch64-tdep.h (aarch64_read_description): Add VQ parmeter. * arch/aarch64.c (aarch64_create_target_description): Check VQ. * arch/aarch64.h (aarch64_create_target_description): Add VQ. parmeter. * doc/gdb.texinfo: Describe SVE feature * features/aarch64-sve.c: New file. gdbserver/ * linux-aarch64-tdesc.c (aarch64_linux_read_description): Add null VQ.
This commit is contained in:
Alan Hayward
parent
22467434fd
commit
95228a0d79
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@ -1,3 +1,19 @@
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2018-05-31 Alan Hayward <alan.hayward@arm.com>
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* aarch64-linux-nat.c (aarch64_linux_read_description):
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Add parmeter zero.
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* aarch64-linux-tdep.c (aarch64_linux_core_read_description):
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Likewise.
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* aarch64-tdep.c (tdesc_aarch64_list): Add.
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(aarch64_read_description): Use VQ to index tdesc_aarch64_list.
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(aarch64_gdbarch_init): Add parmeter zero.
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* aarch64-tdep.h (aarch64_read_description): Add VQ parmeter.
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* arch/aarch64.c (aarch64_create_target_description): Check VQ.
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* arch/aarch64.h (aarch64_create_target_description): Add VQ.
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parmeter.
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* doc/gdb.texinfo: Describe SVE feature
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* features/aarch64-sve.c: New file.
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2018-05-31 Omair Javaid <omair.javaid@linaro.org>
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PR gdb/23210
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@ -537,7 +537,8 @@ aarch64_linux_nat_target::read_description ()
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if (ret == 0)
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return tdesc_arm_with_neon;
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else
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return aarch64_read_description ();
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/* SVE not yet supported. */
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return aarch64_read_description (0);
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}
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/* Convert a native/host siginfo object, into/from the siginfo in the
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@ -233,7 +233,8 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
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NULL, cb_data);
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}
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/* Implement the "core_read_description" gdbarch method. */
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/* Implement the "core_read_description" gdbarch method. SVE not yet
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supported. */
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static const struct target_desc *
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aarch64_linux_core_read_description (struct gdbarch *gdbarch,
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@ -244,7 +245,7 @@ aarch64_linux_core_read_description (struct gdbarch *gdbarch,
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if (target_auxv_search (target, AT_HWCAP, &aarch64_hwcap) != 1)
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return NULL;
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return aarch64_read_description ();
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return aarch64_read_description (0);
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}
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/* Implementation of `gdbarch_stap_is_single_operand', as defined in
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@ -70,6 +70,9 @@
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#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
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#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
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/* All possible aarch64 target descriptors. */
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struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1];
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/* The standard register names, and all the valid aliases for them. */
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static const struct
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{
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@ -2827,18 +2830,26 @@ aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
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return 1;
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}
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/* Get the correct target description. */
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/* Get the correct target description for the given VQ value.
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If VQ is zero then it is assumed SVE is not supported.
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(It is not possible to set VQ to zero on an SVE system). */
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const target_desc *
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aarch64_read_description ()
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aarch64_read_description (long vq)
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{
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static target_desc *aarch64_tdesc = NULL;
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target_desc **tdesc = &aarch64_tdesc;
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if (vq > AARCH64_MAX_SVE_VQ)
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error (_("VQ is %ld, maximum supported value is %d"), vq,
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AARCH64_MAX_SVE_VQ);
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if (*tdesc == NULL)
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*tdesc = aarch64_create_target_description ();
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struct target_desc *tdesc = tdesc_aarch64_list[vq];
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return *tdesc;
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if (tdesc == NULL)
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{
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tdesc = aarch64_create_target_description (vq);
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tdesc_aarch64_list[vq] = tdesc;
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}
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return tdesc;
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}
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/* Initialize the current architecture based on INFO. If possible,
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@ -2864,7 +2875,10 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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/* Ensure we always have a target descriptor. */
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if (!tdesc_has_registers (tdesc))
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tdesc = aarch64_read_description ();
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{
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/* SVE is not yet supported. */
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tdesc = aarch64_read_description (0);
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}
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gdb_assert (tdesc);
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@ -3072,7 +3086,7 @@ When on, AArch64 specific debugging is enabled."),
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selftests::register_test ("aarch64-process-record",
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selftests::aarch64_process_record_test);
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selftests::record_xml_tdesc ("aarch64.xml",
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aarch64_create_target_description ());
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aarch64_create_target_description (0));
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#endif
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}
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@ -75,7 +75,7 @@ struct gdbarch_tdep
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int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
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};
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const target_desc *aarch64_read_description ();
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const target_desc *aarch64_read_description (long vq);
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extern int aarch64_process_record (struct gdbarch *gdbarch,
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struct regcache *regcache, CORE_ADDR addr);
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@ -21,11 +21,12 @@
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#include "../features/aarch64-core.c"
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#include "../features/aarch64-fpu.c"
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#include "../features/aarch64-sve.c"
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/* Create the aarch64 target description. */
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/* See arch/aarch64.h. */
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target_desc *
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aarch64_create_target_description ()
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aarch64_create_target_description (long vq)
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{
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target_desc *tdesc = allocate_target_description ();
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@ -36,7 +37,11 @@ aarch64_create_target_description ()
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long regnum = 0;
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regnum = create_feature_aarch64_core (tdesc, regnum);
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regnum = create_feature_aarch64_fpu (tdesc, regnum);
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if (vq == 0)
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regnum = create_feature_aarch64_fpu (tdesc, regnum);
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else
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regnum = create_feature_aarch64_sve (tdesc, regnum, vq);
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return tdesc;
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}
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@ -22,7 +22,11 @@
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#include "common/tdesc.h"
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target_desc *aarch64_create_target_description ();
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/* Create the aarch64 target description. A non zero VQ value indicates both
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the presence of SVE and the Vector Quotient - the number of 128bit chunks in
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an SVE Z register. */
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target_desc *aarch64_create_target_description (long vq);
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/* Register numbers of various important registers. */
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enum aarch64_regnum
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@ -48,4 +52,7 @@ enum aarch64_regnum
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#define AARCH64_V_REGS_NUM 32
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#define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
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/* Maximum supported VQ value. Increase if required. */
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#define AARCH64_MAX_SVE_VQ 16
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#endif /* ARCH_AARCH64_H */
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@ -42137,6 +42137,10 @@ The @samp{org.gnu.gdb.aarch64.fpu} feature is optional. If present,
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it should contain registers @samp{v0} through @samp{v31}, @samp{fpsr},
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and @samp{fpcr}.
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The @samp{org.gnu.gdb.aarch64.sve} feature is optional. If present,
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it should contain registers @samp{z0} through @samp{z31}, @samp{p0}
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through @samp{p15}, @samp{ffr} and @samp{vg}.
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@node ARC Features
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@subsection ARC Features
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@cindex target descriptions, ARC Features
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@ -0,0 +1,158 @@
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/* Copyright (C) 2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common/tdesc.h"
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/* This function is NOT auto generated from xml. Create the aarch64 with SVE
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feature into RESULT, where SCALE is the number of 128 bit chunks in a Z
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register. */
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static int
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create_feature_aarch64_sve (struct target_desc *result, long regnum,
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int scale)
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{
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struct tdesc_feature *feature;
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tdesc_type *element_type, *field_type;
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tdesc_type_with_fields *type_with_fields;
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feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.sve");
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element_type = tdesc_named_type (feature, "ieee_double");
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tdesc_create_vector (feature, "svevdf", element_type, 2 * scale);
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element_type = tdesc_named_type (feature, "uint64");
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tdesc_create_vector (feature, "svevdu", element_type, 2 * scale);
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element_type = tdesc_named_type (feature, "int64");
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tdesc_create_vector (feature, "svevds", element_type, 2 * scale);
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element_type = tdesc_named_type (feature, "ieee_single");
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tdesc_create_vector (feature, "svevsf", element_type, 4 * scale);
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element_type = tdesc_named_type (feature, "uint32");
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tdesc_create_vector (feature, "svevsu", element_type, 4 * scale);
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element_type = tdesc_named_type (feature, "int32");
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tdesc_create_vector (feature, "svevss", element_type, 4 * scale);
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element_type = tdesc_named_type (feature, "uint16");
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tdesc_create_vector (feature, "svevhu", element_type, 8 * scale);
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element_type = tdesc_named_type (feature, "int16");
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tdesc_create_vector (feature, "svevhs", element_type, 8 * scale);
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element_type = tdesc_named_type (feature, "uint8");
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tdesc_create_vector (feature, "svevbu", element_type, 16 * scale);
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element_type = tdesc_named_type (feature, "int8");
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tdesc_create_vector (feature, "svevbs", element_type, 16 * scale);
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type_with_fields = tdesc_create_union (feature, "svevnd");
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field_type = tdesc_named_type (feature, "svevdf");
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tdesc_add_field (type_with_fields, "f", field_type);
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field_type = tdesc_named_type (feature, "svevdu");
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tdesc_add_field (type_with_fields, "u", field_type);
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field_type = tdesc_named_type (feature, "svevds");
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tdesc_add_field (type_with_fields, "s", field_type);
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type_with_fields = tdesc_create_union (feature, "svevns");
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field_type = tdesc_named_type (feature, "svevsf");
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tdesc_add_field (type_with_fields, "f", field_type);
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field_type = tdesc_named_type (feature, "svevsu");
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tdesc_add_field (type_with_fields, "u", field_type);
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field_type = tdesc_named_type (feature, "svevss");
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tdesc_add_field (type_with_fields, "s", field_type);
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type_with_fields = tdesc_create_union (feature, "svevnh");
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field_type = tdesc_named_type (feature, "svevhu");
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tdesc_add_field (type_with_fields, "u", field_type);
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field_type = tdesc_named_type (feature, "svevhs");
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tdesc_add_field (type_with_fields, "s", field_type);
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type_with_fields = tdesc_create_union (feature, "svevnb");
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field_type = tdesc_named_type (feature, "svevbu");
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tdesc_add_field (type_with_fields, "u", field_type);
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field_type = tdesc_named_type (feature, "svevbs");
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tdesc_add_field (type_with_fields, "s", field_type);
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type_with_fields = tdesc_create_union (feature, "svev");
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field_type = tdesc_named_type (feature, "svevnd");
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tdesc_add_field (type_with_fields, "d", field_type);
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field_type = tdesc_named_type (feature, "svevns");
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tdesc_add_field (type_with_fields, "s", field_type);
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field_type = tdesc_named_type (feature, "svevnh");
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tdesc_add_field (type_with_fields, "h", field_type);
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field_type = tdesc_named_type (feature, "svevnb");
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tdesc_add_field (type_with_fields, "b", field_type);
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field_type = tdesc_named_type (feature, "uint8");
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tdesc_create_vector (feature, "svep", field_type, 2 * scale);
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tdesc_create_reg (feature, "z0", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z1", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z2", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z3", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z4", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z5", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z6", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z7", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z8", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z9", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z10", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z11", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z12", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z13", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z14", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z15", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z16", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z17", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z18", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z19", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z20", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z21", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z22", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z23", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z24", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z25", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z26", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z27", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z28", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z29", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z30", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "z31", regnum++, 1, NULL, 128 * scale, "svev");
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tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "p0", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p1", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p2", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p3", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p4", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p5", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p6", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p7", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p8", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p9", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p10", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p11", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p12", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p13", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p14", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "p15", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "ffr", regnum++, 1, NULL, 16 * scale, "svep");
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tdesc_create_reg (feature, "vg", regnum++, 1, NULL, 64, "int");
|
||||
return regnum;
|
||||
}
|
||||
|
|
@ -1,3 +1,8 @@
|
|||
2018-05-31 Alan Hayward <alan.hayward@arm.com>
|
||||
|
||||
* linux-aarch64-tdesc.c (aarch64_linux_read_description): Add
|
||||
null VQ.
|
||||
|
||||
2018-05-25 Maciej W. Rozycki <macro@mips.com>
|
||||
|
||||
* gdb.arch/mips-fpregset-core.exp: New test.
|
||||
|
|
|
|||
|
|
@ -32,7 +32,8 @@ aarch64_linux_read_description ()
|
|||
|
||||
if (*tdesc == NULL)
|
||||
{
|
||||
*tdesc = aarch64_create_target_description ();
|
||||
/* SVE not yet supported. */
|
||||
*tdesc = aarch64_create_target_description (0);
|
||||
|
||||
static const char *expedite_regs_aarch64[] = { "x29", "sp", "pc", NULL };
|
||||
init_target_desc (*tdesc, expedite_regs_aarch64);
|
||||
|
|
|
|||
Loading…
Reference in New Issue