* sim/cris/asm/testutils.inc (test_move_cc): Add missing call to
test_cc. * sim/cris/asm/asr.ms: Correct expected condition code flags. * sim/cris/asm/boundr.ms: Ditto. * sim/cris/asm/dstep.ms: Ditto. * sim/cris/asm/lsr.ms: Ditto. * sim/cris/asm/movecr.ms: Ditto. * sim/cris/asm/mover.ms: Ditto. * sim/cris/asm/neg.ms: Ditto. Use test_cc, not test_move_cc. * sim/cris/asm/op3.ms: Check the condition code flags after the insn under test. * sim/cris/asm/movecrt10.ms: Update expected number of simulated cycles. * sim/cris/asm/movecrt32.ms: Ditto. * sim/cris/asm/jsr.ms: Don't use local label 8. * sim/cris/asm/nonvcv32.ms: New test.
This commit is contained in:
Hans-Peter Nilsson
parent
57ee890f2f
commit
9538c15c36
@ -1,3 +1,23 @@
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2007-10-22 Edgar E. Iglesias <edgar@axis.com>
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Hans-Peter Nilsson <hp@axis.com>
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* sim/cris/asm/testutils.inc (test_move_cc): Add missing call to
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test_cc.
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* sim/cris/asm/asr.ms: Correct expected condition code flags.
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* sim/cris/asm/boundr.ms: Ditto.
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* sim/cris/asm/dstep.ms: Ditto.
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* sim/cris/asm/lsr.ms: Ditto.
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* sim/cris/asm/movecr.ms: Ditto.
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* sim/cris/asm/mover.ms: Ditto.
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* sim/cris/asm/neg.ms: Ditto. Use test_cc, not test_move_cc.
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* sim/cris/asm/op3.ms: Check the condition code flags after the insn
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under test.
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* sim/cris/asm/movecrt10.ms: Update expected number of simulated
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cycles.
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* sim/cris/asm/movecrt32.ms: Ditto.
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* sim/cris/asm/jsr.ms: Don't use local label 8.
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* sim/cris/asm/nonvcv32.ms: New test.
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2007-10-11 Jesper Nilsson <jesper.nilsson@axis.com>
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* sim/cris/c/freopen2.c: Added testcase.
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@ -205,13 +205,13 @@
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move.d 0x5a67f19f,r3
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moveq 12,r4
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asr.b r4,r3
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test_move_cc 0 0 0 0
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test_move_cc 1 0 0 0
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dumpr3 ; 5a67f1ff
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move.d 0x5a67f19f,r3
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moveq 4,r4
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asr.b r4,r3
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test_move_cc 0 0 0 0
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test_move_cc 1 0 0 0
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dumpr3 ; 5a67f1f9
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move.d 0x5a67f19f,r3
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@ -24,7 +24,7 @@
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moveq -1,r4
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move.d r4,r3
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bound.d r4,r3
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test_move_cc 0 0 0 0
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test_move_cc 1 0 0 0
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dumpr3 ; ffffffff
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move.d 0x5432f789,r4
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@ -30,7 +30,7 @@
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move.d 0x5432f789,r4
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move.d 0x78134452,r3
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dstep r4,r3
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test_move_cc 0 0 0 0
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test_move_cc 1 0 0 0
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dumpr3 ; 9bf3911b
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move.d 0xffff,r3
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@ -41,7 +41,8 @@ x:
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nop
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quit
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8:
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; Can't use local label 8 or 9, as they're used by test_move_cc.
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y:
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move srp,r3
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sub.d 7b,r3
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dumpr3
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@ -78,7 +79,7 @@ x:
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move srp,r3
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sub.d 7b,r3
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dumpr3
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jump 8b
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jump y
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.if ..asm.arch.cris.v32
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nop
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.endif
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@ -127,7 +127,7 @@
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moveq -1,r3
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moveq 31,r4
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lsr.w r4,r3
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test_move_cc 0 0 0 0
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test_move_cc 0 1 0 0
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dumpr3 ; ffff0000
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moveq -1,r3
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@ -13,12 +13,12 @@
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moveq 0,r3
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move.b 0x94,r3
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test_move_cc 0 0 0 0
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test_move_cc 1 0 0 0
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dumpr3
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moveq -1,r3
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move.w 0x4321,r3
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test_move_cc 1 0 0 0
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test_move_cc 0 0 0 0
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dumpr3
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moveq 0,r3
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@ -1,6 +1,6 @@
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#mach: crisv10
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#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
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#output: Basic clock cycles, total @: 22\n
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#output: Basic clock cycles, total @: 82\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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@ -1,6 +1,6 @@
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#mach: crisv32
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#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
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#output: Basic clock cycles, total @: 22\n
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#output: Basic clock cycles, total @: 82\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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@ -8,7 +8,7 @@
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moveq -30,r3
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moveq 5,r4
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move.b r4,r3
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test_move_cc 1 0 0 0
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test_move_cc 0 0 0 0
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dumpr3
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move.w r4,r3
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@ -6,97 +6,97 @@
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moveq 0,r3
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moveq 1,r4
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neg.d r4,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ffffffff
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moveq 1,r3
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moveq 0,r4
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neg.d r3,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ffffffff
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moveq 0,r3
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neg.d r3,r3
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test_move_cc 0 0 1 0
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test_cc 0 1 0 0
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dumpr3 ; 0
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move.d 0x80000000,r3
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neg.d r3,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 1 1
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dumpr3 ; 80000000
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moveq -1,r3
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neg.d r3,r3
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test_move_cc 0 0 0 0
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test_cc 0 0 0 1
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dumpr3 ; 1
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move.d 0x456789ab,r3
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neg.d r3,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ba987655
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moveq 0,r3
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moveq 1,r4
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neg.w r4,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ffff
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moveq 1,r3
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moveq 0,r4
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neg.w r3,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ffff
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moveq 0,r3
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neg.w r3,r3
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test_move_cc 0 0 1 0
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test_cc 0 1 0 0
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dumpr3 ; 0
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move.d 0x89ab8000,r3
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neg.w r3,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 1 1
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dumpr3 ; 89ab8000
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moveq -1,r3
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neg.w r3,r3
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test_move_cc 0 0 0 0
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test_cc 0 0 0 1
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dumpr3 ; ffff0001
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move.d 0x456789ab,r3
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neg.w r3,r3
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test_move_cc 0 0 0 0
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test_cc 0 0 0 1
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dumpr3 ; 45677655
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moveq 0,r3
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moveq 1,r4
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neg.b r4,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ff
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moveq 1,r3
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moveq 0,r4
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neg.b r3,r3
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test_move_cc 1 0 0 0
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test_cc 1 0 0 1
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dumpr3 ; ff
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moveq 0,r3
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neg.b r3,r3
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test_move_cc 0 0 1 0
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test_cc 0 1 0 0
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dumpr3 ; 0
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move.d 0x89abae80,r3
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neg.b r3,r3
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test_move_cc 0 0 1 0
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test_cc 1 0 1 1
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dumpr3 ; 89abae80
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moveq -1,r3
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neg.b r3,r3
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test_move_cc 0 0 0 0
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test_cc 0 0 0 1
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dumpr3 ; ffffff01
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move.d 0x456789ab,r3
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neg.b r3,r3
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test_move_cc 0 0 0 0
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test_cc 0 0 0 1
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dumpr3 ; 45678955
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quit
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167
sim/testsuite/sim/cris/asm/nonvcv32.ms
Normal file
167
sim/testsuite/sim/cris/asm/nonvcv32.ms
Normal file
@ -0,0 +1,167 @@
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# mach: crisv32
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.include "testutils.inc"
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; Check for various non-arithmetic insns that C and V are not affected
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; on v32 (where they were on v10), as the generic tests don't cover
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; that; they are cleared before testing.
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; First, a macro testing that VC are unaffected, not counting previous
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; register contents.
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.macro nonvc0 insn op
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move.d $r0,$r3
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setf vc
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.ifnc \insn,swapnwbr
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\insn \op,$r3
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.else
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\insn $r3
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.endif
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bcc 9f
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nop
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bvc 9f
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nop
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move.d $r0,$r3
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clearf vc
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.ifnc \insn,swapnwbr
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\insn \op,$r3
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.else
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\insn $r3
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.endif
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bcs 9f
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nop
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bvc 8f
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nop
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9:
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fail
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8:
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.endm
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; Use the above, but initialize the non-parameter operand to a value.
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.macro nonvc1 insn val op
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move.d \val,$r0
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nonvc0 \insn,\op
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.endm
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; Use the above, iterating over various values.
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.macro nonvc2 insn op
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.irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
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nonvc1 \insn,\p,\op
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nonvc1 \insn,-\p,\op
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.endr
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.endm
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.macro nonvc2q insn op min=-63 max=63
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.if \op >= \min &&&& \op <= \max
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nonvc2 \insn,\op
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.endif
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.endm
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; The above, for each .b .w .d insn variant.
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.macro nonvcbwd insn op
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.irp s,.b,.w,.d
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nonvc2 \insn\s,\op
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.endr
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.endm
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; For various insns with register, dword constant and memory operands.
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.macro nonvcitermcd op=[$r4]
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nonvc2 and.d,\op
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nonvc2 move.d,\op
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nonvc2 or.d,\op
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.endm
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; Similar, for various insns with register, word constant and memory operands.
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.macro nonvcitermcw op=[$r4]
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nonvcitermcd \op
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nonvc2 and.w,\op
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nonvc2 move.w,\op
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nonvc2 or.w,\op
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nonvc2 movs.w,\op
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nonvc2 movu.w,\op
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.endm
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; Similar, for various insns with register, byte constant and memory operands.
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.macro nonvcitermcb op=[$r4]
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nonvcitermcw \op
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nonvc2 and.b,\op
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nonvc2 move.b,\op
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nonvc2 or.b,\op
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nonvc2 movs.b,\op
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nonvc2 movu.b,\op
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.endm
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; Similar, for insns with quick constant operands.
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.macro nonvciterq op
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nonvcitermcb \op
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nonvc2 bound.b,\op
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nonvc2q andq,\op,min=-32,max=31
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nonvc2q asrq,\op,min=0,max=31
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nonvc2q lsrq,\op,min=0,max=31
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nonvc2q orq,\op,min=-32,max=31
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nonvc2q moveq,\op,min=-32,max=31
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.endm
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; Similar, for insns with register operands.
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.macro nonvciterr op
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nonvcitermcb \op
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nonvcbwd bound,\op
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nonvc2 abs,\op
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nonvcbwd asr,\op
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nonvc2 dstep,\op
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nonvcbwd lsr,\op
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nonvcbwd lsl,\op
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nonvc2 lz,\op
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nonvc2 swapnwbr
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nonvc2 xor,\op
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.endm
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; Test all applicable constant, register and memory variants of a value.
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.macro tst op
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; Constants
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.if (\op <= 31 &&&& \op >= -32)
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nonvciterq \op
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.elseif (\op <= 255 &&&& \op >= -128)
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nonvcitermcb \op
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nonvcbwd bound,\op
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.elseif (\op <= 65535 &&&& \op >= -32767)
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nonvcitermcw \op
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nonvc2 bound.w,\op
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nonvc2 bound.d,\op
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.else
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nonvcitermcd \op
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nonvc2 bound.d,\op
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.endif
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; Registers
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move.d \op,$r4
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nonvciterr $r4
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; Memory
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nonvcitermcb [$r5]
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addq 4,$r5
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.section .rodata
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.dword \op
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.previous
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.endm
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; As above but negation too.
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.macro tstpm op
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tst \op
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tst -\op
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.endm
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; Set up for the actual test.
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start
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move.d c0,$r5
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.section .rodata
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c0:
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.previous
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; Finally, test.
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.irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
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tstpm \x
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.endr
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pass
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@ -43,8 +43,8 @@ x:
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moveq 0,r5
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bdap 2,r10
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test_move_cc 0 0 0 0
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movu.b [r3],r5
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test_move_cc 0 0 0 0
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dumpr3 ; aa
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move.d 0x42435567,r8
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@ -277,7 +277,13 @@ _start:
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.macro test_move_cc N Z V C
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.if ..asm.arch.cris.v32
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; V and C aren't affected on v32, so to re-use the test-cases,
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; we fake them cleared. There's a separate test, nonvcv32.ms
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; covering this omission.
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clearf vc
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test_cc \N \Z 0 0
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.else
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test_cc \N \Z \V \C
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.endif
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.endm
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|
||||
|
||||
Loading…
Reference in New Issue
Block a user