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PR24390, Don't decode mtfsb field as a cr field 

"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.

	PR 24390
include/
	* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
	* ppc-opc.c (BTF): Define.
	(powerpc_opcodes): Use for mtfsb*.
	* ppc-dis.c (print_insn_powerpc): Print fields with both
	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
	* testsuite/gas/ppc/476.d: Update mtfsb*.
	* testsuite/gas/ppc/a2.d: Likewise.
This commit is contained in:
Alan Modra 2019-03-28 10:36:55 +10:30
parent 0720291713
commit 96a86c01d1
8 changed files with 43 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
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@ -1,3 +1,9 @@
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
2019-03-21 Alan Modra <amodra@gmail.com>
* emul.h (struct emulation): Delete strip_underscore.

8
gas/testsuite/gas/ppc/476.d
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@ -315,10 +315,10 @@ Disassembly of section \.text:
4c4: (7d 10 6b 86|86 6b 10 7d) mtdcr 432,r8
4c8: (7c 83 03 46|46 03 83 7c) mtdcrux r3,r4
4cc: (7c e6 03 06|06 03 e6 7c) mtdcrx r6,r7
4d0: (fc 60 00 8c|8c 00 60 fc) mtfsb0 so
4d4: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. so
4d8: (fc 60 00 4c|4c 00 60 fc) mtfsb1 so
4dc: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. so
4d0: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
4d4: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. 3
4d8: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
4dc: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. 3
4e0: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
4e4: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
4e8: (fc 0d 55 8e|8e 55 0d fc) mtfsf 6,f10,0,1

8
gas/testsuite/gas/ppc/a2.d
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@ -372,10 +372,10 @@ Disassembly of section \.text:
560: (7d 4a 3b 86|86 3b 4a 7d) mtdcr 234,r10
564: (7d 6a 03 07|07 03 6a 7d) mtdcrx\. r10,r11
568: (7d 6a 03 06|06 03 6a 7d) mtdcrx r10,r11
56c: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. so
570: (fc 60 00 8c|8c 00 60 fc) mtfsb0 so
574: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. so
578: (fc 60 00 4c|4c 00 60 fc) mtfsb1 so
56c: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. 3
570: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
574: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. 3
578: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
57c: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
580: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
584: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20

5
include/ChangeLog
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@ -1,3 +1,8 @@
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* dis-asm.h (struct disassemble_info): Add stop_offset.

5
include/opcode/ppc.h
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@ -354,7 +354,10 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_CR_BIT (0x20)
/* This is a CR FIELD that does not use symbolic names (unless
-mregnames is in effect). */
-mregnames is in effect). If both PPC_OPERAND_CR_BIT and
PPC_OPERAND_CR_REG are set then treat the field as per
PPC_OPERAND_CR_BIT for assembly, but as if neither of these
bits are set for disassembly. */
#define PPC_OPERAND_CR_REG (0x40)
/* This operand names a special purpose register. */

8
opcodes/ChangeLog
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@ -1,3 +1,11 @@
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.

4
opcodes/ppc-dis.c
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@ -779,10 +779,12 @@ print_insn_powerpc (bfd_vma memaddr,
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
(*info->fprintf_func) (info->stream, "%" PRId64, value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (operand->flags & PPC_OPERAND_CR_BIT) == 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
(*info->fprintf_func) (info->stream, "cr%" PRId64, value);
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
&& (operand->flags & PPC_OPERAND_CR_REG) == 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
{

14
opcodes/ppc-opc.c
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@ -1837,8 +1837,12 @@ const struct powerpc_operand powerpc_operands[] =
#define BT BH + 1
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
/* The BT field in a mtfsb0 or mtfsb1 instruction. */
#define BTF BT + 1
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG },
/* The BI16 field in a BD8 form instruction. */
#define BI16 BT + 1
#define BI16 BTF + 1
{ 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
/* The BI32 field in a BD15 form instruction. */
@ -7381,8 +7385,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BTF}},
{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BTF}},
{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
@ -7395,8 +7399,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
{"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BTF}},
{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BTF}},
{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},