[PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (coprocessor_opcodes): Move NEON VDUP from here... (neon_opcodes): ... to here. (mve_opcodes): Add new instructions. (print_mve_undefined): Handle new reasons. (print_mve_unpredictable): Likewise. (print_mve_size): Handle new instructions. (print_insn_neon): Handle vdup. (print_insn_mve): Handle new operands.
This commit is contained in:
Andre Vieira
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143275ea7e
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9743db035e
@ -1,3 +1,21 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_unpredictable): Add new reasons.
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(enum mve_undefined): Likewise.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(coprocessor_opcodes): Move NEON VDUP from here...
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(neon_opcodes): ... to here.
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(mve_opcodes): Add new instructions.
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(print_mve_undefined): Handle new reasons.
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(print_mve_unpredictable): Likewise.
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(print_mve_size): Handle new instructions.
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(print_insn_neon): Handle vdup.
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(print_insn_mve): Handle new operands.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -87,6 +87,17 @@ enum mve_instructions
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MVE_VCMP_VEC_T4,
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MVE_VCMP_VEC_T5,
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MVE_VCMP_VEC_T6,
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MVE_VDUP,
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MVE_VEOR,
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MVE_VFMAS_FP_SCALAR,
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MVE_VFMA_FP_SCALAR,
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MVE_VFMA_FP,
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MVE_VFMS_FP,
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MVE_VHADD_T1,
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MVE_VHADD_T2,
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MVE_VHSUB_T1,
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MVE_VHSUB_T2,
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MVE_VRHADD,
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MVE_NONE
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};
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@ -98,11 +109,13 @@ enum mve_unpredictable
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fcB = 1 (vpt). */
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UNPRED_R13, /* Unpredictable because r13 (sp) or
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r15 (sp) used. */
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UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
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UNPRED_NONE /* No unpredictable behavior. */
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};
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enum mve_undefined
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{
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_NONE /* no undefined behavior. */
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};
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@ -539,18 +552,6 @@ static const struct sopcode32 coprocessor_opcodes[] =
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0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
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/* Data transfer between ARM and NEON registers. */
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
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{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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@ -1151,6 +1152,20 @@ static const struct opcode32 neon_opcodes[] =
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0xf2b00000, 0xffb00810,
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"vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
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/* Data transfer between ARM and NEON registers. */
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
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/* Move data element to all lanes. */
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
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0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
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@ -1803,10 +1818,12 @@ static const struct opcode32 neon_opcodes[] =
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%% %
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%c print condition code
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%i print MVE predicate(s) for vpt and vpst
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%n print vector comparison code for predicated instruction
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%v print vector predicate for instruction in predicated
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block
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%<bitfield>r print as an ARM register
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%<bitfield>Q print as a MVE Q register
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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UNPREDICTABLE
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@ -1908,6 +1925,78 @@ static const struct mopcode32 mve_opcodes[] =
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0xfe011f40, 0xffc1ff50,
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"vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
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/* Vector VDUP. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VDUP,
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0xeea00b10, 0xffb10f5f,
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"vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
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/* Vector VEOR. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VEOR,
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0xff000150, 0xffd11f51,
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"veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VFMA, vector * scalar. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VFMA_FP_SCALAR,
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0xee310e40, 0xefb11f70,
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"vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VFMA floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VFMA_FP,
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0xef000c50, 0xffa11f51,
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"vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VFMS floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VFMS_FP,
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0xef200c50, 0xffa11f51,
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"vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VFMAS, vector * scalar. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VFMAS_FP_SCALAR,
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0xee311e40, 0xefb11f70,
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"vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VHADD T1. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VHADD_T1,
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0xef000040, 0xef811f51,
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"vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VHADD T2. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VHADD_T2,
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0xee000f40, 0xef811f70,
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"vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VHSUB T1. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VHSUB_T1,
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0xef000240, 0xef811f51,
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"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VHSUB T2. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VHSUB_T2,
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0xee001f40, 0xef811f70,
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"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VDUP. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VDUP,
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0xeea00b10, 0xffb10f5f,
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"vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
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/* Vector VRHADD. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRHADD,
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0xef000140, 0xef811f51,
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"vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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{ARM_FEATURE_CORE_LOW (0),
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MVE_NONE,
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0x00000000, 0x00000000, 0}
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@ -3913,6 +4002,8 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VHADD_T2:
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case MVE_VHSUB_T2:
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case MVE_VCMP_VEC_T1:
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case MVE_VCMP_VEC_T2:
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case MVE_VCMP_VEC_T3:
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@ -3940,7 +4031,31 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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{
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*undefined_code = UNDEF_NONE;
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return FALSE;
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switch (matched_insn)
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{
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case MVE_VDUP:
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if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VRHADD:
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case MVE_VHADD_T1:
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case MVE_VHSUB_T1:
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if (arm_decode_field (given, 20, 21) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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}
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/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
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@ -3980,6 +4095,43 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VDUP:
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{
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unsigned long gpr = arm_decode_field (given, 12, 15);
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if (gpr == 0xd)
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{
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*unpredictable_code = UNPRED_R13;
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return TRUE;
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}
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else if (gpr == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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return FALSE;
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}
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case MVE_VFMA_FP_SCALAR:
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case MVE_VFMAS_FP_SCALAR:
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case MVE_VHADD_T2:
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case MVE_VHSUB_T2:
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{
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unsigned long gpr = arm_decode_field (given, 0, 3);
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if (gpr == 0xd)
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{
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*unpredictable_code = UNPRED_R13;
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return TRUE;
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}
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else if (gpr == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -3996,6 +4148,10 @@ print_mve_undefined (struct disassemble_info *info,
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switch (undefined_code)
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{
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case UNDEF_SIZE_3:
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func (stream, "size equals three");
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break;
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case UNDEF_NONE:
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break;
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}
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@ -4025,6 +4181,10 @@ print_mve_unpredictable (struct disassemble_info *info,
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func (stream, "use of r13 (sp)");
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break;
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case UNPRED_R15:
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func (stream, "use of r15 (pc)");
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break;
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case UNPRED_NONE:
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break;
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}
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@ -4058,12 +4218,17 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VCMP_VEC_T4:
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case MVE_VCMP_VEC_T5:
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case MVE_VCMP_VEC_T6:
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case MVE_VHADD_T1:
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case MVE_VHADD_T2:
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case MVE_VHSUB_T1:
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case MVE_VHSUB_T2:
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case MVE_VPT_VEC_T1:
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case MVE_VPT_VEC_T2:
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case MVE_VPT_VEC_T3:
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case MVE_VPT_VEC_T4:
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case MVE_VPT_VEC_T5:
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case MVE_VPT_VEC_T6:
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case MVE_VRHADD:
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if (size <= 3)
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func (stream, "%s", mve_vec_sizename[size]);
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else
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@ -4072,6 +4237,10 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VCMP_FP_T1:
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case MVE_VCMP_FP_T2:
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case MVE_VFMA_FP_SCALAR:
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case MVE_VFMA_FP:
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case MVE_VFMS_FP:
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case MVE_VFMAS_FP_SCALAR:
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case MVE_VPT_FP_T1:
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case MVE_VPT_FP_T2:
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if (size == 0)
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@ -4080,6 +4249,23 @@ print_mve_size (struct disassemble_info *info,
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func (stream, "16");
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break;
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case MVE_VDUP:
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switch (size)
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{
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case 0:
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func (stream, "32");
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break;
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case 1:
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func (stream, "16");
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break;
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case 2:
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func (stream, "8");
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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@ -5018,7 +5204,8 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
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}
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else if ((given & 0xff000000) == 0xf9000000)
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given ^= 0xf9000000 ^ 0xf4000000;
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else
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/* vdup is also a valid neon instruction. */
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else if ((given & 0xff910f5f) != 0xee800b10)
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return FALSE;
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}
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@ -5557,6 +5744,9 @@ print_insn_mve (struct disassemble_info *info, long given)
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value,
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insn->mve_op);
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break;
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case 'r':
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func (stream, "%s", arm_regnames[value]);
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break;
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case 'Q':
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if (value & 0x8)
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func (stream, "<illegal reg q%ld.5>", value);
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