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opcodes/nfp: Fix disassembly of crc[] with swapped operands.

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The decoding of the CRC operation in alu instructions was using bits
from the instruction word directly, instead of srcA which would be
different if the swap bit was set.

Signed-off-by: Francois H. Theron <francois.theron@netronome.com>
This commit is contained in:
Francois H. Theron 2018-11-13 12:33:16 +02:00
parent 497d849d28
commit 97b3f39201
5 changed files with 43 additions and 10 deletions
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5
binutils/ChangeLog
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@ -1,3 +1,8 @@
2018-11-13 Francois H. Theron <francois.theron@netronome.com>
* testsuite/binutils-all/nfp/test1.d: Test for swapped operand crc[].
2018-11-09 Hafiz Abid Qadeer <abidh@codesourcery.com>
* configure: Regenerate.

32
binutils/testsuite/binutils-all/nfp/test1.d
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@ -484,8 +484,20 @@ Disassembly of section \.text\.i32\.me0:
ee0: 000000f0000c0300 \.476 nop
ee8: 000000f0000c0300 \.477 nop
ef0: 000000f0000c0300 \.478 nop
ef8: 000220e000020000 \.479 ctx_arb\[bpt\]
f00: 000420e000010000 \.480 ctx_arb\[kill\]
ef8: 000060a900301340 \.479 crc_be\[crc_ccitt, gprA_3, gprB_4\]
f00: 000000f0000c0300 \.480 nop
f08: 000e20b9403d0004 \.481 crc_be\[crc_ccitt, gprB_3, gprA_4\]
f10: 000000f0000c0300 \.482 nop
f18: 000400a900301348 \.483 crc_le\[crc_ccitt, gprA_3, gprB_4\]
f20: 000000f0000c0300 \.484 nop
f28: 000400b9403d2004 \.485 crc_le\[crc_ccitt, gprB_3, gprA_4\]
f30: 000000f0000c0300 \.486 nop
f38: 0002e0b900301348 \.487 crc_le\[crc_ccitt, gprB_3, gprB_4\]
f40: 000000f0000c0300 \.488 nop
f48: 0002e0a9403d2004 \.489 crc_le\[crc_ccitt, gprA_3, gprA_4\]
f50: 000000f0000c0300 \.490 nop
f58: 000220e000020000 \.491 ctx_arb\[bpt\]
f60: 000420e000010000 \.492 ctx_arb\[kill\]
Disassembly of section \.text\.i33\.me9:
@ -969,5 +981,17 @@ Disassembly of section \.text\.i33\.me9:
ee0: 000000f0000c0300 \.476 nop
ee8: 000000f0000c0300 \.477 nop
ef0: 000000f0000c0300 \.478 nop
ef8: 000220e000020000 \.479 ctx_arb\[bpt\]
f00: 000420e000010000 \.480 ctx_arb\[kill\]
ef8: 000060a900301340 \.479 crc_be\[crc_ccitt, gprA_3, gprB_4\]
f00: 000000f0000c0300 \.480 nop
f08: 000e20b9403d0004 \.481 crc_be\[crc_ccitt, gprB_3, gprA_4\]
f10: 000000f0000c0300 \.482 nop
f18: 000400a900301348 \.483 crc_le\[crc_ccitt, gprA_3, gprB_4\]
f20: 000000f0000c0300 \.484 nop
f28: 000400b9403d2004 \.485 crc_le\[crc_ccitt, gprB_3, gprA_4\]
f30: 000000f0000c0300 \.486 nop
f38: 0002e0b900301348 \.487 crc_le\[crc_ccitt, gprB_3, gprB_4\]
f40: 000000f0000c0300 \.488 nop
f48: 0002e0a9403d2004 \.489 crc_le\[crc_ccitt, gprA_3, gprA_4\]
f50: 000000f0000c0300 \.490 nop
f58: 000220e000020000 \.491 ctx_arb\[bpt\]
f60: 000420e000010000 \.492 ctx_arb\[kill\]

BIN
binutils/testsuite/binutils-all/nfp/test1_nfp6000.nffw
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4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2018-11-13 Francois H. Theron <francois.theron@netronome.com>
* nfp-dis.c: Fix crc[] disassembly if operands are swapped.
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entries for

12
opcodes/nfp-dis.c
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@ -1325,8 +1325,8 @@ nfp_me27_28_print_alu (uint64_t instr, unsigned int pred_cc,
case 18:
do_close_bracket = 0;
dinfo->fprintf_func (dinfo->stream, "crc_%s[",
_BTST (instr, 3) ? "le" : "be");
if (!nfp_me27_28_crc_op[_BF (instr, 7, 5)])
_BTST (srcA, 3) ? "le" : "be");
if (!nfp_me27_28_crc_op[_BF (srcA, 7, 5)])
{
dinfo->fprintf_func (dinfo->stream, _(", <invalid CRC operator>, "));
err = TRUE;
@ -1334,7 +1334,7 @@ nfp_me27_28_print_alu (uint64_t instr, unsigned int pred_cc,
else
{
dinfo->fprintf_func (dinfo->stream, "%s, ",
nfp_me27_28_crc_op[_BF (instr, 7, 5)]);
nfp_me27_28_crc_op[_BF (srcA, 7, 5)]);
}
/* Dest operand. */
@ -1351,10 +1351,10 @@ nfp_me27_28_print_alu (uint64_t instr, unsigned int pred_cc,
num_ctx, src_lmext, dinfo);
dinfo->fprintf_func (dinfo->stream, "]");
if (_BF (instr, 2, 0))
if (_BF (srcA, 2, 0))
dinfo->fprintf_func (dinfo->stream, ", %s",
nfp_me27_28_crc_bytes[_BF (instr, 2, 0)]);
if (_BTST (instr, 4))
nfp_me27_28_crc_bytes[_BF (srcA, 2, 0)]);
if (_BTST (srcA, 4))
dinfo->fprintf_func (dinfo->stream, ", bit_swap");
break;